Description
V360EPC provides the highest performance, most flexible, and most economical method to directly connect i960Cx/Hx or AMD2930/40 processors to the PCI bus. As a generic solution for 32-bit de-multiplexed local bus applications, V360EPC is also a suitable candidate for a variety of high-performance applications based on Motorola, IBM, DEC and Hitachi embedded processors – where a minimal amount of glue logic is needed.
• Glueless interface to i960Cx/Hx and AMD29030/40 processors
• Configurable for primary master, bus master or target operation.
• Type 0 and type 1 configuration cycles.
• Up to 1Kbyte burst access on PCI or local.
• Large, 640-byte FIFOs using V3’s unique DYNAMIC BANDWIDTH ALLOCATION™ architecture
• 64-byte read FIFO per aperture.
• Enhanced support for 8/16-bit local bus devices with programmable region sizes.
• 3.3 volt support
• Dual bi-directional address space remapping
• Fully compliant with PCI 2.1 specification
• On-the-fly byte order (endian) conversion
• I2O ATU and messaging unit including hardware controlled circular queues
• 2 channel DMA controller plus multiprocessor DMA chaining and demand mode DMA
• Hot swapping capability
• 16 8-bit bi-directional mailbox registers with doorbell interrupts
• Flexible PCI and local interrupt management
• Optional power-on serial EEPROM initialization
• 33MHz and 50MHz local bus versions
• Industrials Temperature Grade -40 to +85’C
• Low cost 160-pin EIAJ PQFP package
V360EPC provides the hi g hest performance, most flexible, and most economical method to directl y connect i960Cx/Hx or AMD2930/40 processors to the PCI bus. As a g eneric solution for 32-bit de-multiplexed local bus applications, V360EPC is also a suitable candidate for a variet y of hi g h-performance applications based on Motorola, IBM, DEC and Hitachi embedded processors – where a minimal amount of g lue lo g ic is needed.
V3-SEMI – V3 SEMI V360EPC-50 REV A1
Glueless interface to i960Cx/Hx and AMD29030/40 processors Configurable for primary master, bus master or target operation. Type 0 and type 1 configuration cycles. to 1Kbyte burst access on PCI or local. Large, 640-byte FIFOs using V3’s unique DYNAMIC BANDWIDTH ALLOCATIONTM architecture 64-byte read FIFO per aperture. Enhanced support for 8/16-bit local bus devices with programmable region sizes. 3.3 volt support Dual bi-directional address space remapping Fully compliant with PCI 2.1 specification V360EPC provides the highest performance, most flexible, and most economical method to directly connect or AMD2930/40 processors to the PCI bus. As a generic solution for 32-bit de-multiplexed local bus applications, V360EPC is also a suitable candidate for a variety of high-performance applications based on Motorola, IBM, DEC and Hitachi embedded processors – where a minimal amount of glue logic is needed. V360EPC is the second generation V3’s I2O ready PCI bridges – fully backward compatible with V962PBC and V292PBC Rev B2 devices and is supporting powerful features like Hot Swap and DMA chaining. The PCI bus can be run at full 33MHz, independent of local bus clock rate. The overall throughput of the system is dramatically improved by increasing the FIFO
Manufacturer:Electronic Components
Datasheet:V360EPC-QuickLogic.pdf
