FEATURES:
Pin Configuration
Logic Block Diagram
Pin Description
DESCRIPTION:
Potato Semiconductor’s PO74G374A is designed for
world top performance using submicron CMOS
technology to achieve higher than
600MHz
TTL
/CMOS output frequency with less than 2.4ns
propagation delay.
This dual Octal edge triggered D-type flip-flops are
designed for 1.65-V to 3.6-V V
CC
operation.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2D
2Q
3Q
3D
4D
1D 1Q OE
5Q 5D
8Q
4Q
GND CLK
V
CC
8D
7D
7Q
6Q
6D
INPUTS
OUTPUT
Q
OE
CLK
D
L
H
H
L
L
L
L
H or L
X
Q
0
H
X
X
Z
OE
To Seven Other Channels
1
11
3
2
CLK
1D
C1
1D
1Q
. Patented technology
. Specified From –40°C to 85°C, –40°C to 125°C,
and –55°C to 125°C
. Operating frequency is faster than 600MHz
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 2.4ns max with 15pf load
. Low input capacitance: 4pf typical
. Latch-Up Performance Exceeds 250 mA Per
JESD 17
. ESD Protection Exceeds JESD 22
. 5000-VHuman-BodyModel (A114-A)
. 200-VMachineModel (A115-A)
. Available in 20pin TSSOP package
. Available in 20pin Ceramic Dual Flatpack
. Available in 20pin Leadless Ceramic Chip Carrier
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
54 & 74 Series Noise Cancellation GHz Logic
1
01/01/10
Potato Semiconductor Corporation
PO54G374A, PO74G374A
www.potatosemi.com