Rabbit-3000-html.html

Rabbit 3000 Microprocessor User’s Manual

3.4.5 Atomic Moves from Memory to I/O Space ............................................................................... 43

3.5 Interrupt Structure .............................................................................................................................. 44

Chapter 4. Rabbit Capabilities

4.1 Precisely Timed Output Pulses .......................................................................................................... 49

4.1.1 Pulse Width Modulation to Reduce Relay Power ..................................................................... 50

4.2 Open-Drain Outputs Used for Key Scan............................................................................................ 51
4.3 Cold Boot ........................................................................................................................................... 52
4.4 The Slave Port .................................................................................................................................... 53

4.4.1 Slave Rabbit As A Protocol UART ........................................................................................... 54

Chapter 5. Pin Assignments and Functions

5.1 LQFP Package.................................................................................................................................... 56

5.1.1 Pinout ......................................................................................................................................... 56
5.1.2 Mechanical Dimensions and Land Pattern ................................................................................ 57

5.2 Ball Grid Array Package ................................................................................................................... 59

5.2.1 Pinout ......................................................................................................................................... 59
5.2.2 Mechanical Dimensions and Land Pattern ................................................................................ 60

5.3 Rabbit Pin Descriptions...................................................................................................................... 62
5.4 Bus Timing ......................................................................................................................................... 64
5.5 Description of Pins with Alternate Functions .................................................................................... 65
5.6 DC Characteristics.............................................................................................................................. 68
5.7 I/O Buffer Sourcing and Sinking Limit.............................................................................................. 69

Chapter 6. Rabbit Internal I/O Registers

6.1 Default Values for all the Peripheral Control Registers..................................................................... 73

Chapter 7. Miscellaneous Functions

7.1 Processor Identification...................................................................................................................... 79
7.2 Rabbit Oscillators and Clocks ............................................................................................................ 80
7.3 Clock Doubler .................................................................................................................................... 83
7.4 Clock Spectrum Spreader................................................................................................................... 86
7.5 Chip Select Options for Low Power .................................................................................................. 87
7.6 Output Pins CLK, STATUS, /WDTOUT, /BUFEN .......................................................................... 90
7.7 Time/Date Clock (Real-Time Clock) ................................................................................................. 91
7.8 Watchdog Timer................................................................................................................................. 93
7.9 System Reset ...................................................................................................................................... 95
7.10 Rabbit Interrupt Structure................................................................................................................. 97

7.10.1 External Interrupts ................................................................................................................... 99
7.10.2 Interrupt Vectors: INT0 - EIR,0x00/INT1 - EIR,0x08 .......................................................... 100

7.11  Bootstrap Operation ....................................................................................................................... 101
7.12 Pulse Width Modulator .................................................................................................................. 103
7.13  Input Capture.................................................................................................................................. 105
7.14  Quadrature Decoder ....................................................................................................................... 110

Chapter 8. Memory Interface and Mapping

115

8.1 Interface for Static Memory Chips................................................................................................... 115
8.2 Memory Mapping Overview ............................................................................................................ 117
8.3 Memory-Mapping Unit .................................................................................................................... 117

Rabbit 3000 Microprocessor User’s Manual

Chapter 14. Rabbit 3000 Clocks

211

14.1 Low-Power Design......................................................................................................................... 212

Chapter 15. EMI Control

213

15.1 Power Supply Connections and Board Layout .............................................................................. 214
15.2 Using the Clock Spectrum Spreader .............................................................................................. 214

Chapter 16. AC Timing Specifications

217

16.1  Memory Access Time .................................................................................................................... 217
16.2  I/O Access Time............................................................................................................................. 225
16.3  Further Discussion of Bus and Clock Timing ................................................................................ 227
16.4  Maximum Clock Speeds ................................................................................................................ 229
16.5  Power and Current Consumption ................................................................................................... 231
16.6 Current Consumption Mechanisms ................................................................................................ 234
16.7  Sleepy Mode Current Consumption ............................................................................................... 235
16.8  Memory Current Consumption ...................................................................................................... 236
16.9  Battery-Backed Clock Current Consumption ................................................................................ 237
16.10 Reduced-Power External Main Oscillator.................................................................................... 238

Chapter 17. Rabbit BIOS and Virtual Driver

239

17.1 The BIOS........................................................................................................................................ 239

17.1.1 BIOS Services ....................................................................................................................... 239
17.1.2 BIOS Assumptions ................................................................................................................ 240

17.2 Virtual Driver ................................................................................................................................. 240

17.2.1 Periodic Interrupt ................................................................................................................... 240
17.2.2 Watchdog Timer Support ...................................................................................................... 240

Chapter 18. Other Rabbit Software

243

18.1 Power Management Support .......................................................................................................... 243
18.2 Reading and Writing I/O Registers ................................................................................................ 244

18.2.1 Using Assembly Language .................................................................................................... 244
18.2.2 Using Library Functions ........................................................................................................ 244

18.3 Shadow Registers ........................................................................................................................... 245

18.3.1 Updating Shadow Registers .................................................................................................. 245
18.3.2 Interrupt While Updating Registers ....................................................................................... 245
18.3.3 Write-only Registers Without Shadow Registers .................................................................. 246

18.4 Timer and Clock Usage.................................................................................................................. 246

Chapter 19. Rabbit Instructions

249

19.1  Load Immediate Data ..................................................................................................................... 252
19.2  Load & Store to Immediate Address.............................................................................................. 252
19.3 8-bit Indexed Load and Store ......................................................................................................... 252
19.4  16-bit Indexed Loads and Stores .................................................................................................... 252
19.5  16-bit Load and Store 20-bit Address ............................................................................................ 253
19.6  Register to Register Moves ............................................................................................................ 253
19.7 Exchange Instructions .................................................................................................................... 254
19.8  Stack Manipulation Instructions..................................................................................................... 254
19.9  16-bit Arithmetic and Logical Ops................................................................................................. 254
19.10 8-bit Arithmetic and Logical Ops................................................................................................. 255
19.11 8-bit Bit Set, Reset and Test......................................................................................................... 256
19.12 8-bit Increment and Decrement.................................................................................................... 256
19.13 8-bit Fast A Register Operations .................................................................................................. 257
19.14 8-bit Shifts and Rotates ................................................................................................................ 257
19.15 Instruction Prefixes ...................................................................................................................... 258

Chapter 1 Introduction

1. I

NTRODUCTION

Rabbit Semiconductor was formed expressly to design a a better microprocessor for use in
small and medium-scale controllers. The first microprocessor was the

Rabbit 2000

. The

second microprocessor, now available, is the

Rabbit 3000

. Rabbit microprocessor design-

ers have had years of experience using Z80, Z180, and HD64180 microprocessors in small
controllers. The Rabbit shares a similar architecture and a high degree of compatibility
with these microprocessors, but it is a vast improvement.

The Rabbit 3000 has been designed in close cooperation with Z-World, Inc., a long-time
manufacturer of low-cost single-board computers. Z-World and Rabbit Semiconductor
products are supported by an innovative C-language development system (Dynamic C).

The Rabbit 3000 is easy to use. Hardware and software interfaces are as uncluttered and
are as foolproof as possible. The Rabbit has outstanding computation speed for a micro-
processor with an 8-bit bus. This is because the Z80-derived instruction set is very com-
pact, and the timing of the memory interface allows higher clock speeds for a given
memory speed.

Microprocessor hardware and software development is easy for Rabbit users. In-circuit
emulators are not needed and will not be missed by the Rabbit developer. Software devel-
opment is accomplished by connecting a simple interface cable from a PC serial port to the
Rabbit-based target system or by performing software development and debugging over a
network or the Internet using interfaces and tools provided by Rabbit Semiconductor.

Rabbit 3000 Microprocessor User’s Manual

1.1 Features and Specifications Rabbit 3000

•

128-pin LQFP package. Operating voltage 1.8 V to 3.6 V. Clock speed to 54+ MHz. All
specifications are given for both industrial and commercial temperature and voltage
ranges. Rabbit microprocessors are low-cost.

•

Industrial specifications are for 3.3 V ±10% and a temperature range from -40°C to
+85°C. Modified commercial specifications are for a voltage variation of 5% and a
temperature range from -40°C to 70°C.

•

1-megabyte code-data space allows C programs with 50,000+ lines of code. The
extended Z80-style instruction set is C-friendly, with short and fast opcodes for the
most important C operations.

•

Four levels of interrupt priority make a fast interrupt response practical for critical
applications. The maximum time to the first instruction of an interrupt routine is about
0.5 µs at a clock speed of 50 MHz.

•

Access to I/O devices is accomplished by using memory access instructions with an I/O
prefix. Access to I/O devices is thus faster and easier compared to processors with a
distinct and narrow I/O instruction set. As an option the auxiliary I/O bus can be
enabled to use separate pins for address and data, allowing the I/O bus to have a greater
physical extent with less EMI and less conflict with the requirements of the fast mem-
ory bus.(Further described below.)

•

Hardware design is simple. Up to six static memory chips (such as RAM and flash
memory) connect directly to the microprocessor with no glue logic. A memory-access
time of 55 ns suffices to support up to a 30 MHz clock with no wait states; with a 30 ns
memory-access time, a clock speed of up to 50 MHz is possible with no wait states.
Most I/O devices may be connected without glue logic.

The memory read cycle is two clocks long. The write cycle is 3 clocks long. A clean
memory and I/O cycle completely avoid the possibility of bus fights. Peripheral I/O
devices can usually be interfaced in a glueless fashion using the common /IORD and
/IOWR strobes in addition to the user-configurable IO strobes on Parallel Port E. The
Parallel Port E pins can be configured as I/O read, write, read/write, or chip select when
they are used as I/O strobes.

•

EMI reduction features reduce EMI levels by as much as 25 dB compared to other sim-
ilar microprocessors. Separate power pins for the on-chip I/O buffers prevent high-fre-
quency noise generated in the processor core from propagating to the signal output
pins. A built-in clock spectrum spreader reduces electromagnetic interference and facil-
itates passing EMI tests to prove compliance with government regulatory requirements.
As a consequence, the designer of a Rabbit-3000-based system can be assured of pass-
ing FCC or CE EMI tests as long as minimal design precautions are followed.

•

The Rabbit may be cold-booted via a serial port or the parallel access slave port. This
means that flash program memory may be soldered in unprogrammed, and can be
reprogrammed at any time without any assumption of an existing program or BIOS.

Chapter 1 Introduction

A Rabbit that is slaved to a master processor can operate entirely with volatile RAM,
depending on the master for a cold program boot.

•

There are 56 parallel I/O lines (shared with serial ports). Some I/O lines are timer syn-
chronized, which permits precisely timed edges and pulses to be generated under com-
bined hardware and software control. Pulse-width modulation outputs are implemented
in addition to the timer-synchronization feature (see below).

•

Four pulse width modulated (PWM) outputs are implemented by special hardware. The
repetition frequency and the duty cycle can be varied over a wide range. The resolution
of the duty cycle is 1 part in 1024.

•

There are six serial ports. All six serial ports can operate asynchronously in a variety of
commonly used operating modes. Four of the six ports (designated A, B, C, D) support
clocked serial communications suitable for interfacing with “SPI” devices and various
similar devices such as A/D converters and memories that use a clocked serial protocol.
Two of the ports, E and F, support HDLC/SDLC synchronous communication. These
ports have a 4-byte FIFO and can operate at a high data rate. Ports E and F also have a
digital phase-locked loop for clock recovery, and support popular data-encoding meth-
ods. High data rates are supported by all six serial ports. The asynchronous ports also
support the 9th bit network scheme as well as infrared transmission using the IRDA pro-
tocol. The IRDA protocol is also supported in SDLC format by the two ports that sup-
port SDLC.

•

A slave port allows the Rabbit to be used as an intelligent peripheral device slaved to a
master processor. The 8-bit slave port has six 8-bit registers, 3 for each direction of
communication. Independent strobes and interrupts are used to control the slave port in
both directions. Only a Rabbit and a RAM chip are needed to construct a complete
slave system, if the clock and reset control are shared with the master processor

•

There is an option to enable an auxiliary I/O bus that is separate from the memory bus.
The auxiliary I/O bus toggles only on I/O instructions. It reduces EMI and speeds the
operation of the memory bus, which only has to connect to memory chips when the
auxiliary I/O bus is used to connect I/O devices. This important feature makes memory
design easy and allows a more relaxed approach to interfacing I/O devices.

•

The built-in battery-backable time/date clock uses an external 32.768 kHz crystal oscil-
lator. The suggested model circuit for the external oscillator utilizes a single “tiny
logic” active component. The time/date clock can be used to provide periodic interrupts
every 488 µs. Typical battery current consumption is about 3 µA.

•

Numerous timers and counters can be used to generate interrupts, baud rate clocks, and
timing for pulse generation.

•

Two input-capture channels can be used to measure the width of pulses or to record the
times at which a series of events take place. Each capture channel has a 16-bit counter
and can take input from one or two pins selected from any of 16 pins.

•

Two quadrature decoder units accept input from incremental optical shaft encoders.
These units can be used to track the motion of a rotating shaft or similar device.

Rabbit 3000 Microprocessor User’s Manual

•

A built-in clock doubler allows ½-frequency crystals to be used.

•

The built-in main clock oscillator uses an external crystal or a ceramic resonator. Typical
crystal or resonator frequencies are in the range of 1.8 MHz to 30 MHz. Since precision
timing is available from the separate 32.768 kHz oscillator, a low-cost ceramic resonator
with ½ percent error is generally satisfactory. The clock can be doubled or divided down
to modify speed and power dynamically. The I/O clock, which clocks the serial ports, is
divided separately so as not to affect baud rates and timers when the processor clock is
divided or multiplied. For ultra low power operation, the processor clock can be driven
from the separate 32.768 kHz oscillator and the main oscillator can be powered down.
This allows the processor to operate at approximately between 20 and 100 µA and still
execute instructions at the rate of up to 10,000 instructions per second. The 32.768 kHz
clock can also be divided by 2, 4, 8 or 16 to reduce power. This “sleepy mode” is a pow-
erful alternative to sleep modes of operation used by other processors.

•

Processor current requirement is approximately 65 mA at 30 MHz and 3.3 V. The cur-
rent is proportional to voltage and clock speed—at 1.8 V and 3.84 MHz the current
would be about 5 mA, and at 1 MHz the current is reduced to about 1 mA.

•

To allow extreme low power operation there are options to reduce the duty cycle of
memories when running at low clock speeds by only enabling the chip select for a brief
period, long enough to complete a read. This greatly reduces the power used by flash
memory when operating at low clock speeds.

•

The excellent floating-point performance is due to a tightly coded library and powerful
processing capability. For example, a 50 MHz clock takes 7 µs for a floating add, 7 µs
for a multiply, and 20 µs for a square root. In comparison, a 386EX processor running
with an 8-bit bus at 25 MHz and using Borland C is about 20 times slower.

•

There is a built-in watchdog timer.

•

The standard 10-pin programming port eliminates the need for in-circuit emulators. A
very simple 10-pin connector can be used to download and debug software using
Rabbit Semiconductor’s Dynamic C and a simple connection to a PC serial port. The
incremental cost of the programming port is extremely small.

Figure 1-1 shows a block diagram of the Rabbit.

Chapter 1 Introduction

Figure 1-1. Rabbit 3000 Block Diagram

CPU

External Interface

Data

Buffer

Memory

Management/

Control

Address

Buffer

Memory Chip

Interface

Parallel Ports

Port A

Port B

Port C

Port D

Port E

Port F

Port G

Global Power

Save & Clock

Distribution

Fast

Oscillator

Timer A

Timer B

Real-Time

Clock

32.768 kHz

Clock Input

Watchdog

Timer

Periodic

Interrupt

External I/O

Chip Interface

External

Interrupts

/RESET

/IOWR

/IORD

/BUFEN

SMODE0

SMODE1

TUS

/WDT

OUT

CLK

BUS

(8 bit

D[7:0]

A[19:0]

XTALA1
XTALA2

CLK32K

I[7:0]

INT0A, INT1A

INT0B, INT1B

/CS2, /CS1, /CS0

/OE1, /OE0

/WE1, /WE0

PA [7:0]

PB[7:0]

PC[7:0]

PD[7:0]

PE[7:0]

TXA, RXA, CLKA,

ATXA, ARXA

TXB, RXB, CLKB,

ATXB, ARXB

TXC, RXC, CLKC

TXD, RXD, CLKD

ADDRESS BUS

(8 bit

RESOUT

PF[7:0]

PG[7:0]

Asynch

Serial

Synch

Serial

Asynch

Bootstrap

Synch

Bootstrap

Serial Port A

Asynch Serial IrDA

Serial Ports

B,C,D

Asynch Serial IrDA

Asynch

Serial

Synch

Serial

Serial Ports

E, F

Asynch Serial IrDA

Asynch

Serial

HDLC

SDLC

HDLC/SDLC IrDA

TXE, RXE

TCLKE, RCLKE

Slave Port

Slave Interface

SD[7:0]

SA[1:0],

/SCS, /SRD, /SWR,

/SLAVEATTN

Bootstrap Interface

TXF, RXF

TCLKF, RCLKF

ID[7:0]
IA[5:0]

Spectrum

Spreader

Clock

Doubler

Pulse Width

Modulation

PWM[3:0]

Quadrature

Decoder

QD1A, QD1B

QD2A, QD2B

AQD1A, AQD1B

AQD2A, AQD2B

Input

Capture

PC[7,5,3,1]

PD[7,5,3,1]

PF[7,5,3,1]

PG[7,5,3,1]

IrDA Bootstrap

Rabbit 3000 Microprocessor User’s Manual

1.2 Summary of Rabbit 3000 Advantages

•

The glueless architecture makes it is easy to design the hardware system.

•

There are a lot of serial ports and they can communicate very fast.

•

Precision pulse and edge generation is a standard feature.

•

EMI is at extremely low levels.

•

Interrupts can have multiple priorities.

•

Processor speed and power consumption are under program control.

•

The ultra low power mode can perform computations and execute logical tests since the
processor continues to execute, albeit at 32 kHz or even as slow as 2 kHz.

•

The Rabbit may be used to create an intelligent peripheral or a slave processor. For
example, protocol stacks can be off loaded to a Rabbit slave. The master can be any
processor.

•

The Rabbit can be cold-booted so unprogrammed flash memory can be soldered in
place.

•

You can write serious software, be it 1,000 or 50,000 lines of C code. The tools are
there and they are low in cost.

•

If you know the Z80 or Z180, you know most of the Rabbit.

•

A simple 10-pin programming interface replaces in-circuit emulators and PROM pro-
grammers.

•

The battery-backable time/date clock is included.

•

The standard Rabbit chip is made to industrial temperature and voltage specifications.

•

The Rabbit 3000 is backed by extensive software development tools and libraries, espe-
cially in the area of networking and embedded Internet.

Chapter 1 Introduction

1.3 Differences Rabbit 3000 vs. Rabbit 2000

For the benefit of readers who are familiar with the Rabbit 2000 microprocessor the Rab-
bit 3000 is contrasted with the Rabbit 2000 in the table below.

Feature

Rabbit 3000

Rabbit 2000

Maximum clock speed

54 MHz

30 MHz

Maximum crystal frequency main oscillator (may be
doubled internally)

30 MHz

32 MHz

32.768 kHz crystal oscillator

External

Internal

Maximum operating voltage

3.6 V

5.5 V

Maximum I/O input voltage

5.5 V

Current consumption

2 mA/MHz @ 3.3 V

4 mA/MHz @5 V

Number of package pins

128

100

Size of package

16 × 16 × 1.5 mm LQFP

10 × 10 × 1.2 mm

TFBGA

24 × 18 × 3 mm PQFP

Spacing between package pins

0.4 mm (16 mils) LQFP

0.8 mm TFBGA

0.65 mm (26 mils) PQFP

Separate power and ground for I/O buffers (EMI
reduction)

Yes

Clock Spectrum Spreader (EMI reduction)

Yes

Rabbit 2000B and

Rabbit 2000C versions.

Clock Modes

1x, 2x, /2, /3, /4, /6, /8

1x, 2x, /4, /8

Power Down Modes

Sleepy (32 kHz)

Ultra-Sleepy

(16, 8, 2 kHz)

Sleepy (32 kHz)

Low Power Memory Control (Chip Select)

Short CS (CLK /4 /6 /8)

Self Timed

(32,16,8,2 kHz)

None

Extended memory timing for high freq. operation

Yes

Number of 8-bit I/O ports

Auxiliary I/O Data/Address bus

Yes

None

Number of serial ports

Serial ports capable of SPI/clocked serial

4 (A, B, C, D)

2 (A, B)

Serial ports capable of SDLC/HDLC

2 (E, F)

None

Asynch serial ports with support for IrDA
communications

None

Chapter 2 Rabbit 3000 Design Features

2. R

ABBIT

3000 D

ESIGN

EATURES

The Rabbit 3000 is an evolutionary design. The processor and instruction set are nearly
identical to the immediate predecessor processor, the Rabbit 2000. Both the Rabbit 3000
and the Rabbit 2000 follow in broad outline the instruction set and the register layout of
the Z80 and Z180. Compared to the Z180 the instruction set has been augmented by a sub-
stantial number of new instructions. Some obsolete or redundant Z180 instructions have
been dropped to make available efficient 1-byte opcodes for important new instructions.
(see Chapter 20, “Differences Rabbit vs. Z80/Z180 Instructions,”.) The advantage of this
evolutionary approach is that users familiar with the Z80 or Z180 can immediately under-
stand Rabbit assembly language. Existing Z80 or Z180 source code can be assembled or
compiled for the Rabbit with minimal changes.

Changing technology has made some features of the Z80/Z180 family obsolete, and these
features have been dropped in the Rabbit. For example, the Rabbit has no special support
for dynamic RAM but it has extensive support for static memory. This is because the price
of static memory has decreased to the point that it has become the preferred choice for
medium-scale embedded systems. The Rabbit has no support for DMA (direct memory
access) because most of the uses for which DMA is traditionally used do not apply to
embedded systems, or they can be accomplished better in other ways, such as fast inter-
rupt routines, external state machines or slave processors.

Our experience in writing C compilers has revealed the shortcomings of the Z80 instruc-
tion set for executing the C language. The main problem is the lack of instructions for han-
dling 16-bit words and for accessing data at a computed address, especially when the stack
contains that data. New instructions correct these problems.

Another problem with many 8-bit processors is their slow execution and a lack of number-
crunching ability. Good floating-point arithmetic is an important productivity feature in
smaller systems. It is easy to solve many programming problems if an adequate floating-
point capability is available. The Rabbit’s improved instruction set provides fast floating-
point and fast integer math capabilities.

The Rabbit supports four levels of interrupt priorities. This is an important feature that
allows the effective use of fast interrupt routines for real-time tasks.

Rabbit 3000 Microprocessor User’s Manual

2.1 The Rabbit 8-bit Processor vs. Other Processors

The Rabbit 3000 processor has been designed with the objective of creating practical sys-
tems to solve real world problems in an economical fashion. A cursory comparison of the
Rabbit 3000 compared to other processors with similar capabilities may miss certain Rab-
bit strong points.

•

The Rabbit is a processor that can be used to build a system in which EMI is nearly
absent, even at clock frequencies in excess of 40 MHz. This is due to the split power
supply, the clock doubler, the clock spectrum spreader and the PC board layout advice
(or processor core modules) that we provide. Low EMI is a huge timesaver for the
designer pressed to meet schedules and pass government EMI tests of the final product.

•

Execution speed with the Rabbit is usually a pleasant surprise compared to other pro-
cessors. This is due to the well-chosen and compact instruction set partnered with and
excellent compiler and library. We have many benchmarks, comparing the Rabbit to
186, 386, 8051, Z180 and ez80 families of processors that prove the point.

•

The Rabbit memory bus is an exceptionally efficient and very clean design. No external
logic is required to support static memory chips. Battery-backed external memory is
supported by built-in functionality. During reduced-power slow-clock operation the
memory duty cycle can be correspondingly reduced using built-in hardware, resulting
in low power consumption by the memories.

The Rabbit external bus uses 2 clocks for read cycles and 3 clocks for write cycles. This
has many advantages compared to a single-clock design, and on closer examination the
advantages of the single-clock system turn out to be mostly chimerical. The advantages
include: easy design to avoid bus fights, clean write cycles with solid data and address
hold times, flexibility to have memory output enable access times greater than ½ of the
bus cycle, and the ability to use an asymmetric clock generated by a clock doubler. The
supposed advantage that single-clock systems have of double-speed bus operation is
not possible with real-world memories unless the memory is backed with fast-cache
RAM.

•

The Rabbit 3000 operates at 3.6 V or less, but it has 5 V tolerant inputs and has a sec-
ond complete bus for I/O operations that is separate from the memory bus. This second
auxiliary bus can be enabled by the application as a designer option. These features
make it easy to design systems that mix 3 V and 5 V components, and avoid the loading
problems and the EMI problems that result if the memory bus is extended to connect
with many I/O devices.

•

The Rabbit may be remotely programmed, including complete cold-boot, via a serial
link, Ethernet, or even via a network or the Internet using built in capabilities and/or the
RabbitLink ethernet network accessory device. These capabilities proven and inexpen-
sive to implement.

•

The Rabbit 3000 on-chip peripheral complement is huge compared to competitive pro-
cessors.

Chapter 2 Rabbit 3000 Design Features

The Rabbit is an 8-bit processor with an 8-bit external data bus and an 8-bit internal data
bus. Because the Rabbit makes the most of its external 8-bit bus and because it has a com-
pact instruction set, its performance is as good as many 16-bit processors.

We hesitate to compare the Rabbit to 32-bit processors, but there are undoubtedly occa-
sions where the user can use a Rabbit instead of a 32-bit processor and save a vast amount
of money. Many Rabbit instructions are 1 byte long. In contrast, the minimum instruction
length on most 32-bit RISC processors is 32 bits.

2.2 Overview of On-Chip Peripherals and Features

The on-chip peripherals were chosen based on our experience as to what types of periph-
eral devices are most useful in small embedded systems. The major on-chip peripherals
are the serial ports, system clock, time/date oscillator, parallel I/O, slave port, motion
encoders, pulse width modulators, pulse measurement, and timers. These and other fea-
tures are described below.

2.2.1 5 V Tolerant Inputs

The Rabbit 3000 operates on a voltage in the range of 1.8 V to 3.6 V, but most Rabbit 3000
input pins are 5 V tolerant. The exceptions are the power supply pins, and the oscillator
buffer pins. When a 5 V signal is applied to 5 V tolerant pins, they present a high impedance
even if the Rabbit power is off. The 5 V tolerant feature allows 5 V devices that have a
suitable switching threshold to be directly connected to the Rabbit. This includes HCT
family parts operated at 5 V that have an input threshold between 0.8 and 2 V.

NOTE:

CMOS devices operated at 5 V that have a threshold at 2.5 V are not suitable for

direct connection because the Rabbit outputs do not rise above VDD, which cannot
exceed 3.6 V, and is often specified as 3.3 V. Although a CMOS input with a 2.5 V
threshold may switch at 3.3 V, it will consume excessive current and switch slowly.

In order to translate between 5 V and 3.3 V, HCT family parts powered from 5 V can be
used, and are often the best solution. There is also the “LVT” family of parts that operate
from 2.0 V to 3.3 V, but that have 5 V tolerant inputs and are available from many suppli-
ers. True level-translating parts are available with separate 3.3 V and 5 V supply pins, but
these parts are not usually needed, and have design traps involving power sequencing.
Many charge pump chips that perform DC to DC voltage conversion at low cost have been
introduced in recent years. These are convenient for systems with dual voltage requirements.

2.2.2 Serial Ports

There are six serial ports designated ports A, B, C, D, E, and F. All six serial ports can
operate in an asynchronous mode up to a baud rate equal to the system clock divided by 8.
The asynchronous ports use 7-bit or 8-bit data formats, with or without parity. A 9th bit
address scheme, where an additional bit is set or cleared to mark the first byte of a mes-
sage, is also supported.

The serial port software driver can tell when the last byte of a message has finished trans-
mitting from the output shift register - correcting an important defect of the Z180. This is

Rabbit 3000 Microprocessor User’s Manual

important for RS-485 communication because a half duplex line driver cannot have the
direction of transmission reversed until the last data bit has been sent. In many UARTs,
including those on the Z180, it is difficult to generate an interrupt after the last bit is sent.
A so called address bit can be transmitted as either high or low after the last data bit. The
address bit, if used, is followed by a high stop bit. This facility can be used to transmit 2
stop bits or a parity bit if desired. The ability to directly transmit a high voltage level
address bit was not included in the original revision of the Rabbit 2000 processor.

Serial Ports A, B, C and D can be operated in the clocked serial mode. In this mode, a
clock line synchronously clocks the data in or out. Either the Rabbit serial port or the
remote device can supply the clock. When the Rabbit provides the clock, the baud rate can
be up to one half of the system clock frequency. When the clock is provided by another
device, the maximum data rate is the system clock divided by 6 because of the need to
synchronize the externally supplied clock with the internal clock. The clocked serial mode
may be used to support “SPI” bus devices.

Serial Port A has special features. It can be used to cold-boot the system after reset. Serial
Port A is the normal port that is used for software development under Dynamic C.

All the serial ports have a special timing mode that supports infrared data communications
standards.

2.2.3 System Clock

The main oscillator uses an external crystal with a frequency typically in the range from
1.8 MHz to 26 MHz. The processor clock is derived from the oscillator output by either
doubling the frequency, using the frequency directly, or dividing the frequency by 2, 4, 6,
or 8. The processor clock can also be driven by the 32.768 kHz real-time clock oscillator
for very low power operation, in which case the main oscillator can be shut down under
software control.

2.2.4 32.768 kHz Oscillator Input

The 32.768 kHz oscillator input is designed to accept a 32.768 kHz clock. A suggested low-
power clock circuit using “tiny logic” parts is documented and low in cost. The 32.768 kHz
clock is used to drive a battery-backable (there is a separate power pin) internal 48-bit
counter that serves as a real-time clock (RTC). The counter can be set and read by software
and is intended for keeping the date and time. There are enough bits to keep the date for
more than 100 years. The 32.768 kHz oscillator input is also used to drive the watchdog
timer and to generate the baud clock for Serial Port A during the cold-boot sequence.

Chapter 2 Rabbit 3000 Design Features

2.2.5 Parallel I/O

There are 56 parallel input/output lines divided among seven 8-bit ports designated A
through G. Most of the port lines have alternate functions, such as serial data or chip select
strobes. Parallel Ports D, E, F, and G have the capability of timer-synchronized outputs.
The output registers are cascaded as shown in Figure 2-1.

Figure 2-1. Cascaded Output Registers for Parallel Ports D and E

Stores to the port are loaded in the first-level register. That register in turn is transferred to
the output register on a selected timer clock. The clock can be selected to be the output of
Timer A1, B1, B2 or the peripheral clock (divided by 2?). The timer signal can also cause
an interrupt that can be used to set up the next bit to be output on the next timer pulse. This
feature can be used to generate precisely controlled pulses whose edges are positioned
with high accuracy in time. Applications include communications signaling, pulse width
modulation and driving stepper motors. (A separate pulse width modulation facility is also
included in the Rabbit 3000.)

Figure 2-2. Digital Filtering Input Pins

Input pins to the parallel ports are filtered by cascaded D flip flops as shown in Figure 2-2.
This prevents pulses shorter then the peripheral clock from being recognized, synchro-
nizes external pulses to the internal clock, and avoids problems with meta stability (tem-
porarily indeterminate logical conditions due to marginal set up time with respect to the
clock).

Timer Clock

Load Clock

Load Data

Output Port

D Q

Peripheral

External Input

Filtered Input

Clock

Rabbit 3000 Microprocessor User’s Manual

2.2.6 Slave Port

The slave port is designed to allow the Rabbit to be a slave to another processor, which
could be another Rabbit. The port is shared with Parallel Port A and is a bidirectional data
port. The master can read any of three registers selected via two select lines that form the
register address and a read strobe that causes the register contents to be output by the port.
These same registers can be written as I/O registers by the Rabbit slave. Three additional
registers transmit data in the opposite direction. They are written by the master by means
of the two select lines and a write strobe.

Figure 2-3 shows the data paths in the slave port.

Figure 2-3. Slave-Port Data Paths

The slave Rabbit can read the same registers as I/O registers. When incoming data bits are
written into one of the registers, status bits indicate which registers have been written, and
an optional interrupt can be programmed to take place when the write occurs. When the
slave writes to one of the registers carrying data bits outward, an attention line is enabled
so that the master can detect the data change and be interrupted if desired. One line tells
the master that the slave has read all the incoming data. Another line tells the master that
new outgoing data bits are available and have not yet been read by the master. The slave
port can be used to signal the master to perform tasks using a variety of communication
protocols over the slave port.

Master

Processor

Input

Registers

Output

Registers

Control

Slave Interface

Registers

CPU

RABBIT 3000

Chapter 2 Rabbit 3000 Design Features

2.2.7 Auxiliary I/O Bus

The Rabbit 3000 instruction set supports memory access and I/O access. Memory access
takes place in a 1 megabyte memory space. I/O access takes place in a 64K I/O space. In a
traditional microprocessor design the same address and data lines are used for both mem-
ory and I/O spaces. Sharing address and data lines in this manner often forces compromises
or makes design more complicated. Generally the memory bus has more critical timing and
less tolerant of additional capacitive loading imposed by sharing it with an I/O bus.

With the Rabbit 3000, the designer has the option of enabling completely separate buses
for I/O and memory. The auxiliary I/O bus uses many of the same pins used by the slave
port, so its operation is mutually exclusive from operation of the slave port. Parallel Port A
is used to provide 8 bidirectional data lines. Parallel Port B bits 2:7 provide 6 address
lines, the least significant 6 lines of the 16 lines that define the full I/O space. The auxil-
iary bus is only active on I/O bus cycles. The address lines remain in the same state
assumed at the end of the previous I/O cycle until another I/O cycle takes place. I/O chip
selects as well as read and write strobes are available at various other pins so that the 64
byte space defined by the 6 address lines may be easily expanded. I/O cycles also execute
in parallel on the main (memory) bus when they take place on the auxiliary bus, so addi-
tional address lines can be buffered and provided if needed.

By connecting I/O devices to the auxiliary bus, the fast memory bus is relieved of the
capacitive load that would otherwise slow the memory. For core modules based on the
Rabbit 3000, fewer pins are required to exit the core module since the slave port and the
I/O bus can share the same pins and the memory bus no longer needs to exit the module to
provide I/O capability. Because the I/O bus has less activity and is slower than the memory
bus, it can be run further physically without EMI and ground bounce problems. 5 V signals
can appear on the I/O bus since the Rabbit 3000 inputs are 5 V tolerant. 5 V signals could
easily cause problems on the main bus if non 5 V tolerant 3.3 V memories are connected.

2.2.8 Timers

The Rabbit has several timer systems. The periodic interrupt is driven by the 32.768 kHz
oscillator divided by 16, giving an interrupt every 488 µs if enabled. This is intended to be
used as a general-purpose clock interrupt. Timer A consists of ten 8-bit countdown and
reload registers that can be cascaded up to two levels deep. Each countdown register can be
set to divide by any number between 1 and 256. The output of six of the timers is used to
provide baud clocks for the serial ports. Any of these registers can also cause interrupts and
clock the timer-synchronized parallel output ports. Timer B consists of a 10-bit counter that
can be read but not written. There are two 10-bit match registers and comparators. If the
match register matches the counter, a pulse is output. Thus the timer can be programmed to
output a pulse at a predetermined count in the future. This pulse can be used to clock the
timer-synchronized parallel-port output registers as well as cause an interrupt. Timer B is
convenient for creating an event at a precise time in the future under program control.

Figure 2-4 illustrates the Rabbit timers.

Rabbit 3000 Microprocessor User’s Manual

Figure 2-4. Rabbit Timers A and B

2.2.9 Input Capture Channels

The input capture channels are used to determine the time at which an event takes place.
An event is signaled by a rising or falling edge (or optionally by either edge) on one of 16
input pins that can be selected as input for either of the two channels. A 16 bit counter is
used to record the time at which the event takes place. The counter is driven by the output
of Timer A8 and can be set to count at a rate ranging from full clock speed to 1/256 the
clock speed.

Two events are recognized: a

start condition

and a

stop condition

. The start condition may

be used to start counting and the stop condition to stop counting. However the counter
may also run continuously or run until a stop condition is encountered. The start and stop
conditions may also be used to latch the current time at the instant the condition occurs
rather than actually start or stop the counter. The same pin may be used to detect the start

Timer A System

match reg

compare

Timer B System

match preload

10 bits

Timer B1

Timer B2

perclk

perclk/2

10-bit counter

Serial E

Serial F

Serial A

Serial B

Serial C

Serial D

Input
Capture

PWM

Quadrature
Decode

A10

Timer A1

perclk/2

perclk/8

Control Timer
Synchronized
outputs

Chapter 2 Rabbit 3000 Design Features

and stop condition, for example a rising edge could be the start condition and a falling
edge the stop condition. However, optionally, the start and stop condition can be input
from separate pins.

The input capture channels can be used to measure the width of fast pulses. This is done
by starting the counter on the first edge of the pulse and capturing the counter value on the
second edge of the pulse. In this case the maximum error in the measurement is approxi-
mately 2 periods of the clock used to count the counter. If there is sufficient time between
events for an interrupt to take place the unit can be set up to capture the counter value on
either start or stop conditions or both and cause an interrupt each time the count is cap-
tured. In this case the start and stop conditions lose the connection with starting or stop-
ping the counter and simply become capture conditions that may be specified for 2
independent edge detectors. The counter can also be cleared and started under software
control and then have its value captured in response to an input.

If desired the capture counter can synchronized with Timer B outputs used to synchro-
nously load parallel port output registers. This makes it possible to generate an output sig-
nal precisely synchronized with an input signal. Usually it will be desired to synchronize
one of the input capture counters with the Timer B counter. The count offset can be mea-
sured by outputting a pulse at a precise time using Timer B to set the output time and cap-
turing the same pulse. Once the phase relationship is known between the counters it is then
possible to output pulses a precise time delay after an input pulse is captured, provided
that the time delay is great enough for the interrupt routine to processes the capture event
and set up the output pulse synchronized by Timer B. The minimum time delay needed is
probably less than 10 microseconds if the software is done carefully the clock speed is rea-
sonably high.

2.2.10 Quadrature Decoder Inputs

A quadrature encoder is a common electromechanical device used to track the rotation of
a shaft, or in some cases to track the motion of a linear follower. These devices are usually
implemented by the use of a disk or a strip with alternate opaque and transparent bands
that excite dual optical detectors. The output signals are square waves 90 degrees out of
phase also called being in quadrature with each other. By having quadrature signals, the
direction of rotation can be detected by noting which signal leads the other signal.

The Rabbit 3000 has two quadrature decoder units. Each unit has two inputs, the normal
input and the 90 degree or quadrature input. An 8-bit up/down counter counts encoder steps
in the forward and backward directions. The count can be extended beyond eight bits by an
interrupt that takes place each time the count overflows or underflows. The external signals
are synchronized with an internal clock provided by the output of Timer A10.

2.2.11 Pulse Width Modulation Outputs

The pulse width modulated output generates a train of pulses periodic on a 1024 pulse
frame with a duty cycle that varies from 1/1024 to 1024/1024. There are 4 independent
PWM units. The units are driven by the output of Timer A9 which may be used to vary the

Rabbit 3000 Microprocessor User’s Manual

length of the pulses. When the duty cycle is greater then 1/1024 the pulses are spread into
groups distributed 256 counts apart in the 1024 frame. The pulse width modulation outputs
can be passed through a filter and used as a 10-bit D/A converter. The outputs can also be
used to directly drive devices that have intrinsic filtering such as motors or solenoids.

2.2.12 Spread Spectrum Clock

The main system clock, which is generated by the crystal oscillator or input from an exter-
nal oscillator, can be modified by a clock spectrum spreader internal to the Rabbit 3000
chip. When the spectrum spreader is engaged, the clock is alternately speeded up and
slowed down, thus spreading the spectrum of the clock harmonics in the frequency
domain. This reduces EMI and improves the results of official radiated-emissions tests
typically by 15–20 dB at critical frequencies. The spectrum spreader has 3 modes of oper-
ation: off, normal, and strong. Slightly faster memory access time is required when the
spectrum spreader is used: 2–3 ns for the normal setting when the clock doubler is
enabled, and 6–9 ns for the strong setting when the clock doubler is used. The spreader
slightly influences baud rates and other timings because it introduces clock jitter, but the
effect is usually small enough to be negligible.

2.2.13 Separate Core and I/O Power Pins

The silicon die that constitutes the Rabbit 3000 processor is divided into the core logic and
the I/O ring. The I/O ring located on the 4 edges of the die holds the bonding pads and the
large transistors used to create the I/O buffers that drive signals to the external world. The
core section, inside the I/O ring contains the main processor and peripheral logic. The
clock and clock edges in the core are very fast with large transient currents that create a lot
of noise that is communicated to the outside of the package via the power pins. The I/O
buffers have slower switching times and mostly operate at much lower frequencies than
the core logic. The Rabbit has separate power and ground pins for the core and I/O ring.
This allows the designer to feed clean power to the I/O ring filtered to be free of the noise
generated by the core switching. This minimizes high frequency noise that would other-
wise appear on output pins driven by buffers in the I/O ring. The result is lower EMI.

2.3 Design Standards

The same functionality can often be accomplished in more than one way with the Rabbit
3000. By publishing design standards, or standard ways to accomplish common objec-
tives, software and hardware support become easier.

Refer to the

Rabbit 3000 Microprocessor Designer’s Handbook

for additional information.

2.3.1 Programming Port

Rabbit Semiconductor publishes a specification for a standard programming port (see
Appendix A, “The Rabbit Programming Port,”) and provides a converter cable that may
be used to connect a PC serial port to the standard programming interface. The interface is
implemented using a 10-pin connector with two rows of pins on 2 mm centers. The port is
connected to Rabbit Serial Port A, to the startup mode pins on the Rabbit, to the Rabbit

Chapter 3 Details on Rabbit Microprocessor Features

3. D

ETAILS

ABBIT

ICROPROCESSOR

EATURES

3.1 Processor Registers

The Rabbit’s registers are nearly identical to those of the Z180 or the Z80. The figure
below shows the register layout. The XPC and IP registers are new. The EIR register is the
same as the Z80 I register, and is used to point to a table of interrupt vectors for the exter-
nally generated interrupts. The IIR register occupies the same logical position in the
instruction set as the Z80 R register, but its function is to point to an interrupt vector table
for internally generated interrupts.

Figure 3-1. Rabbit Registers

F '

H '

D '

E '

B '

C '

Alternate Registers

XPC

IIR

EIR

–

flag register layout

–

sign,

–

zero,

–

overflow,

–

carry

Bits marked "x" are read/write

8/16-bit

registers

A –

8-bit accumulator

F –

flags register

HL –

16-bit accumulator

IX, IY –

index registers/alt accum’s

SP –

stack pointer

PC –

program counter

XPC –

extension of program counter

IIR –

internal interrupt register

EIR–

external interrupt register

IP –

interrupt priority register

Rabbit 3000 Microprocessor User’s Manual

The Rabbit (and the Z80/Z180) processor has two accumulators—the A register serves as
an 8-bit accumulator for 8-bit operations such as

ADD

AND

. The 16-bit register HL regis-

ter serves as an accumulator for 16-bit operations such as

ADD HL,DE

, which adds the 16-

bit register DE to the 16-bit accumulator HL. For many operations IX or IY can substitute
for

as accumulators.

The register marked F is the flags register or status register. It holds a number of flags that
provide information about the last operation performed. The flag register cannot be
accessed directly except by using the

POP AF

and

PUSH AF

instructions. Normally the

flags are tested by conditional jump instructions. The flags are set to mark the results of
arithmetic and logic operations according to rules that are specified for each instruction.
There are four unused read/write bits in the flag register that are available to the user via
the

PUSH AF

and

POP AF

instructions. These bits should be used with caution since new-

generation Rabbit processors could use these bits for new purposes.

The registers IX, IY and HL can also serve as index registers. They point to memory
addresses from which data bits are fetched or stored. Although the Rabbit can address a
megabyte or more of memory, the index registers can only directly address 64K of mem-
ory (except for certain extended addressing

LDP

instructions). The addressing range is

expanded by means of the memory mapping hardware (see “Memory Mapping” on
page 23) and by special instructions. For most embedded applications, 64K of

data

mem-

ory (as opposed to

code

memory) is sufficient. The Rabbit can efficiently handle a mega-

byte of program space.

The register SP points to the stack that is used for subroutine and interrupt linkage as well
as general-purpose storage.

A feature of the Rabbit (and the Z80/Z180) is the

alternate register set

. Two special

instructions swap the alternate registers with the regular registers. The instruction

EX AF,AF’

exchanges the contents of AF with AF'. The instruction

EXX

exchanges HL, DE, and BC

with HL', DE', and BC'. Communication between the regular and alternate register set in
the original Z80 architecture was difficult because the exchange instructions provided the
only means of communication between the regular and alternate register sets. The Rabbit
has new instructions that greatly improve communication between the regular and alter-
nate register set. This effectively doubles the number of registers that are easily available
for the programmer’s use. It is not intended that the alternate register set be used to pro-
vide a separate set of registers for an interrupt routine, and Dynamic C does not support
this usage because it uses both registers sets freely.

The IP register is the interrupt priority register. It contains four 2-bit fields that hold a his-
tory of the processor’s interrupt priority. The Rabbit supports four levels of processor pri-
ority, something that exists only in a very restricted form in the Z80 or Z180.

Chapter 3 Details on Rabbit Microprocessor Features

3.2 Memory Mapping

Although the Rabbit memory mapping scheme is fairly complex, the user rarely needs to
worry about it because the details are handled by the Dynamic C development system.

Except for a handful of special instructions (see Section 19.5, “16-bit Load and Store 20-
bit Address”), the Rabbit instructions directly address a 64K data memory space. This
means that the address fields in the instructions are 16 bits long and that the registers that
may be used as pointers to memory addresses (index registers (IX, IY), program counter
and stack pointer (

)) are also 16 bits long.

Because Rabbit instructions use 16-bit addresses, the instructions are shorter and can exe-
cute much faster than if, for example, 32-bit addresses were used. The executable code is
very compact.

The Rabbit memory-mapping unit is similar to, but more powerful than, the Z180 mem-
ory-mapping unit. Figure 3-2 illustrates the relationship among the major components
related to addressing memory.

Figure 3-2. Addressing Memory Components

The memory-mapping unit receives 16-bit addresses as input and outputs 20-bit addresses.
The processor (except for certain

LDP

instructions) sees only a 16-bit address space. That

is, it sees 65536 distinctly addressable bytes that its instructions can manipulate. Three
segment registers are used to map this 16-bit space into a 1-megabyte space. The 16-bit
space is divided into four separate zones. Each zone, except the first or root zone, has a
segment register that is added to the 16-bit address within the zone to create a 20-bit
address. The segment register has eight bits and those eight bits are added to the upper
four bits of the 16-bit address, creating a 20-bit address. Thus, each separate zone in the
16-bit memory becomes a window to a segment of memory in the 20-bit address space.
The relative size of the four segments in the 16-bit space is controlled by the SEGSIZE
register. This is an 8-bit register that contains two 4-bit registers. This controls the bound-
ary between the first and the second segment and the boundary between the second and
the third segment. The location of the two movable segment boundaries is determined by a
4-bit value that specifies the upper four bits of the address where the boundary is located.
These relationships are illustrated in Figure 3-3.

Memory

Chips

Processor

Memory

Mapping

Unit

Memory

Interface

Unit

16
bits

20
bits

20 bits plus control

Rabbit 3000 Microprocessor User’s Manual

Figure 3-3. Example of Memory Mapping Operation

The names given to the segments in the figure are evocative of the common uses for each
segment. The

root segment

is mapped to the base of flash memory and contains the startup

code as well as other code that may happen to be stored there. The

data segment

usage

varies depending on the overall strategy for setting up memory. It may be an extension of

10000

E000

D000

7000

0000

16-bit

address space

XPC Segment

Stack Segment

Data Segment

Root Segment

20-bit

address space

00000

07000

07000
79

80000

0D000
80

8D000

0E000
85

93000

SEGSIZE
Register

10000

XPC register

STACKSEG register

DATASEG register

Chapter 3 Details on Rabbit Microprocessor Features

the root segment or it may contain data variables. The

stack segment

is normally 4K long

and it holds the system stack. The

XPC segment

is normally used to execute code that is

not stored in the root segment or the data segment. Special instructions support executing
code that is visible in the XPC segment.

The memory interface unit receives the 20-bit addresses generated by the memory-map-
ping unit. The memory interface unit conditionally modifies address lines A16, A18 and
A19. The other address lines of the 20-bit address are passed unconditionally. The mem-
ory interface unit provides control signals for external memory chips. These interface sig-
nals are chip selects (/CS0, /CS1, /CS2), output enables (/OE0, /OE1), and write enables
(/WE0, /WE1). These signals correspond to the normal control lines found on static mem-
ory chips (chip select or /CS, output enable or /OE, and write enable or /WE). In order to
generate these memory control signals, the 20-bit address space is divided into four quad-
rants of 256K each. A

bank control register

for each quadrant determines which of the

chip selects and which pair of output enables, and write enables (if any) is enabled when a
memory read or write to that quadrant takes place. For example, if a 512K x 8 flash mem-
ory is to be accessed in the first 512K of the 20-bit address space, then /CS0, /WE0, /OE0
could be enabled in both quadrants.

Figure 3-4 shows a memory interface unit.

Figure 3-4. Memory Interface Unit

/CS0

/CS1

/CS2

/OE0

/WE0

/OE1

/WE1

A19in

A18in

A18

A19

A18in

A19in

A19in'

Optional A19 inversion

Memory

Control

Memory
Control
Lines

A18, A19 invertible

by quadrant

Read/Write
Synchronization

Axxin—

from processor

Axx—

out from memory

control unit

Address lines not shown
are passed directly.

Rabbit 3000 Microprocessor User’s Manual

3.2.1 Extended Code Space

A crucial element of the Rabbit memory mapping scheme is the ability to execute pro-
grams containing up to a megabyte of code in an efficient manner. This ability is absent in
a pure 16-bit address processor, and it is poorly supported by the Z180 through its memory
mapping unit. On paged processors, such as the 8086, this capability is provided by paging
the code space so that the code is stored in many separate pages. On the 8086 the page size
is 64K, so all the code within a given page is accessible using 16-bit addressing for jumps,
calls and returns. When paging is used, a separate register (CS on the 8086) is used to
determine where the active page currently resides in the total memory space. Special
instructions make it possible to jump, call or return from one page to another. These spe-
cial instructions are called long calls, long jumps and long returns to distinguish them
from the same operations that only operate on 16-bit variables.

The Rabbit also uses a paging scheme to expand the code space beyond the reach of a 16-
bit address. The Rabbit paging scheme uses the concept of a sliding page, which is 8K
long. This is the XPC segment. The 8-bit XPC register serves as a page register to specify
the part of memory where the window points. When a program is executed in the XPC
segment, normal 16-bit jumps, calls and returns are used for most jumps within the win-
dow. Normal 16-bit jumps, calls and returns may also be used to access code in the other
three segments in the 16-bit address space. If a transfer of control to code outside the win-
dow is required, then a long jump, long call or long return is used. These instructions mod-
ify both the program counter (PC) and the XPC register, causing the XPC window to point
to a different part of memory where the target of the long jump, call or return is located.
The XPC segment is always 8K long. The granularity with which the XPC segment can be
positioned in memory is 4K. Because the window can be slid by one-half of its size, it is
possible to compile continuously without unused gaps in memory.

As the compiler generates code resident in the XPC window, the window is slid down by
4K when the code goes beyond F000. This is accomplished by a long jump that reposi-
tions the window 4K lower. This is illustrated by Figure 3-5. The compiler is not presented
with a sharp boundary at the end of the page because the window does not run out of space
when code passes F000 unless 4K more of code is added before the window is slid down.
All code compiled for the XPC window has a 24-bit address consisting of the 8-bit XPC
and the 16-bit address. Short jumps and calls can be used, provided that the source and tar-
get instructions both have the same XPC address. Generally this means that each instruc-
tion belongs to a window that is approximately 4K long and has a 16-bit address between
E000+n and F000+m, where n and m are on the order of a few dozen bytes, but can be up
to 4096 bytes in length. Since the window is limited to no more than 8K, the compiler is
unable to compile a single expression that requires more than 8K or so of code space. This
is not a practical consideration since expressions longer than a few hundred bytes are in
the nature of stunts rather than practical programs.

Program code can reside in the root segment or the XPC segment. Program code may also
be resident in the data segment. Code can be executed in the stack segment, but this is usu-
ally restricted to special situations. Code in the root, meaning any of the segments other

Chapter 3 Details on Rabbit Microprocessor Features

than the XPC segment, can call other code in the root using short jumps and calls. Code in
the XPC segment can also call code in the root using short jumps and calls. However, a
long call must be used when code in the XPC segment is called. Functions located in the
root have an efficiency advantage because a long call and a long return require 32 clocks
to execute, but a short call and a short return require only 20 clocks to execute. The differ-
ence is small, but significant for short subroutines.

Figure 3-5. Use of XPC Segment

3.2.2 Separate I and D Space - Extending Data Memory

In the normal memory model, the data space must share a 64K space with root code, the
stack, and the XPC window. Typically, this leaves a potential data space of 40K or less.
The XPC requires 8K, the stack requires 4K, and most systems will require at least 12K of
root code. This amount of data space is sufficient for many embedded applications.

One approach to getting more data space is to place data in RAM or in flash memory that
is not mapped into the 64K space, and then access this data using function calls or in
assembly language using the

LDP

instructions that can access memory using a 20-bit

address. This greatly expands the data space, but the instructions are less efficient than
instructions that access the 64k space using 16 bit addresses.

The Rabbit 3000 supports separate I and D or Instruction and Data spaces. When separate
I and D space is enabled it applies only to addresses in the root segment or data segment.
Separate I and D spaces mean that instruction execution makes a distinction between

10000

E000

D000

Stack Segment

Data Segment

Root Segment

short
calls
returns

XPC = N

PC = F000 + K

XPC = N + 1

PC = E000 + K + 4

Illustration of Sliding XPC Window

E000

F000

Compiler notices

that code has

Compiler inserts

long jump in code.

XPC Segment

passed F000.

Rabbit 3000 Microprocessor User’s Manual

fetching an instruction from memory and fetching or storing data in memory. When
enabled separate I and D space make available the combined root and data segment, typi-
cally 52k bytes for root code in the I space. In the D space, the root code segment part of
the D space is typically used for constant data mapped to flash memory while the data seg-
ment part of the D space is used for variable data mapped to RAM. Separate I and D space
increases the amount of both root code and root data because they no longer have to share
the same memory, even though they share the same addresses.

Figure 3-6. Separate I and D Space

Normally separate I and D space is implemented as shown in Figure 3-6. In the I space the
root segment and the data segment are combined into a single root code segment. In the D
space the segments are separately mapped to flash and RAM to provide storage for con-
stant data and variable data. The hardware method to achieve separate 20 bit addresses for
the D space is to invert either A16 or A19 for data accesses. The inversion may be speci-
fied separately for the root segment and the data segment. Normally A16 is inverted for
data accesses in the root segment. This causes data accesses to the root segment to be
moved 64k higher to a section of flash starting at 20 bit address 64k that is reserved for
constant data. A19 is normally inverted for data accesses to the data segment, causing the
data accesses in the data segment to be moved to an address 512k higher in the 20 bit
space, an address normally mapped to RAM. The stack segment and the XPC segment do

Constant
D Space

Variable

D Space

Root
Code

stack

XPC

window

512k

64k

RAM

Flash

128k

52k

56k

64k

20-bit Memory Space

D Space

Root
Segment

Data
Segment

I space

Chapter 3 Details on Rabbit Microprocessor Features

not have split I and D space and memory accesses to these segments do not distinguish
between I and D space.

The advantage of having more root code space is that root code executes faster because
short calls using a 16 bit address are used to call it. This compares to long calls that have a
20 bit address for extended code. Data located in the root can be more conveniently
accessed due to the comparatively limited instructions available for accessing data in the
full 20 bit space and the greater overhead involve in manipulating 20 bit addresses in a
processor that has 8 and 16 bit registers.

3.2.3 Using the Stack Segment for Data Storage

Another approach to extending data memory is to use the stack segment to access data,
placing the stack in the data segment so as to free up the stack segment. This approach
works well for a software system that uses data groupings that are self-contained and are
accessed one at a time rather than randomly between all the groupings. An example would
be the software structures associated with a TCP/IP communication protocol connection
where the same code accesses the data structures associated with each connection in a pat-
tern determined by the traffic on each connection.

The advantage of this approach is that normal C data access techniques, such as 16-bit
pointers, may be used. The stack segment register has to be modified to bring the data
structure into view in the stack segment before operations are performed on a particular
data structure. Since the stack has to be moved into the data area, it is important that the
number of stacks required be kept to a minimum when using the stack segment to view
data. Of course, tasks that don’t need to see the data structures can have their stack located
in the stack segment. Another possibility is to have a data structure and a stack located
together in the stack segment, and to use a different stack segment for different tasks, each
task having its own data area and stack bound to it.

These approaches are shown in Figure 3-7 below.

Rabbit 3000 Microprocessor User’s Manual

Figure 3-7. Schemes for Data Memory Windows

A third approach is to place the data and root code in RAM in the root segment, freeing the
data segment to be a window to extended memory. This requires copying the root code to
RAM at startup time. Copying root code to RAM is not necessarily that burdensome since
the amount of RAM required can be quite small, say 12K for example.

The XPC segment at the top of the memory can also be used as a data segment by pro-
grams that are compiled into root memory. This is handy for small programs that need to
access a lot of data.

3.2.4 Practical Memory Considerations

The simplest Rabbit configurations have one flash memory chip interfaced using /CS0 and
one RAM memory chip interfaced using /CS1. Typical Rabbit-based systems use 256K of
flash and 128 K of RAM, but smaller or larger memories may be used.

Although the Rabbit can support code size approaching a megabyte, it is anticipated that
the majority of applications will use less than 250K of code, equivalent to approximately
10,000–20,000 C statements. This reflects both the compact nature of Rabbit code and the
typical size of embedded applications.

Directly accessible C variables are limited to approximately 44K of memory, split
between data stored in flash and RAM. This will be more than adequate for many embed-

Root
Code

Data

(RAM)

Root
Code

Data

(RAM)

Stack Segment
used as data
window

Data Segment
used as data
window

Stacks in data
segment

Root Segment
mapped to
RAM has both
root code and
data.

Stack Segment
used for stack

Using Stack Segment

for a Data Window

Using Data Segment for

a Data Window (Code must

be copied to RAM on startup.)

(flash)

(RAM)

Rabbit 3000 Microprocessor User’s Manual

3.3 Instruction Set Outline

“Load Immediate Data to a Register” on page 33
“Load or Store Data from or to a Constant Address” on page 33
“Load or Store Data Using an Index Register” on page 34
“Register-to-Register Move” on page 35
“Register Exchanges” on page 35
“Push and Pop Instructions” on page 36
“16-bit Arithmetic and Logical Ops” on page 36
“Input/Output Instructions” on page 39—these include a fix for a bug that manifests itself
if an I/O instruction (prefix

IOI

IOE

) is followed by one of 12 single-byte op codes that

use HL as an index register.

In the discussion that follows, we give a few example instructions in each general category
and contrast the Z80/ Z180 with the Rabbit. For a detailed description of every instruction,
see Chapter 19, “Rabbit Instructions,”

The Rabbit executes instructions in fewer clocks then the Z80 or Z180. The Z180 usually
requires a minimum of four clocks for 1-byte opcodes or three clocks for each byte for
multi-byte op codes. In addition, three clocks are required for each data byte read or writ-
ten. Many instructions in the Z180 require a substantial number of additional clocks. The
Rabbit usually requires two clocks for each byte of the op code and for each data byte
read. Three clocks are needed for each data byte written. One additional clock is required
if a memory address needs to be computed or an index register is used for addressing.
Only a few instructions don’t follow this pattern. An example is

mul

, a 16 x 16 bit signed

two’s complement multiply.

mul

is a 1-byte op code, but requires 12 clocks to execute.

Compared to the Z180, not only does the Rabbit require fewer clocks, but in a typical situ-
ation it has a higher clock speed and its instructions are more powerful.

The most important instruction set improvements in the Rabbit over the Z180 are in the
following areas.

•

Fetching and storing data, especially 16-bit words, relative to the stack pointer or the
index registers IX, IY, and HL.

•

16-bit arithmetic and logical operations, including 16-bit and’s, or’s, shifts and 16-bit
multiply.

•

Communication between the regular and alternate registers and between the index reg-
isters and the regular registers is greatly facilitated by new instructions. In the Z180 the
alternate register set is difficult to use, while in the Rabbit it is well integrated with the
regular register set.

•

Long calls, long returns and long jumps facilitate the use of 1M of code space. This
removes the need in the Z180 to utilize inefficient memory banking schemes for larger
programs that exceed 64K of code.

Chapter 3 Details on Rabbit Microprocessor Features

•

Input/output instructions are now accomplished by normal memory access instructions
prefixed by an op code byte to indicate access to an I/O space. There are two I/O
spaces, internal peripherals and external I/O devices.

Some Z80 and Z180 instructions have been deleted and are not supported by the Rabbit
(see Chapter 20, “Differences Rabbit vs. Z80/Z180 Instructions,”). Most of the deleted
instructions are obsolete or are little-used instructions that can be emulated by several
Rabbit instructions. It was necessary to remove some instructions to free up 1-byte op
codes needed to implement new instructions efficiently. The instructions were not re-
implemented as 2-byte op codes so as not to waste on-chip resources on unimportant
instructions. Except for the instruction

EX (SP),HL

, the original Z180 binary encoding

of op codes is retained for all Z180 instructions that are retained.

3.3.1 Load Immediate Data to a Register

A constant that follows the op code in the instruction stream can generally be loaded to
any register, except PC, IP, and F. (Load to the PC is a jump instruction.) This includes the
alternate registers on the Rabbit, but not on the Z180. Some example instructions appear
below.

LD A,3

LD HL,456

LD BC',3567 ; not possible on Z180

LD H',0x4A ; not possible on Z180

LD IX,1234

LD C,54

Byte loads require four clocks, word loads require six clocks. Loads to IX, IY or the alter-
nate registers generally require two extra clocks because the op code has a 1-byte prefix.

3.3.2 Load or Store Data from or to a Constant Address

LD A,(mn) ; loads 8 bits from address mn

LD A',(mn) ; not possible on Z180

LD (mn),A

LD HL,(mn)

; load 16 bits from the address specified by mn

LD HL',(mn) ; to alternate register, not possible Z180

LD (mn),HL

Similar 16-bit loads and stores exist for DE, BC, SP, IX and IY.

It is possible to load data to the alternate registers, but it is not possible to store the data in
the alternate register directly to memory.

LD A’,(mn)

; allowed

** LD (mn),D’ ; **** not a legal instruction!

** LD (mn),DE’ ; **** not a legal instruction!

Rabbit 3000 Microprocessor User’s Manual

3.3.3 Load or Store Data Using an Index Register

An index register is a 16-bit register, usually IX, IY, SP or HL, that is used for the address
of a byte or word to be fetched from or stored to memory. Sometimes an 8-bit offset is
added to the address either as a signed or unsigned number. The 8-bit offset is a byte in the
instruction word. BC and DE can serve as index registers only for the special cases below.

LD A,(BC)

LD A’,(BC)

LD (BC),A

LD A,(DE)

LD A’,(DE)

LD (DE),A

Other 8-bit loads and stores are the following.

LD r,(HL) ; r is any of 7 registers A, B, C, D, E, H, L

LD r’,(HL) ; same but alternate register destination

LD (HL),r ; r is any of the 7 registers above

; or an immediate data byte

** LD (HL),r’ ; **** not a legal instruction!

LD r,(IX+d) ; r is any of 7 registers, d is -128 to +127 offset

LD r’,(IX+d) ; same but alternate destination

LD (IX+d),r ; r is any of 7 registers or an immediate data byte

LD (IY+d),r ; IX or IY can have offset d

The following are 16-bit indexed loads and stores. None of these instructions exists on the
Z180 or Z80. The only source for a store is HL. The only destination for a load is HL or HL'.

LD HL,(SP+d) ; d is an offset from 0 to 255.

; 16-bits are fetched to HL or HL’

LD (SP+d),HL ; corresponding store

LD HL,(HL+d) ; d is an offset from -128 to +127,

; uses original HL value for addressing

; l=(HL+d), h=(HL+d+1)

LD HL’,(HL+d)

LD (HL+d),HL

LD (IX+d),HL ; store HL at address pointed to

; by IX plus -128 to +127 offset

LD HL,(IX+d)

LD HL’,(IX+d)

LD (IY+d),HL ; store HL at address pointed to

; by IY plus -128 to +127 offset

LD HL,(IY+d)

LD HL’,(IY+d)

Chapter 3 Details on Rabbit Microprocessor Features

3.3.4 Register-to-Register Move

Any of the 8-bit registers, A, B, C, D, E, H, and L, can be moved to any other 8-bit regis-
ter, for example:

LD A,c

LD d,b

LD e,l

The alternate 8-bit registers can be a destination, for example:

LD a’,c

LD d’,b

These instructions are unique to the Rabbit and require 2 bytes and four clocks because of
the required prefix byte. Instructions such as

LD A,d’

LD d’,e’

are not allowed.

Several 16-bit register-to-register move instructions are available. Except as noted, these
instructions all require 2 bytes and four clocks. The instructions are listed below.

LD dd’,BC ; where dd’ is any of HL’, DE’, BC’ (2 bytes, 4 clocks)

LD dd’,DE

LD IX,HL

LD IY,HL

LD HL,IY

LD HL,IX

LD SP,HL ; 1-byte, 2 clocks

LD SP,IX

LD SP,IY

Other 16-bit register moves can be constructed by using 2-byte moves.

3.3.5 Register Exchanges

Exchange instructions are very powerful because two (or more) moves are accomplished
with one instruction. The following register exchange instructions are implemented.

EX af,af’ ; exchange af with af’

EXX ; exchange HL, DE, BC with HL’, DE’, BC’

EX DE,HL ; exchange DE and HL

The following instructions are unique to the Rabbit.

EX DE’,HL ; 1 byte, 2 clocks

EX DE, HL’ ; 2 bytes, 4 clocks

EX DE’, HL’ ; 2 bytes, 4 clocks

The following special instructions (Rabbit and Z180/Z80) exchange the 16-bit word on
the top of the stack with the HL register. These three instructions are each 2 bytes and 15
clocks.

EX (SP),HL

EX (SP),IX

EX (SP),IY

Rabbit 3000 Microprocessor User’s Manual

3.3.6 Push and Pop Instructions

There are instructions to push and pop the 16-bit registers AF, HL, DC, BC, IX, and IY.
The registers AF', HL', DE', and BC' can be popped. Popping the alternate registers is
exclusive to the Rabbit, and is not allowed on the Z80 / Z180.

Examples

POP HL

PUSH BC

PUSH IX

PUSH af

POP DE

POP DE’

POP HL’

3.3.7 16-bit Arithmetic and Logical Ops

The HL register is the primary 16-bit accumulator. IX and IY can serve as alternate accu-
mulators for many 16-bit operations. The Z180/Z80 has a weak set of 16-bit operations,
and as a practical matter the programmer has to resort to combinations of 8-bit operations
in order to perform many 16-bit operations. The Rabbit has many new op codes for 16-bit
operations, removing some of this weakness.

The basic Z80/Z180 16-bit arithmetic instructions are

ADD HL,ww ; where ww is HL, DE, BC, SP

ADC HL,ww ; ADD and ADD carry

SBC HL,ww ; sub and sub carry

INC ww ; increment the register (without affecting flags)

In the above op codes, IX or IY can be substituted for HL. The

ADD

and

ADC

instructions

can be used to left-shift HL with the carry. An alternate destination prefix (

ALTD

) may be

used on the above instructions. This causes the result and its flags to be stored in the corre-
sponding alternate register. If the

ALTD

flag

is used when IX or IY is the destination regis-

ter, then only the flags are stored in the alternate flag register.

The following new instructions have been added for the Rabbit.

;Shifts

RR HL

; rotate HL right with carry, 1 byte, 2 clocks

; note use ADC HL,HL for left rotate, or add HL,HL if

; no carry in is needed.

RR DE

; 1 byte, 2 clocks

RL DE ; rotate DE left with carry, 1-byte, 2 clocks

RR IX ; rotate IX right with carry, 2 bytes, 4 clocks

RR IY ; rotate IY right with carry

;Logical Operations

AND HL,DE ; 1 byte, 2 clocks

AND IX,DE ; 2 bytes, 4 clocks

AND IY,DE

OR HL,DE ; 1 byte, 2 clocks

OR IX,DE ; 2 bytes, 4 clocks

OR IY,DE

Chapter 3 Details on Rabbit Microprocessor Features

The

BOOL

instruction is a special instruction designed to help test the HL register.

BOOL

sets HL to the value 1 if HL is non zero, otherwise, if HL is zero its value is not changed.
The flags are set according to the result.

BOOL

can also operate on IX and IY.

BOOL HL

; set HL to 1 if non- zero, set flags to match HL

BOOL IX

BOOL IY

ALTD BOOL HL ; set HL’ an f’ according to HL

ALTD BOOL IY ; modify IY and set f’ with flags of result

The

SBC

instruction can be used in conjunction with the

BOOL

instruction for performing

comparisions. The

SBC

instruction subtracts one register from another and also subtracts

the carry bit. The carry out is inverted compared to the carry that would be expected if the
number subtracted was negated and added. The following examples illustrate the use of
the

SBC

and

BOOL

instructions.

; Test if HL>=DE - HL and DE unsigned numbers 0-65535

OR A

; clear carry

SBC HL,DE ; if C==0 then HL>=DE else if C==1 then HL<DE

; convert the carry bit into a boolean variable in HL

;

SBC HL,HL ; sets HL==0 if C==0, sets HL==0ffffh if C==1

BOOL HL

; HL==1 if C was set, otherwise HL==0

;

; convert not carry bit into boolean variable in HL

SBC HL,HL ; HL==0 if C==0 else HL==ffff if C=1

INC HL

; HL==1 if C==0 else HL==0 if C==1

; note carry flag set, but zero / sign flags reversed

In order to compare signed numbers using the

SBC

instruction, the programmer can map

the numbers into an equivalent set of unsigned numbers by inverting the sign bit of each
number before performing the comparison. This maps the most negative number 0x08000
to the smallest unsigned number 0x0000, and the most positive signed number 0x07FFF to
the largest unsigned number 0x0FFFF. Once the numbers have been converted, the com-
parision can be done as for unsigned numbers. This procedure is faster than using a jump
tree that requires testing the sign and overflow bits.

; example - test for HL>=DE where HL and DE are signed numbers

; invert sign bits on both

ADD HL,HL ; shift left

CCF

; invert carry

RR HL ; rotate right

RL DE

CCF

RR DE ; invert DE sign

SBC HL,DE ; no carry if HL>=DE

; generate boolean variable true if HL>=DE

SBC HL,HL ; zero if no carry else -1

INC HL ; 1 if no carry, else zero

BOOL ; use this instruction to set flags if needed

Rabbit 3000 Microprocessor User’s Manual

The

SBC

instruction can also be used to perform a sign extension.

; extend sign of l to HL

LD A,l

rla ; sign to carry

SBC A,a

; a is all 1’s if sign negative

LD h,a

; sign extended

The multiply instruction performs a signed multiply that generates a 32-bit signed result.

MUL ; signed multiply of BC and DE,

; result in HL:BC - 1 byte, 12 clocks

If a 16-bit by 16-bit multiply with a 16-bit result is performed, then only the low part of
the 32-bit result (BC) is used. This (counter intuitively) is the correct answer whether the
terms are signed or unsigned integers. The following method can be used to perform a 16
x 16 bit multiply of two unsigned integers and get an unsigned 32-bit result. This uses the
fact that if a negative number is multiplied the sign causes the other multiplier to be sub-
tracted from the product. The method shown below adds double the number subtracted so
that the effect is reversed and the sign bit is treated as a positive bit that causes an addition.

LD BC,n1

LD HL’,BC ; save BC in HL’

LD DE,n2

LD A,b

; save sign of BC

MUL

; form product in HL:BC

OR A

; test sign of BC multiplier

JR p,x1 ; if plus continue

ADD HL,DE ; adjust for negative sign in BC

x1:

RL DE

; test sign of DE

JR nc,x2 ; if not negative

; subtract other multiplier from HL

EX DE,HL’

ADD HL,DE

x2:

; final unsigned 32 bit result in HL:BC

This method can be modified to multiply a signed number by an unsigned number. In that
case only the unsigned number has to be tested to see if the sign is on, and in that case the
signed number is added to the upper part of the product.

The multiply instruction can also be used to perform left or right shifts. A left shift of n
positions can be accomplished by multiplying by the unsigned number 2^^n. This works
for n # 15, and it doesn’t matter if the numbers are signed or unsigned. In order to do a
right shift by n (0 < n < 16), the number should be multiplied by the unsigned number
2^^(16 – n), and the upper part of the product taken. If the number is signed, then a signed
by unsigned multiply must be performed. If the number is unsigned or is to be treated as
unsigned for a logical right shift, then an unsigned by unsigned multiply must be per-
formed. The problem can be simplified by excluding the case where the multiplier is
2^^15.

Rabbit 3000 Microprocessor User’s Manual

3.4 How to Do It in Assembly Language—Tips and Tricks

3.4.1 Zero HL in 4 Clocks

BOOL HL ; 2 clocks, clears carry, HL is 1 or 0

RR HL

; 2 clocks, 4 total - get rid of possible 1

This sequence requires four clocks compared to six clocks for

LD HL,0

3.4.2 Exchanges Not Directly Implemented

HL<->HL' - eight clocks

EX DE’,HL

; 2 clocks

EX DE’,HL’ ; 4 clocks

EX DE’,HL ; 2 clocks, 8 total

DE<->DE' - six clocks

EX DE’,HL ; 2 clocks

EX DE,HL ; 2 clocks

EX DE’,HL ; 2 clocks, 6 total

BC<->BC' - 12 clocks

EX DE’,HL ; 2 clocks

EX DE,HL’ ; 4

EX DE,HL ; 2

EXX ; 2

EX DE,HL ; 2

Move between IX, IY and DE, DE'

IX/IY->DE / DE->IX/IY

;IX, IX --> DE

EX DE,HL

LD HL,IX/IY / LD IX/IY,HL

EX DE,HL ; 8 clocks total

; DE --> IX/ IY

EX DE,HL

LD IX/IY,HL

EX DE,HL

; 8 clocks total

3.4.3 Manipulation of Boolean Variables

The following examples show logical operations involving HL when HL is a logical variable
with a value of 1 or 0. Such operations are important for the C language where the least bit
of a 16-bit integer is used to represent a logical result in HL

Logical

not

operator—invert bit 0 of HL in four clocks (also works for IX, IY in eight

clocks)

DEC HL

; 1 goes to zero, zero goes to -1

BOOL HL ; -1 to 1, zero to zero. 4 clocks total

Logical

xor

operator—

xor HL,DE

when HL/DE are 1 or 0.

ADD HL,DE

RES 0x1,L ; 6 clocks total, clear bit 1 result of if 1+L=2

Chapter 3 Details on Rabbit Microprocessor Features

3.4.4 Comparisons of Integers

Unsigned integers may be compared by testing the zero and carry flags after a subtract
operation. The zero flag is set if the numbers are equal. With the

SBC

instruction the carry

cleared is set if the number subtracted is less than or equal to the number it is subtracted
from. 8-bit unsigned integers span the range 0–255. 16-bit unsigned integers span the
range 0–65535.

OR A

; clear carry

SBC HL,DE ; HL=A and DE=B

A>=B !C

A<B C

A==B Z

A>B !C & !Z

A<=B C v Z

If the value

is in HL and the value

is in DE, these operations can be performed as

follows assuming that the object is to set HL to 1 or 0 depending on whether the compare
is true or false.

; compute HL<DE

; unsigned integers

; EX DE,HL ; uncomment for DE<HL

OR A ; clear carry

SBC HL,DE

; C set if HL<DE

SBC HL,HL

; HL-HL-C -- -1 if carry set

BOOL HL

; set to 1 if carry, else zero

; else result == 0

;unsigned integers

; compute HL>=DE or DE>=HL - check for !C

; EX DE,HL ; uncomment for DE<=HL

OR A ; clear carry

SBC HL,DE ; !C if HL>=DE

SBC HL,HL ; HL-HL-C - zero if no carry, -1 if C

INC HL

; 14 / 16 clocks total -if C after first SBC result 1,

; else 0

; 0 if C , 1 if !C

;

: compute HL==DE

OR A

; clear carry

SBC HL,DE ; zero is equal

BOOL HL ; force to zero, 1

DEC HL ; invert logic

BOOL HL

; 12 clocks total -logical not, 1 for inputs equal

;

Rabbit 3000 Microprocessor User’s Manual

Some simplifications are possible if one of the unsigned numbers being compared is a
constant. Note that the carry has a reverse sense from

SBC

. In the following examples, the

pseudo-code in the form

LD DE,(65535-tt)

does not indicate a load of

with the

address pointed to by

65535-tt

, but simply indicates the difference between 65535 and

the 16-bit unsigned integer

;test for HL>tt tt is constant

LD DE,(65535-tt)

ADD HL,DE ; carry set if HL>tt

SBC HL,HL ; HL-HL-C - result -1 if carry set, else zero

BOOL HL ; 14 total clocks - true if HL>tt

; HL>=tt tt is constant not zero

LD DE,(65536-tt)

ADD HL,DE

SBC HL,HL

BOOL HL

; 14 clocks

; HL>=tt and tt is zero

LD HL,0x1

; 6 clocks

; HL<tt tt is a constant, not zero (if tt==0 always false)

LD DE,(65536-tt)

ADD HL,DE ; not carry if HL<tt

SBC HL,HL ; -1 if carry, else 0

INC HL ; 14 clocks --0 if carry, else 1 if no carry

;

; HL <= tt tt is constant not zero

LD DE,(65535-tt)

ADD HL,DE ; ~C if HL<=tt

CCF ; C if true

SBC HL,HL ; if C -1 else 0

INC HL ; 16 clocks -- 1 if true, else 0

;

; HL <= tt tt is zero - true if HL==0

BOOL HL

; result in HL

;

; HL==tt and tt is a constant not zero

LD DE,(65536-tt)

ADD HL,DE ; zero if equal

BOOL HL

INC HL

RES 0x1,L ; 16 clocks

; HL==tt and tt==0

BOOL HL

INC HL

RES 0x1,L ; 8 clocks

For signed integers the conventional method is to look at the zero flag, the minus flag, and
the overflow flag. Signed 8-bit integers span the range –128 to +127 (0x80 to 0x7F).
Signed 16-bit integers span the range –32768 to + 32767 (0x8000 to 0x7FFF). The sign
and zero flag tell which is the larger number after the subtraction unless the overflow is
set, in which case the sign flag needs to be inverted in the logic, that is, it is wrong.

Chapter 3 Details on Rabbit Microprocessor Features

ss>tt (!S & !V & !Z) v (S & V)

ss<tt (S & !V) v (!S & V & !Z)

ss==tt

ss>=tt

ss<=tt

Another method of doing signed compare is to first map the signed integers onto unsigned
integers by inverting bit 15. This is shown in Figure 3-8. Once the mapping has been per-
formed by inverting bit 15 on both numbers, the comparisions can be done as if the num-
bers were unsigned integers. This avoids having to construct a jump tree to test the
overflow and sign flags. An example is shown below.

; test HL>5 for signed integers

LD DE,65535-(5+0x08000) ; 5 mapped to unsigned integers

LD BC,0x08000

ADD HL,BC ; invert high bit

ADD HL,DE ; 16 clocks to here

; carry now set if HL>5 - opportunity to jump on carry

SUBC HL,HL ; HL-HL-C ; if C on result is -1, else zero

BOOL HL ; 22 clocks total - true if HL>5 else false

Figure 3-8. Mapping Signed Integers to Unsigned Integers by Inverting Bit 15

3.4.5 Atomic Moves from Memory to I/O Space

To avoid disabling interrupts while copying a shadow register to its target register, it is
desirable to have an atomic move from memory to I/O space. This can be done using LDD
or LDI instructions.

LD HL,sh_PDDDR ; point to shadow register

LD DE,PDDDR ; set DE to point to I/O reg

SET 5,(HL) ; set bit 5 of shadow register

; use ldd instruction for atomic transfer

IOI ldd ; (io DE)<-(HL) HL--, DE--

When the LDD instruction is prefixed with an I/O prefix, the destination becomes the I/O
address specified by DE. The decrementing of HL and DE is a side effect. If the repeating
instructions LDIR and LDDR are used, interrupts can take place between successive itera-
tions. Word stores to I/O space can be used to set two I/O registers at adjacent addresses
with a single noninterruptable instruction.

0111...

000...
111...

100...

1111...

100...
011...

000...

Rabbit 3000 Microprocessor User’s Manual

3.5 Interrupt Structure

When an interrupt occurs on the Rabbit, the return address is pushed on the stack, and con-
trol is transferred to the address of the interrupt service routine. The address of the inter-
rupt service routine has two parts: the upper byte of the address comes from a special
register and the lower byte is fixed by hardware for each interrupt, as shown in Table 6-1.
There are separate registers for internal interrupts (IIR) and external interrupts (EIR) to
specify the high byte of the interrupt service routine address. These registers are accessed
by special instructions.

LD A,IIR

LD IIR,A

LD A,EIR

LD EIR,A

Interrupts are initiated by hardware devices or by certain 1-byte instructions called reset
instructions.

RST 10

RST 18

RST 20

RST 28

RST 38

The

RST

instructions are similar to those on the Z80 and Z180, but certain ones have been

removed from the instruction set (00, 08, 30). The

RST

interrupts are not inhibited regard-

less of the processor priority. The user is advised to exercise caution when using these
instructions as they are mostly reserved for the use of Dynamic C for debugging. Unlike
the Z80 or Z180, the IIR register contributes the upper byte of the service routine address
for RST interrupts.

Since interrupt routines do not affect the XPC, interrupt routines must be located in the
root code space. However, they can jump to the extended code space after saving the XPC
on the stack.

3.5.1 Interrupt Priority

The Z80 and Z180 have two levels of interrupt priority: maskable and nonmaskable. The
nonmaskable interrupt cannot be disabled and has a fixed interrupt service routine address
of 0x66. The Rabbit, in contrast, has three levels of interrupt priority and four priority lev-
els at which the processor can operate. If an interrupt is requested, and the priority of the
interrupt is higher than that of the processor, the interrupt will take place after the execu-
tion of the current instruction is complete (except for privileged instructions)

Multiple interrupt priorities have been established to make it feasible for the embedded
systems programmer to have extremely fast interrupts available.

Interrupt latency

refers to

the time required for an interrupt to take place after it has been requested. Generally, inter-
rupts of the same priority are disabled when an interrupt service routine is entered. Some-
times interrupts must stay disabled until the interrupt service routine is completed, other
times the interrupts can be re-enabled once the interrupt service routine has at least dis-
abled its own cause of interrupt. In any case, if several interrupt routines are operating at

Chapter 3 Details on Rabbit Microprocessor Features

the same priority, this introduces interrupt latency while the next routine is waiting for the
previous routine to allow more interrupts to take place. If a number of devices have inter-
rupt service routines, and all interrupts are of the same priority, then pending interrupts
can not take place until at least the interrupt service routine in progress is finished, or at
least until it changes the interrupt priority. As a rule of thumb, Rabbit Semiconductor
usually suggests that 100 µs be allowed for interrupt latency on Z180- or Rabbit-based
controllers. This can result if, for example, there are five active interrupt routines, and
each turns off the interrupts for at most 20 µs.

The intention in the Rabbit is that most interrupting devices will use priority 1 level inter-
rupts. Devices that need extremely fast response to interrupts will use priority level 2 or 3
interrupts. Since code that runs at priority level 0 or 1 never disables level 2 and level 3
interrupts, these interrupts will take place within about 20 clocks, the length of the longest
instruction or longest sensible sequence of privileged instructions followed by an unprivi-
leged instruction. It is important that the user be careful not to overdisable interrupts in
critical code sections.

The processor priority should not be raised above level 1 except in

carefully considered situations.

The effect of the processor priority on interrupts is shown in Table 3-1. The priority of the
interrupt is usually established by bits in an I/O control register associated with the hard-
ware that creates the interrupt. The 8-bit interrupt register (IP) holds the processor priority
in the least significant 2 bits. When an interrupt takes place, the IP register is shifted left 2
positions and the lower 2 bits are set to equal the priority of the interrupt that just took
place. This means that an interrupt service request (ISR) can only be interrupted by an
interrupt of higher priority (unless the priority is explicitly set lower by the programmer).
The IP register serves as a 4-word stack of 2-bit words to save and restore interrupt priori-
ties. It can be shifted right, restoring the previous priority by a special instruction (

IPRES

Since only the current processor priority and 3 previous priorities can be saved in the inter-
rupt register, instructions are also provided to

PUSH

and

POP IP

using the regular stack. A

new priority can be “pushed” into the IP register with special instructions (

IPSET 0

IPSET 1

IPSET 2

IPSET 3

Table 3-1. Effect of Processor Priorities on Interrupts

Processor

Priority

Effect on Interrupts

All interrupts, priority 1,2 and 3 take place after
execution of current non privileged instruction.

Only interrupts of priority 2 and 3 take place.

Only interrupts of priority 3 take place.

All interrupt are suppressed (except RST instruction).

Rabbit 3000 Microprocessor User’s Manual

3.5.2 Multiple External Interrupting Devices

The Rabbit 3000 has two distinct external interrupt request lines. If there are more than
two external causes of interrupts, then these lines must be shared between multiple
devices. The interrupt line is edge-sensitive, meaning that it requests an interrupt only
when a rising or falling edge, whichever is specified in the setup registers, takes place. The
state of the interrupt line(s) can always be read by reading Parallel Port E since they share
pins with Parallel Port E.

If several lines are to share interrupts with the same port, the individual interrupt requests
would normally be or’ed together so that any device can cause an interrupt. If several
devices are requesting an interrupt at the same time, only one interrupt results because
there will be only one transition of the interrupt request line. To resolve the situation and
make sure that the separate interrupt routines for the different devices are called, a good
method is to have a interrupt dispatcher in software that is aided by providing separate
attention request lines for each device. The attention request lines are basically the inter-
rupt request lines for the separate devices before they are or’ed together. The interrupt dis-
patcher calls the interrupt routines for all devices requesting interrupts in priority order so
that all interrupts are serviced.

3.5.3 Privileged Instructions, Critical Sections and Semaphores

Normally an interrupt happens at the end of the instruction currently executing. However,
if the instruction executing is

privileged

, the interrupt cannot take place at the end of the

instruction and is deferred until a non privileged instruction is executed, usually the next
instruction. Privileged instructions are provided as a handy way of making a certain oper-
ation

atomic

because there would be a software problem if an interrupt took place after the

instruction. Turning off the interrupts explicitly may be too time consuming or not possi-
ble because the purpose of the privileged instruction is to manipulate the interrupt con-
trols. For additional information on privileged instructions, see Section 19.19, “Privileged
Instructions”.

The privileged instructions to load the stack are listed below.

LD SP,HL

LD SP,IY

LD SP,IX

The following instructions to load SP are privileged because they are frequently followed
by an instruction to change the stack segment register. If an interrupt occurs between these
two instructions and the following instruction, the stack will be ill-defined.

LD SP,HL

IOI LD sseg,a

Chapter 3 Details on Rabbit Microprocessor Features

The privileged instructions to manipulate the IP register are listed below.

IPSET 0 ; shift IP left and set priority 00 in bits 1,0

IPSET 1

IPSET 2

IPSET 3

IPRES ; rotate IP right 2 bits, restoring previous priority

RETI ; pops IP from stack and then pops return address

POP IP ; pop IP register from stack

3.5.4 Critical Sections

Certain library routines may need to disable interrupts during a critical section of code.
Generally these routines are only legal to call if the processor priority is either 0 or 1. A
priority higher than this implies custom hand-coded assembly routines that do not call
general-purpose libraries. The following code can be used to disable priority 1 interrupts.

IPSET 1 ; save previous priority and set priority to 1

....critical section...

IPRES ; restore previous priority

This code is safe if it is known that the code in the critical section does not have an embed-
ded critical section. If this code is nested, there is the danger of overflowing the IP register.
A different version that can be nested is the following.

PUSH IP

IPSET 1 ; save previous priority and set priority to 1

....critical section...

POP IP ; restore previous priority

The following instructions are also privileged.

LD A,xpc

LD xpc,a

BIT B,(HL)

3.5.5 Semaphores Using Bit B,(HL)

The

bit B,(HL)

instruction is privileged to allow the construction of a semaphore by the

following code.

BIT B,(HL) ; test a bit in the byte at (HL)

SET B,(HL) ; make sure bit set, does not affect flag

; if zero flag set the semaphore belongs to us;

; otherwise someone else has it

A semaphore is used to gain control of a resource that can only belong to one task or pro-
gram at a time. This is done by testing a bit to see if it is on, in which case someone else is
using the resource, otherwise setting the bit to indicate ownership of the resource. No
interrupt can be allowed between the test of the bit and the setting of the bit as this might
allow two different program to both think they own the resource.

Chapter 4 Rabbit Capabilities

4. R

ABBIT

APABILITIES

This chapter describes the various capabilities of the Rabbit that
may not be obvious from the technical description.

4.1 Precisely Timed Output Pulses

The Rabbit can output precise pulses under software control. The effect of interrupt latency
is avoided because the interrupt always prepares a future pulse edge that is clocked into
the output registers on the next clock. This is shown in Figure 4-1.

Figure 4-1. Timed Output Pulses

The timer output in Figure 4-1 is periodic. As long as the interrupt routine can be com-
pleted during one timer period, an arbitrary pattern of synchronous pulses can be output
from the parallel port.

The interrupt latency depends on the priority of the interrupt and the amount of time that
other interrupt routines of the same or higher priority inhibit interrupts. The first instruc-
tion of the interrupt routine will start executing within 30 clocks of the interrupt request
for the highest priority interrupt routine. This includes 19 clocks for the longest instruction
to complete execution and 10 clocks for the interrupt to execute. Pushing registers requires
10–12 clocks per 16-bit register. Popping registers requires 7–9 clocks. Return from inter-
rupt requires 7 clocks. If three registers are saved and restored, and 20 instructions averag-
ing 5 clocks are executed, an entire interrupt routine will require about 200 clocks, or 10
µs with a 20 MHz clock. Given this timing, the following capabilities become possible.

Latency

Interrupt
routine sets
up B edge

Timer Output

Parallel Port Output

Timer Output

Parallel Port Output

Setup Register

Rabbit 3000 Microprocessor User’s Manual

Pulse width modulated outputs—The minimum pulse width is 10 µs. If the repetition rate
is 10 ms, then a new pulse with 1000 different widths can be generated at the rate of 100
times per second.

Asynchronous communications serial output—Asynchronous output data can be gener-
ated with a new pulse every 10 µs. This corresponds to a baud rate of 100,000 bps.

Asynchronous communications serial input—To capture asynchronous serial input, the
input must be polled faster than the baud rate, a minimum of three times faster, with five
times being better. If five times polling is used, then asynchronous input at 20,000 bps
could be received.

Generating pulses with precise timing relationships—The relationship between two events
can be controlled to within 10 µs to 20 µs.

Using a timer to generate a periodic clock allows events to be controlled to a precision of
approximately 10 µs. However, if Timer B is used to control the output registers, a preci-
sion approximately 100 times better can be achieved. This is because Timer B has a match
register that can be programmed to generate a pulse at a specified future time. The match
register has two cascaded registers, the match register and the next match register. The
match register is loaded with the contents of the next match register when a pulse is gener-
ated. This allows events to be very close together, one count of Timer B. Timer B can be
clocked by

sysclk

/2 divided by a number in the range of 1–256. Timer B can count as fast

as 10 MHz with a 20 MHz system clock, allowing events to be separated by as little as 100
ns. Timer B and the match registers have 10 bits.

Using Timer B, output pulses can be positioned to an accuracy of

clk

/2. Timer B can also

be used to capture the time at which an external event takes place in conjunction with the
external interrupt line. The interrupt line can be programmed to interrupt on either rising,
falling or both edges. To capture the time of the edge, the interrupt routine can read the
Timer B counter. The execution time of the interrupt routine up to the point where the
timer is read can be subtracted from the timer value. If no other interrupt is of the same or
higher priority, then the uncertainty in the position of the edge is reduced to the variable
time of the interrupt latency, or about one-half the execution time of the longest instruc-
tion. This uncertainty is approximately 10 clocks, or 0.5 µs for a 20 MHz clock. This
enables pulse width measurements for pulses of any length, with a precision of about 1 µs.
If multiple pulses need to be measured simultaneously, then the precision will be reduced,
but this reduction can be minimized by careful programming.

4.1.1 Pulse Width Modulation to Reduce Relay Power

Typically relays need far less current to hold them closed than is needed to initially close
them. For example, if the driver is switched to a 75% duty cycle using pulse width modu-
lation after the initial period when the relay armature is picked, the holding current will be
approximately 75% of the full duty-cycle current and the power consumption will be
about 56% as great.

Rabbit 3000 Microprocessor User’s Manual

4.3 Cold Boot

Most microprocessors start executing at a fixed address, often address zero, after a reset or
power-on condition. The Rabbit has two mode pins (SMODE0, SMODE1—see Figure 5-
1). The logic state of these two pins determines the startup procedure after a reset. If both
pins are grounded, then the Rabbit starts executing instructions at address zero. On reset,
address zero is defined to be the start of the memory connected to the memory control
lines /CS0, and /OE0. However, three other startup modes are available. These alternate
methods all involve accepting a data stream via a communications port that is used to store
a boot program in a RAM memory, which in turn can be used to start any further second-
ary boot process, such as downloading a program over the same communications port.
(For a detailed description, see Section 7.11, “Bootstrap Operation”)

Three communication channels may be used for the bootstrap, either Serial Port A in asyn-
chronous mode at 2400 bps, Serial Port A in synchronous mode with an external clock, or
the (parallel) slave port.

The cold-boot protocol accepts groups of three bytes that define an address and a data
byte. Each triplet causes a write of the data byte to either memory or to internal I/O space.
The high bit of the address is set to specify the I/O space, and thus writes are limited to the
first 32K of either space. The cold boot is terminated by a store to an address in I/O space,
which causes execution to begin at address zero. Since any memory chip can be remapped
to address zero by storing in the I/O space, RAM can be temporarily be mapped to zero to
avoid having to deal with the more complicated write protocol of flash memory, which is
the usual default memory located at address zero.

The following are the advantages of the cold-boot capability.

•

Flash memory can be soldered to the microprocessor board and programmed via a
serial port or a parallel port. This avoids having to socket the part or program it with a
BIOS or boot program before soldering.

•

Complete reprogramming of the flash memory can be accomplished in the field. This is
particularly useful during software development when the development platform can
perform a complete reload of software regardless of the state of the existing software in
the processor. The standard programming cable for Dynamic C allows the development
platform to reset and cold boot the target, a Rabbit-based microprocessor board.

•

If the Rabbit is used as a slave processor, the master processor can cold boot it over via
the slave port. This means the slave can operate without any nonvolatile memory. Only
RAM is required.

Chapter 4 Rabbit Capabilities

4.4 The Slave Port

The slave port allows a Rabbit to act as a slave to another processor, which can also be a
Rabbit. The slave has to have only a processor chip, a RAM chip, and clock and reset sig-
nals that can be supplied by the master. The master can cold boot and download a program
to the slave. The master does not have to be a Rabbit processor, but can be any type of pro-
cessor capable of reading and writing standard registers.

For a detailed description, see Chapter 13 Rabbit Slave Port

The slave processor’s slave port is connected to the master processor’s data bus. Commu-
nication between the master and the slave takes place via three registers, implemented in
the Rabbit, for each direction of communication, for a total of six data registers. In addi-
tion, there is a slave port status register that can be read by either the master or the slave
(see Figure 13-1). Two slave address lines are used by the master to select the register to
be read or written. The registers that carry data from the master to the slave appear as write
registers to the master and as read registers to the slave. The registers that operate in the
opposite direction appear as read registers to the master and as write registers to the slave.
These registers appear as read-write registers on both sides, but are not true read-write reg-
isters since different data may be read from what is written. The master provides the clock
or strobe to store data in the three write registers under its control. The master also can do
a write to the status register, which is used as a signaling device and does not actually
write to the status register. The three registers that the master can write appear as read reg-
isters to the slave Rabbit. The master provides an enable strobe to read the three read data
registers and the status register. These registers are write registers to the Rabbit.

The first register or the three pairs of registers is special in that writing can interrupt the
other processor in the master-slave communications link. An output line from the slave is
asserted when the slave writes to slave register zero. This line can be used to interrupt the
master. Internal circuits in the slave can be setup up to interrupt the slave when the master
writes to slave register zero.

The status register that is available to both sides keeps score on all the registers and reports
if a potential interrupt is requested by either side. The status register keeps track of the
"full-empty" status of each register. A register is considered full when one side of the link
writes to it. It becomes empty if the other side reads it. In this way either side can test if the
other side has modified a register or whether either side has even stored the same informa-
tion to a register.

The master-slave communication link makes possible "set and forget" communication
protocols. Either side can issue a command or request by storing data in some register and
then go about its business while the other side takes care of the request according to its
own time schedule. The other side can be alerted by an interrupt that takes place when a
store is made to register zero, or it can alert itself by a periodic poll of the status register.

Rabbit 3000 Microprocessor User’s Manual

5.1 LQFP Package

5.1.1 Pinout

Rabbit 3000 (AT56C55-IL1T, IL2T)
128-pin Low-Profile Quad Flat Pack (LQFP)
14 × 14 Body, 0.4 mm pitch

Figure 5-1. Package Outline and Pin Assignments

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

128

127

126

125

124

123

122

121

120

111

109

108

107

106

105

104

103

102

101

100

VSSIO
/OE1
A11
A9
A8
A13
A14
VSSCORE
VDDCORE
A17
/WE0
A18
A16
A15
A12
VDDIO
VSSIO
A7
A6
A5
A4
PC0, TXD
PC1, RXD
VSSCORE
VDDCORE
PC2, TXC
PC3, RXC
PC4, TXB
PC5, RXB
PC6, TXA
PC7, RXA
VDDIO

VSSIO

PF7,

AQD2A, PWM3

PF6,

AQD2B, PWM2

PF5,

AQD1A, PWM1

PF4,

AQD1B, PWM0

PB7, IA5, /SLA

VEA

TTN

PB6, IA4

PB5, IA3, SA1

PB4, IA2, SA0

PB3, IA1, /SRD

PB2, IA0, /SWR

PB1, CLKA

PB0, CLKB

VDDIO

ALA2

ALA1

VSSIO

PA7, ID7, SD7

PA6, ID6, SD6

PA5, ID5, SD5

PA4, ID4, SD4

PA3, ID3, SD3

PA2, ID2, SD2

PA1, ID1, SD1

PA0, ID0, SD0

PF3, QD2A

PF2, QD2B

PF1, QD1A, CLKC

PF0, QD1B, CLKD

/WE1

A19

VDDIO

CLK

/CS2

STATUS

/OE0

A10

/CS0

VDDCORE

VSSCORE

D7
D6
D5
D4
D3
D2

VSSIO

VDDIO

D1
D0
A0
A1
A2
A3

VDDCORE

VSSCORE

/SCS, I7, PE7

I6, PE6

INT1B, I5, PE5
INT0B, I4, PE4

I3, PE3
I2, PE2

VSSIO

VDDIO,

INT1A, I1, PE1

INT0A, I0, PE0

RXE, PG7

TXE, PG6

RCLKE, PG5

TCLKE, PG4

/IOWR

/IORD

/BUFEN

/WDIOUT

SMODE1

SMODE0

/RESET

/CS1

VSSIO

CLK32K

RESOUT

VBA

ARXA, PD7

TXA, PD6

ARXB, PD5

TXB, PD4

PD3

PD2

PD1

PD0

RXF

, PG3

TXF

, PG2

RCLKF

, PG1

TCLKF

, PG0

VSSIO

Rabbit 3000 Microprocessor User’s Manual

Figure 5-3 shows the PC board land pattern for the Rabbit 3000 chip in a 128-pin LQFP
package. This land pattern is based on the IPC-SM-782 standard developed by the Surface
Mount Land Patterns Committee and specified in

Surface Mount Design and Land Pat-

tern Standard

, IPC, Northbrook, IL, 1999.

Figure 5-3. PC Board Land Pattern for Rabbit 3000 128-pin LQFP

13.75 mm (min.)

16.85 mm (max.)

12.4 mm

15.3 mm

0.28 mm (max.)

0.40 mm

13.75 mm (min.)

16.85 mm (max.)

12.4 mm

15.3 mm

1.55 mm

: 0.290.55 mm

Toe Fillet

: 0.290.604 mm

Heel Fillet

: -0.010.077 mm

Side Fillet

TOLERANCE AND SOLDER JOINT ANALYSIS

max

: 16.85 mm

min

: 13.75 mm

X: 0.28 mm

min

max

min

Solder fillet min/max (toe, heel, and side respectively)

Toe-to-toe distance across chip

Heel-to-heel distance across chip

Toe-to-heel distance on pin

Width of pin

(max.)

Chapter 5 Pin Assignments and Functions

5.2 Ball Grid Array Package

5.2.1 Pinout

Rabbit 3000 (AT56C55-IZ1T, IZ2T)
128-pin Thin Map Ball Grid Array (TFBGA)
10 × 10 Body, 0.8 mm pitch

Figure 5-4. Ball Grid Array Pinout Looking Through the Top of Package

9 10 11 12

VDDIO

VSSIO

PF5

PB6

PB2

XTALA2

PA6

PA2

PF3

PF1

PF0

PF7

CLK

/CS2

PF6

PF4

PB5

PB1

XTALA1

PA5

PA1

PF2

/WE1

A19

STATUS

/OE0

A10

PB7

PB4

PB0

VSSIO

PA4

PA0

VDDIO

VSSIO

/OE1

/CS0

VDDCORE VSSCORE

PB3

VDDIO

PA7

PA3

A11

A13

A17

VDDCORE

VSSCORE

A14

VSSIO

VDDIO

/WE0

A18

A16

A15

VSSIO

VDDIO

A12

VDDCORE VSSCORE

PE7

PC0

VDDCORE

VSSCORE

PC1

PD0

PD4

VBAT

/CS1

/WDTOUT

PE3

PE4

PE5

PE6

PE2

VSSIO

/IOWR SMODE1 VSSIO

PD7

PD3

PG3

PG0

PC2

PC3

VDDIO

PE1

PE0

PG5

/IORD SMODE0 CLK32K

PD6

PD2

PG2

VSSIO

PC7

PC4

PC5

PC6

VDDIO

PG1

PD1

PD5

RESOUT

/RESET

/BUFEN

PG4

PG6

PG7

Rabbit 3000 Microprocessor User’s Manual

5.2.2 Mechanical Dimensions and Land Pattern

The design considerations in Table 5-3 are based on 5 mil design rules and assume a single
conductor between solder lands.

Table 5-2. Ball and Land Size Dimensions

Nominal Ball

Diameter

(mm)

Tolerance

Variation

(mm)

Ball Pitch

(mm)

Nominal Land

Diameter

(mm)

Land

Variation

(mm)

0.3

0.35–0.25

0.8

0.25

0.25–0.20

Table 5-3. Design Considerations

(all dimensions in mm)

Key

Feature

Recommendation

Solder Land Diameter

0.254 (0.010)

NSMD Defined Land Diameter

0.406 (0.016)

Land to Mask Clearance (min.)

0.050 (0.002)

Conductor Width (max.)

0.127 (0.005)

Conductor Spacing (typ.)

0.127 (0.005)

Via Capture Pad (max.)

0.406 (0.016)

Via Drill Size (max.)

0.254 (0.010)

Land and Trace

Via

Chapter 5 Pin Assignments and Functions

Figure 5-5. BGA Package Outline

12 11 10 9

0.80

10.00 ± 0.05

0.80

10.00 ± 0.05

0.20~0.30

1.20 (max.)

Ball Pitch:

Ball Diameter:

0.80 mm

0.3 mm (0.25~0.35)

TOP VIEW

BOTTOM VIEW

Rabbit 3000 Microprocessor User’s Manual

5.3 Rabbit Pin Descriptions

Table 5-1 lists all the pins on the device, along with their direction, function, and pin num-
ber on the package.

Table 5-1. Rabbit Pin Descriptions

Pin Group

Pin Name

Direction

Function

Pin

Numbers

LQFP

Pin

Numbers

TFBGA

Hardware

CLK

Output

Internal Clock

CLK32K

Input

32 kHz Oscillator In

/RESET

Input

Master Reset

RESOUT

Output

Reset Output

XTALA1

Input

Main Oscillator In—if an
external clock is used, this
pin should be driven by
the external clock; see
Technical Note TN235 for
more information on
external oscillator circuits

113

XTALA2

Output

Main Oscillator Out

114

CPU Buses

ADDR[19:0]

Output

Address Bus

various

DATA[7:0]

Bidirectional

Data Bus

10–15, 18–
19

D4, E1–E4,
F1, F4, G0

Status/Control /WDTOUT

Output

WDT Time-Out

STATUS

Output

Instruction Fetch First
Byte

SMODE[1:0]

Input

Bootstrap Mode Select

44, 45

K5, L5

Memory Chip
Selects

/CS0

Output

Memory Chip Select 0

/CS1

Output

Memory Chip Select 1

/CS2

Output

Memory Chip Select 2

Memory
Output
Enables

/OE0

Output

Memory Output Enable 0

/OE1

Output

Memory Output Enable 1

C12

Memory
Write Enables

/WE0

Output

Memory Write Enable 0

/WE1

Output

Memory Write Enable 1

B11

I/O Control

/BUFEN

Output

I/O Buffer Enable

/IORD

Output

I/O Read Enable

/IOWR

Output

I/O Write Enable

Chapter 5 Pin Assignments and Functions

I/O ports

PA[7:0]

Input / Output I/O Port A

111–104

D7, A8, B8,
C8, D8, A9,
B9, C9

I/O ports
(continued)

PB[7:0]

Input / Output I/O Port B

123–116

C4, A5, B5,
C5, D5, A6,
B6, C6

PC[7:0]

4 In / 4 Out

I/O Port C

66–71, 74,
75

L11, M11,
M12, L12,
K12, K11,
J10, H12

PD[7:0]

Input / Output I/O Port D

52–59

K7, L7, M7,
J8, K8, L8,
M8, J9

PE[7:0]

Input / Output I/O Port E

26–31, 34,
35

H4, J1–J4,
K1, L1–L2

PF[7:0]

Input / Output I/O Port F

127–124,
103–100

A3, B3, A4,
B4, A10,
B10, A11,
A12

PG[7:0]

Input / Output I/O Port G

36–38, 60–
63

M1, M2, L3,
M3, K9, L9,
M9, K10

Power,
processor core

VDDCORE

+3.3 V

8, 24, 72,
88

D2, E11, H2,
J12

Power
Processor I/O
Ring

VDDIO

+3.3 V

1, 17, 33,
65, 81, 97,
115

A1, C10, D6,
F3, G10, K3,
M10

Power Battery
Backup

VBAT

+3.3 V or battery

Ground
Processor
Core

VSSCORE

Ground

9, 25, 73,
89

D3, E10, H3,
J11

Ground
Processor I/O
Ring

VSSIO

Ground

16, 32, 48,
64, 80, 96,
112, 128

A2, C7, C11,
F2, G11, K2,
K6, L10

Table 5-1. Rabbit Pin Descriptions (continued)

Pin Group

Pin Name

Direction

Function

Pin

Numbers

LQFP

Pin

Numbers

TFBGA

Rabbit 3000 Microprocessor User’s Manual

5.4 Bus Timing

The external bus has essentially the same timing for memory cycles or I/O cycles. A mem-
ory cycle begins with the chip select and the address lines. One clock later, the output
enable is asserted for a read. The output data and the write enable are asserted for a write.

Figure 5-6. Bus Timing Read and Write

In some cases, the timing shown in Figure 5-6 may be prefixed by a false memory access
during the first clock, which is followed by the access sequence shown in Figure 5-6. In
this case, the address and often the chip select will change values after one clock and
assume the final values for the memory to be actually accessed. Output enable and write
enable are always delayed by one clock from the time the final, stable address and chip
select are enabled. Normally the false memory access attempts to start another instruction
access cycle, which is aborted after one clock when the processor realizes that a read data
or write data bus cycle is needed. The user should not attempt a design that uses the chip
select or a memory address as a clock or state changing signal without taking this into con-
sideration.

Address (20 for memory, 16 for I/O)

valid

Notes:

Read may have no wait states.

Write cycles and I/O read cycles have at least 1 wait state.

Clock may be asymmetric if clock doubler used. I/O chip
select available on Port E as option.

/IOCSn or /CSn

Data for read

/OEn or /IORD and /BUFEN (/BUFEN rd or wr)

Data for write 3-s drive starts at end of T1

/WEn or /IOWR

Chapter 5 Pin Assignments and Functions

5.5 Description of Pins with Alternate Functions

Table 5-2. Pins With Alternate Functions

Pin Name

Output Function

Input Function

Input Capture Option

PA[7:0]

SLAVE D[7:0], ID[7:0]

PB7

SLAVEATTN, IA5

PB6

IA4

/ASCS

PB5

IA3

SD1

PB4

IA2

SD0

PB3

IA1

/SRD

PB2

IA0

/SWR

PB1

CLKA

PB0

CLKB

PC7

n/a

RXA

yes

PC6

TXA

n/a

PC5

n/a

RXB

yes

PC4

TXB

n/a

PC3

n/a

RXC

yes

PC2

TXC

n/a

PC1

n/a

RXD

yes

PC0

TXD

n/a

PD7

APWM3

ARXA

yes

PD6

ATXA

PD5

APWM2

ARXB

yes

PD4

ATXB

PD3

yes

PD2

PD1

yes

PD0

PE7

/SCS (slave chip select)

PE6

PE5

INT1B

PE4

INT0B

PE3

PE2

PE1

INT1A

PE0

INT0A

Rabbit 3000 Microprocessor User’s Manual

PF7

PWM3

AQD2A

yes

PF6

PWM2

AQD2B

PF5

PWM1

AQD1A

yes

PF4

PWM0

AQD1B

PF3

QD2A

yes

PF2

QD2B

PF1

CLKC

QD1A, CLKC

yes

PF0

CLKD

QD1B, CLKD

PG7

APWM1

RXE

yes

PG6

TXE

PG5

RCLKE

RCLKE, ARXE

yes

PG4

TCLKE

TCLKE, ARCLKE

PG3

APWM0

RXF

yes

PG2

TXF

PG1

RCLKF

RCLKF, ARXF

yes

PG0

TCLKF

TCLKF, ARCLKF

* Introduced with Rabbit 3000A chip

Table 5-2. Pins With Alternate Functions (continued)

Pin Name

Output Function

Input Function

Input Capture Option

Chapter 5 Pin Assignments and Functions

The alternate output functions identified in Table 5-2 are configured by setting the appro-
priate bits in the Paralle Port x Function Register.

Table 5-3. Parallel Port x Alternate Functions

Parallel Port x Function Register

(PCFR)

(Address = 0x0055)

(PDFR)

(Address = 0x0065)

(PEFR)

(Address = 0x0075)

(PFFR)

(Address = 0x003D)

(PGFR)

(Address = 0x004D)

Bit(s)

Value

Description

7:0

The corresponding port bit functions normally.

The corresponding port bit carries its alternate signal as an output. See Table 5-4
below. Only the bits that have alternate functions listed in Table 5-4 actually have
a control bit in these registers. That is, there are four in Port C, four in Port D,
eight in Port E, four in Port F, and eight in Port G.

Table 5-4. Parallel Port x Alternate Functions Control Bits

Alternate Output Function

Bit

Port B

Port C

Port D

Port E

Port F

Port G

/SLAVEATTN, IA5

APWM3

PWM3

APWM1

IA4

TXA

ATXA

PWM2

TXE

IA3

APWM2

PWM1

RCLKE

IA2

TXB

ATXB

PWM0

TCLKE

IA1

APWM0

IA0

TXC

TXF

CLKA

CLKC

RCLKF

CLKB

TXD

CLKD

TCLKF

Rabbit 3000 Microprocessor User’s Manual

5.6 DC Characteristics

Stresses beyond those listed in Table 5-5 may cause permanent damage. The ratings are
stress ratings only, and functional operation of the Rabbit 3000 chip at these or any other
conditions beyond those indicated in this section is not implied. Exposure to the absolute
maximum rating conditions for extended periods may affect the reliability of the Rabbit
3000 chip.

Table 5-6 outlines the DC characteristics for the Rabbit 3000 at 3.3 V over the recom-
mended operating temperature range from T

= –55°C to +85°C, V

= 3.0 V to 3.6 V.

Table 5-5. Rabbit 3000 Absolute Maximum Ratings

Symbol

Parameter

Maximum Rating

Operating Temperature

-55° to +85°C

Storage Temperature

-65° to +150°C

Maximum Input Voltage:

•

Oscillator Buffer Input

•

5-V-tolerant I/O

+ 0.5 V

5.5 V

Maximum Operating Voltage

3.6 V

Table 5-6. 3.3 Volt DC Characteristics

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

Supply Voltage

3.0

3.3

3.6

High-Level Input Voltage

2.0

Low-Level Input Voltage

0.8

High-Level Output Voltage

= 6.8 mA,

= V

(min)

0.7 ×

Low-Level Output Voltage

= 6.8 mA,

= V

(min)

0.4

High-Level Input Current

(absolute worst case, all buffers)

= V

(max)

µA

Low-Level Input Current

(absolute worst case, all buffers)

= V

(max)

-10

µA

High-Impedance State
Output Current

(absolute worst case, all buffers)

= V

or V

= V

(max), no pull-up

-10

µA

Rabbit 3000 Microprocessor User’s Manual

Table 6-1. Rabbit 3000 Peripherals and Interrupt Service Vectors

On-Chip Peripheral

ISR Starting Address

Periodic Interrupt (GCSR)

{IIR[7:1], 0, 0x00}

Memory Management

No interrupts

Slave Port

{IIR[7:1], 0, 0x80}

Parallel Port A

No interrupts

Parallel Port F

No interrupts

Parallel Port B

No interrupts

Parallel Port G

No interrupts

Parallel Port C

No interrupts

Input Capture

{IIR[7:1], 1, 0xA0}

Parallel Port D

No interrupts

Parallel Port E

No interrupts

External I/O Control

No interrupts

Pulse Width Modulator

No interrupts—Rabbit 3000
{IIR[7:1], 1, 0x70}—Rabbit 3000A

Quadrature Decoder

{IIR[7:1], 1, 0x90}

External Interrupts

INT0 {EIR, 0x00}

INT1 {EIR, 0x10}

Timer A

{IIR[7:1], 0, 0xA0}

Timer B

{IIR[7:1], 0, 0xB0}

Serial Port A (async/cks)

{IIR[7:1], 0, 0xC0}

Serial Port E (async/hdlc)

{IIR[7:1], 1, 0xC0}

Serial Port B (async/cks)

{IIR[7:1], 0, 0xD0}

Serial Port F (async/hdlc)

{IIR[7:1], 1, 0xD0}

Serial Port C (async/cks)

{IIR[7:1], 0, 0xE0}

Serial Port D (async/cks)

{IIR[7:1], 0, 0xF0}

RST 10 instruction

{IIR[7:1], 0, 0x20}

RST 18 instruction

{IIR[7:1], 0, 0x30}

RST 20 instruction

{IIR[7:1], 0, 0x40}

RST 28 instruction

{IIR[7:1], 0, 0x50}

RST 38 instruction

{IIR[7:1], 0, 0x70}

Chapter 6-2 Rabbit Internal I/O Registers

6.1 Default Values for all the Peripheral Control Registers

The default values for all of the peripheral control registers are shown in Table 6-2. The
registers within the CPU affected by reset are the Stack Pointer (SP), the Program Counter
(PC), the IIR register, the EIR register, and the IP register. The IP register is set to all ones
(disabling all interrupts), while all of the other listed CPU registers are reset to all zeros.

Table 6-2. Rabbit Internal I/O Registers

Register Name

Mnemonic

I/O Address

R/W

Reset

Global Control/Status Register

GCSR

0x00

R/W

11000000

Global Clock Modulator 0 Register

GCM0R

0x0A

00000000

Global Clock Modulator 1 Register

GCM1R

0x0B

00000000

Global Power Save Control Register

GPSCR

0x0D

0000x000

Global Output Control Register

GOCR

0x0E

00000000

Global Clock Double Register

GCDR

0x0F

00000000

MMU Instruction/Data Register

MMIDR

0x10

R/W

00000000

MMU Common Base Register

STACKSEG

0x11

R/W

00000000

MMU Bank Base Register

DATASEG

0x12

R/W

00000000

MMU Common Bank Area Register

SEGSIZE

0x13

R/W

11111111

Memory Bank 0 Control Register

MB0CR

0x14

00001000

Memory Bank 1 Control Register

MB1CR

0x15

xxxxxxxx

Memory Bank 2 Control Register

MB2CR

0x16

xxxxxxxx

Memory Bank 3 Control Register

MB3CR

0x17

xxxxxxxx

MMU Expanded Code Register

MECR

0x18

R/W

xxxxx000

Memory Timing Control Register

MTCR

0x19

xxxx0000

Breakpoint/Debug Control Register

BDCR

0x1C

0xxxxxxx

Slave Port Data 0 Register

SPD0R

0x20

R/W

xxxxxxxx

Slave Port Data 1 Register

SPD1R

0x21

R/W

xxxxxxxx

Slave Port Data 2 Register

SPD2R

0x22

R/W

xxxxxxxx

Slave Port Status Register

SPSR

0x23

00000000

Slave Port Control Register

SPCR

0x24

R/W

0xx00000

Global ROM Configuration Register

GROM

0x2C

0xx00000

Global RAM Configuration Register

GRAM

0x2D

0xx00000

Global CPU Configuration Register

GCPU

0x2E

0xx00001

Rabbit 3000 Microprocessor User’s Manual

Global Revision Register

GREV

0x2F

0xx00000

Port A Data Register

PADR

0x30

R/W

xxxxxxxx

Port B Data Register

PBDR

0x40

R/W

00xxxxxx

Port B Data Direction Register

PBDDR

0x47

11000000

Port C Data Register

PCDR

0x50

R/W

x0x1x1x1

Port C Function Register

PCFR

0x55

x0x0x0x0

Port D Data Register

PDDR

0x60

R/W

xxxxxxxx

Port D Control Register

PDCR

0x64

xx00xx00

Port D Function Register

PDFR

0x65

xxxxxxxx

Port D Drive Control Register

PDDCR

0x66

xxxxxxxx

Port D Data Direction Register

PDDDR

0x67

00000000

Port D Bit 0 Register

PDB0R

0x68

xxxxxxxx

Port D Bit 1 Register

PDB1R

0x69

xxxxxxxx

Port D Bit 2 Register

PDB2R

0x6A

xxxxxxxx

Port D Bit 3 Register

PDB3R

0x6B

xxxxxxxx

Port D Bit 4 Register

PDB4R

0x6C

xxxxxxxx

Port D Bit 5 Register

PDB5R

0x6D

xxxxxxxx

Port D Bit 6 Register

PDB6R

0x6E

xxxxxxxx

Port D Bit 7 Register

PDB7R

0x6F

xxxxxxxx

Port E Data Register

PEDR

0x70

R/W

xxxxxxxx

Port E Control Register

PECR

0x74

xx00xx00

Port E Function Register

PEFR

0x75

00000000

Port E Data Direction Register

PEDDR

0x77

00000000

Port E Bit 0 Register

PEB0R

0x78

xxxxxxxx

Port E Bit 1 Register

PEB1R

0x79

xxxxxxxx

Port E Bit 2 Register

PEB2R

0x7A

xxxxxxxx

Port E Bit 3 Register

PEB3R

0x7B

xxxxxxxx

Port E Bit 4 Register

PEB4R

0x7C

xxxxxxxx

Port E Bit 5 Register

PEB5R

0x7D

xxxxxxxx

Port E Bit 6 Register

PEB6R

0x7E

xxxxxxxx

Table 6-2. Rabbit Internal I/O Registers (continued)

Register Name

Mnemonic

I/O Address

R/W

Reset

Chapter 6-2 Rabbit Internal I/O Registers

Port E Bit 7 Register

PEB7R

0x7F

xxxxxxxx

Port F Data Register

PFDR

0x38

R/W

xxxxxxxx

Port F Control Register

PFCR

0x3C

xx00xx00

Port F Function Register

PFFR

0x3D

xxxxxxxx

Port F Drive Control Register

PFDCR

0x3E

xxxxxxxx

Port F Data Direction Register

PFDDR

0x3F

00000000

Port G Data Register

PGDR

0x48

R/W

xxxxxxxx

Port G Control Register

PGCR

0x4C

xx00xx00

Port G Function Register

PGFR

0x4D

xxxxxxxx

Port G Drive Control Register

PGDCR

0x4E

xxxxxxxx

Port G Data Direction Register

PGDDR

0x4F

00000000

Input Capture Ctrl/Status Register

ICCSR

0x56

R/W

00000000

Input Capture Control Register

ICCR

0x57

xxxxxx00

Input Capture Trigger 1 Register

ICT1R

0x58

00000000

Input Capture Source 1 Register

ICS1R

0x59

xxxxxxxx

Input Capture LSB 1 Register

ICL1R

0x5A

xxxxxxxx

Input Capture MSB 1 Register

ICM1R

0x5B

xxxxxxxx

Input Capture Trigger 2 Register

ICT2R

0x5C

00000000

Input Capture Source 2 Register

ICS2R

0x5D

xxxxxxxx

Input Capture LSB 2 Register

ICL2R

0x5E

xxxxxxxx

Input Capture MSB 2 Register

ICM2R

0x5F

xxxxxxxx

I/O Bank 0 Control Register

IB0CR

0x80

000000xx

I/O Bank 1 Control Register

IB1CR

0x81

000000xx

I/O Bank 2 Control Register

IB2CR

0x82

000000xx

I/O Bank 3 Control Register

IB3CR

0x83

000000xx

I/O Bank 4 Control Register

IB4CR

0x84

000000xx

I/O Bank 5 Control Register

IB5CR

0x85

000000xx

I/O Bank 6 Control Register

IB6CR

0x86

000000xx

I/O Bank 7 Control Register

IB7CR

0x87

000000xx

PWM LSB 0 Register

PWL0R

0x88

xxxxxxxx

Table 6-2. Rabbit Internal I/O Registers (continued)

Register Name

Mnemonic

I/O Address

R/W

Reset

Rabbit 3000 Microprocessor User’s Manual

PWM MSB 0 Register

PWM0R

0x89

xxxxxxxx

PWM LSB 1 Register

PWL1R

0x8A

xxxxxxxx

PWM MSB 1 Register

PWM1R

0x8B

xxxxxxxx

PWM LSB 2 Register

PWL2R

0x8C

xxxxxxxx

PWM MSB 2 Register

PWM2R

0x8D

xxxxxxxx

PWM LSB 3 Register

PWL3R

0x8E

xxxxxxxx

PWM MSB 3 Register

PWM3R

0x8F

xxxxxxxx

Quad Decode Ctrl/Status Register

QDCSR

0x90

R/W

xxxxxxxx

Quad Decode Control Register

QDCR

0x91

00xx0000

Quad Decode Count 1 Register

QDC1R

0x94

xxxxxxxx

Quad Decode Count 2 Register

QDC2R

0x96

xxxxxxxx

Interrupt 0 Control Register

I0CR

0x98

xx000000

Interrupt 1 Control Register

I1CR

0x99

xx000000

Real Time Clock Control Register

RTCCR

0x01

00000000

Real Time Clock Byte 0 Register

RTC0R

0x02

R/W

xxxxxxxx

Real Time Clock Byte 1 Register

RTC1R

0x03

xxxxxxxx

Real Time Clock Byte 2 Register

RTC2R

0x04

xxxxxxxx

Real Time Clock Byte 3 Register

RTC3R

0x05

xxxxxxxx

Real Time Clock Byte 4 Register

RTC4R

0x06

xxxxxxxx

Real Time Clock Byte 5 Register

RTC5R

0x07

xxxxxxxx

Timer A Control/Status Register

TACSR

0xA0

R/W

00000000

Timer A Prescale Register

TAPR

0xA1

xxxxxxx1

Timer A Time Constant 1 Register

TAT1R

0xA3

xxxxxxxx

Timer A Control Register

TACR

0xA4

00000000

Timer A Time Constant 2 Register

TAT2R

0xA5

xxxxxxxx

Timer A Time Constant 8 Register

TAT8R

0xA6

xxxxxxxx

Timer A Time Constant 3 Register

TAT3R

0xA7

xxxxxxxx

Timer A Time Constant 9 Register

TAT9R

0xA8

xxxxxxxx

Timer A Time Constant 4 Register

TAT4R

0xA9

xxxxxxxx

Timer A Time Constant 10 Register

TAT10R

0xAA

xxxxxxxx

Table 6-2. Rabbit Internal I/O Registers (continued)

Register Name

Mnemonic

I/O Address

R/W

Reset

Chapter 6-2 Rabbit Internal I/O Registers

Timer A Time Constant 5 Register

TAT5R

0xAB

xxxxxxxx

Timer A Time Constant 6 Register

TAT6R

0xAD

xxxxxxxx

Timer A Time Constant 7 Register

TAT7R

0xAF

xxxxxxxx

Timer B Control/Status Register

TBCSR

0xB0

R/W

xxxxx000

Timer B Control Register

TBCR

0xB1

xxxx0000

Timer B MSB 1 Register

TBM1R

0xB2

xxxxxxxx

Timer B LSB 1 Register

TBL1R

0xB3

xxxxxxxx

Timer B MSB 2 Register

TBM2R

0xB4

xxxxxxxx

Timer B LSB 2 Register

TBL2R

0xB5

xxxxxxxx

Timer B Count MSB Register

TBCMR

0xBE

xxxxxxxx

Timer B Count LSB Register

TBCLR

0xBF

xxxxxxxx

Serial Port A Data Register

SADR

0xC0

R/W

xxxxxxxx

Serial Port A Address Register

SAAR

0xC1

R/W

xxxxxxxx

Serial Port A Long Stop Register

SALR

0xC2

R/W

xxxxxxxx

Serial Port A Status Register

SASR

0xC3

0xx00000

Serial Port A Control Register

SACR

0xC4

xx000000

Serial Port A Extended Register

SAER

0xC5

00000000

Serial Port B Data Register

SBDR

0xD0

R/W

xxxxxxxx

Serial Port B Address Register

SBAR

0xD1

R/W

xxxxxxxx

Serial Port B Long Stop Register

SBLR

0xD2

R/W

xxxxxxxx

Serial Port B Status Register

SBSR

0xD3

0xx00000

Serial Port B Control Register

SBCR

0xD4

xx000000

Serial Port B Extended Register

SBER

0xD5

00000000

Serial Port C Data Register

SCDR

0xE0

R/W

xxxxxxxx

Serial Port C Address Register

SCAR

0xE1

R/W

xxxxxxxx

Serial Port C Long Stop Register

SCLR

0xE2

R/W

xxxxxxxx

Serial Port C Status Register

SCSR

0xE3

0xx00000

Serial Port C Control Register

SCCR

0xE4

xx000000

Serial Port C Extended Register

SCER

0xE5

00000000

Serial Port D Data Register

SDDR

0xF0

R/W

xxxxxxxx

Table 6-2. Rabbit Internal I/O Registers (continued)

Register Name

Mnemonic

I/O Address

R/W

Reset

Rabbit 3000 Microprocessor User’s Manual

Serial Port D Address Register

SDAR

0xF1

R/W

xxxxxxxx

Serial Port D Long Stop Register

SDLR

0xF2

R/W

xxxxxxxx

Serial Port D Status Register

SDSR

0xF3

0xx00000

Serial Port D Control Register

SDCR

0xF4

xx000000

Serial Port D Extended Register

SDER

0xF5

00000000

Serial Port E Data Register

SEDR

0xC8

R/W

xxxxxxxx

Serial Port E Address Register

SEAR

0xC9

R/W

xxxxxxxx

Serial Port E Long Stop Register

SELR

0xCA

R/W

xxxxxxxx

Serial Port E Status Register

SESR

0xCB

0xx00000

Serial Port E Control Register

SECR

0xCC

xx000000

Serial Port E Extended Register

SEER

0xCD

00000000

Serial Port F Data Register

SFDR

0xD8

R/W

xxxxxxxx

Serial Port F Address Register

SFAR

0xD9

R/W

xxxxxxxx

Serial Port F Long Stop Register

SFLR

0xDA

R/W

xxxxxxxx

Serial Port F Status Register

SFSR

0xDB

0xx00000

Serial Port F Control Register

SFCR

0xDC

xx000000

Serial Port F Extended Register

SFER

0xDD

00000000

Watchdog Timer Control Register

WDTCR

0x08

00000000

Watchdog Timer Test Register

WDTTR

0x09

00000000

Table 6-2. Rabbit Internal I/O Registers (continued)

Register Name

Mnemonic

I/O Address

R/W

Reset

Chapter 7 Miscellaneous Functions

7. M

ISCELLANEOUS

UNCTIONS

7.1 Processor Identification

Four read-only registers are provided to allow software to identify the Rabbit micropro-
cessor and recognize the features and capabilities of the chip. Five bits in each of these
registers are unique to each version of the chip. One register is reserved for the on-chip
flash memory configuration (GROM), one register is reserved for the on-chip RAM mem-
ory configuration (GRAM), one register identifies the CPU (GCPU), and the final register
is reserved for revision identification (GREV). The Rabbit 3000 does not contain on-chip
SRAM or flash memories.

Table 7-1. Global ROM Configuration Register

Global ROM Configuration Register

(GROM)

(Address = 0x2C)

Bit(s)

Value

Description

Program fetch as a function of the SMODE pins.

(read only)

Ignore the SMODE pins program fetch function.

6:5

read

These bits report the state of the SMODE pins.

4:0

00000

ROM identifier for this version of the chip.

Table 7-2. Global RAM Configuration Register

Global RAM Configuration Register

(GRAM)

(Address = 0x2D)

Bit(s)

Value

Description

Program fetch as a function of the SMODE pins.

(read only)

Ignore the SMODE pins program fetch function.

6:5

read

These bits report the state of the SMODE pins.

4:0

00000

RAM identifier for this version of the chip.

Rabbit 3000 Microprocessor User’s Manual

7.2 Rabbit Oscillators and Clocks

The Rabbit 3000 usually requires two separate clocks. The

main clock

normally drives the

processor core and most of the peripheral devices, and the

32.768 kHz clock

drives the

battery-backable time-date clock and other circuitry.

Main Clock

An oscillator buffer is built into the Rabbit 3000 that may be used to implement the main
processor oscillator (Figure 7-1). For lowest power an external oscillator may be substi-
tuted for the built-in oscillator circuit. An oscillator implemented using the built in buffer
accepts crystals up to a frequency of 27 MHz (first overtone crystals only). This frequency
may be then doubled by the clock doubler. The component values shown in the figure for
the oscillator circuits are subject to adjustment depending on the crystal used and the oper-
ating frequency.

The Rabbit 3000 has a spectrum spreader unit that modifies the clock by shortening and
lengthening clock cycles. The effect of this is to spread the spectral energy of the clock
harmonics over a fairly wide range of frequencies. This limits the peak energy of the har-
monics and reduces EMI that may interfere with other devices as well as reducing the
readings in government mandated EMI tests. The spectrum spreader has two operating
modes, normal spreading and strong spreading. The spreader can also be turned off.

Table 7-3. Global CPU Register

Global CPU Register

(GCPU)

(Address = 0x2E)

Bit(s)

Value

Description

Program fetch as a function of the SMODE pins.

(read only)

Ignore the SMODE pins program fetch function.

6:5

read

These bits report the state of the SMODE pins.

4:0

00001

CPU identifier for this version of the chip.

Table 7-4. Global Revision Register

Global Revision Register

(GREV)

(Address = 0x2F)

Bit(s)

Value

Description

Program fetch as a function of the SMODE pins.

(read only)

Ignore the SMODE pins program fetch function.

6:5

read

These bits report the state of the SMODE pins.

4:0

00000

Revision identifier for this version of the chip.

Chapter 7 Miscellaneous Functions

32.768 kHz Clock

The 32.768 kHz clock is primarily used to clock the on-chip real-time clock. In addition, it
is also used to support remote cold boot via Serial Port A, driving the 2400 baud commu-
nications used to initiate the cold boot. Another function of the 32.768 kHz oscillator is to
drive the low power

sleepy mode

with the main oscillator shut down to reduce power. The

32.768 kHz clock can be left out of a system provided that its functions are not required.

Figure 7-1. Clock Distribution

TN235,

External 32.768 kHz Oscillator Circuits

, provides further information on oscilla-

tor circuits and selecting the values of components to use in the oscillator circuit.

Spectrum

Spreader

Clock

Doubler

f/(8,6,4,2)

22 M

330 k

32.768 kHz

= 7 pF

U1A

U2A

SN74AHC1GU04

NC7SP14

Divider

f/(1,2,4,8,16)

XTALB2

XTALB1

1 M

2.5 k

Watchdog

Timer

Real-Time

Clock

f/2

f/1

Rabbit 3000

CLK

clock out

113

114

Reference design for

32.768 kHz oscillator

Peripheral clock

Note:

Peripherals

cannot be clocked

slower than processo

Processor clock

enb

R1 and R2 control the

power consumed by the

unbuffered inverter.

VBAT

Rabbit 3000 Microprocessor User’s Manual

Table 7-5. Global Control/Status Register

Global Control/Status Register

(GCSR)

(Address = 0x00)

Bit(s)

Value

Description

7:6

(rd-only)

No Reset or Watchdog Timer time-out since the last read.

The Watchdog Timer timed out. These bits are cleared by a read of this
register.

This bit combination is not possible.

Reset occurred. These bits are cleared by a read of this register.

No effect on the Periodic interrupt. This bit will always be read as zero.

Force a Periodic interrupt to be pending.

4:2

xxx

See table below for decode of this field.

1:0

Periodic interrupts are disabled.

Periodic interrupts use Interrupt Priority 1.

Periodic interrupts use Interrupt Priority 2.

Periodic interrupts use Interrupt Priority 3.

Table 7-6. Clock Select Field of GCSR

Clock Select

Bits 4:2 GCSR

CPU Clock

Peripheral

Clock

Main

Oscillator

Power-Save CS

if Enabled by

GPSCR

000

osc/8

short CS option

001

osc/8

osc

short CS option

010

osc

none

011

osc/2

none

100

32 kHz or fraction

self-timed option

101

32 kHz or fraction

off

self-timed option

110

osc/4

short CS option

111

osc/6

short CS option

Chapter 7 Miscellaneous Functions

7.3 Clock Doubler

The clock doubler is provided to allow a lower frequency crystal to be used for the main
oscillator and to provide an added range of clock frequency adjustability. The clock dou-
bler is controlled via the Global Clock Double Register as shown in Table 7-7.

The clock doubler uses an on-chip delay circuit that must be programmed by the user at
startup if there is a need to double the clock. Table 7-8 lists the recommended delays for
the Global Clock Double Register for various oscillator frequencies.

Table 7-7. Global Clock Double Register

Global Clock Double Register

(GCDR)

(Address = 0x0F)

Bit(s)

Value

Description

7:4

xxxx

Reserved

3:0

0000

The clock doubler circuit is disabled.

0001

6 ns nominal low time

0010

7 ns nominal low time

0011

8 ns nominal low time

0100

9 ns nominal low time

0101

10 ns nominal low time

0110

11 ns nominal low time

0111

12 ns nominal low time

1000

13 ns nominal low time

1001

14 ns nominal low time

1010

15 ns nominal low time

1011

16 ns nominal low time

1100

17 ns nominal low time

1101

18 ns nominal low time

1110

19 ns nominal low time.

1111

20 ns nominal low time

Table 7-8. Recommended Delays Set In GCDR for Clock Doubler

Recommended GCDR Value

Frequency Range

≤

7.3728 MHz

7.3728–11.0592 MHz

11.0592–16.5888 MHz

16.5888–20.2752 MHz

20.2752–52.8384 MHz

>52.8384 MHz

Rabbit 3000 Microprocessor User’s Manual

When the clock doubler is used and there is no subsequent division of the clock, the output
clock will be asymmetric, as shown in Figure 7-2.

Figure 7-2. Effect of Clock Doubler

The doubled-clock low time is subject to wide (50%) variation since it depends on process
parameters, temperature, and voltage. The times given above are for a supply voltage of
3.3 V and a temperature of 25°C. The doubled-clock low time increases by 20% when the
voltage is reduced to 2.5 V, and increases by about 40% when the voltage is reduced fur-
ther to 2.0 V. The values increase or decrease by 1% for each 5°C increase or decrease in
temperature. The doubled clock is created by xor’ing the delayed and inverted clock with
itself. If the original clock does not have a 50-50 duty cycle, then alternate clocks will
have a slightly different length. Since the duty cycle of the built-in oscillator can be as
asymmetric as 52-48, the clock generated by the clock doubler will exhibit up to a 4%

Oscillator

Oscillator delayed

and inverted

Doubled clock

Delay
time

48%

52%

0.48P

0.52P

0.48P

0.52P

Data out

Example
Write
Cycle

Write pulse

Early write pulse
option

Address / CS

Output enb

Early output enb
option

Data out from mem

Example
Read
Cycle

Chapter 7 Miscellaneous Functions

7.5 Chip Select Options for Low Power

Some types of flash memory and RAM consume power whenever the chip select is
enabled even if no signals are changing. The chip select behavior of the Rabbit 3000 can
be modified to reduce unnecessary power consumption when the Rabbit 3000 is running
at a reduced clock speed. The

short chip select option

can be enabled when the processor

clock is divided (by 4, 6, or 8) so as to run at a lower speed.

The short chip select option is exercised with clock select bits 4:2 of the GCSR register as
shown in Table 7-6. Whether the chip select is normal or short is then determined by
whether bit 4 in the GPSCR register is 0 or 1.

When the short chip select option is enabled, the chip select delays turning on until the end
of the of the memory cycle when it turns on for the last 2 undivided clocks. If the clock is
divided by 6, the memory read cycle with no wait states would normally be 12 undivided
clocks long. With the short chip select, the chip select is on for only 2/12 clocks for a
memory duty cycle of 1/6. If wait states are added, the duty cycle is reduced even more.
For example, if there is one wait state and the clock is divided by 6, the memory bus cycle
will be 18 undivided clocks long and the duty cycle will be 2/18 = 1/9 with the short chip
select option enabled.

When the short chip select option is enabled, the interrupt sequence will attempt to write
the return address to the stack if an interrupt takes place immediately after an internal or
an external I/O instruction. The chip select will be suppressed during the write cycle, and
the correct return address will not be stored on the stack. This happens only when an inter-
rupt takes place immediately after an I/O instruction when the short chip select option is
enabled. Therefore, when using the short chip select option, ensure that interrupts are dis-
abled during I/O instructions (or do not use short chip select). Interrupts can be disabled
for a single I/O instruction as shown in the following example.

PUSH IP ; save interrupt state

IPSET 3 ; interrupts off

IOE LD a,(hl) ; typical I/O instruction

POP IP ; reenable interrupts

When the 32.768 kHz clock is used as the main processor clock (sleepy mode) the mem-
ory duty cycle can be reduced by enabling a

self-timed chip select

mode. When the

32.768 kHz clock is used, the clock period is approximately 32 µs, and a normal memory
read cycle without wait states will be approximately 64 µs. No more than a few hundred
nanoseconds are needed to read the memory. The main oscillator is normally shut down
when operating at 32 kHz, and no faster clock is available to time out a short chip select
cycle. To provide for a low-memory-duty cycle, a chip select and memory read can take
place under control of a delay timer that is on the chip. The cycle starts at the start of the
final 64 µs clock of the memory cycle and can be set to enable chip select for a period in
the range of 70 to 200 ns. The data are clocked in early at the end of the delay-driven
cycle. The chip select duty cycle is very small, about 0.2/128 = 1/600.

Rabbit 3000 Microprocessor User’s Manual

When operating in the 32 kHz mode, it is also possible to further divide the clock to a fre-
quency as low as 2 kHz, further reducing execution speed and current consumption.

It is anticipated that these measures would reduce operating current consumption to as low as
20 µA plus some additional leakage that would be significant at high operating temperatures.

Global Power Save Control Register

(GPSCR)

(Address = 0x0D)

Bit(s)

Value

Description

7:5

000

Self-timed chip selects are disabled.

001

This bit combination is reserved and should not be used.

01x

This bit combination is reserved and should not be used.

100

296 ns self-timed chip selects (192 ns best case, 457 ns worst case).

101

234 ns self-timed chip selects (151 ns best case, 360 ns worst case).

110

171 ns self-timed chip selects (111 ns best case, 264 ns worst case).

111

109 ns self-timed chip selects (71 ns best case, 168 ns worst case).

Normal Chip Select operation.

Short Chip Select timing when dividing main oscillator by 4, 6, or 8.

This bit is reserved and should not be used.

2:0

000

The 32 kHz clock divider is disabled.

001

This bit combination is reserved and should not be used.

01x

This bit combination is reserved and should not be used.

100

32 kHz oscillator divided by two (16.384 kHz).

101

32 kHz oscillator divided by four (8.192 kHz).

110

32 kHz oscillator divided by eight (4.096 kHz).

111

32 kHz oscillator divided by sixteen (2.048 kHz).

Rabbit 3000 Microprocessor User’s Manual

7.6 Output Pins CLK, STATUS, /WDTOUT, /BUFEN

Certain output pins can have alternate assignments as specified in Table 7-9.

Table 7-9. Global Output Control Register (GOCR = 0x0E)

Bit(s)

Value

Description

7:6

CLK pin is driven with peripheral clock.

CLK pin is driven with peripheral clock divided by 2.

CLK pin is low.

CLK pin is high.

5:4

STATUS pin is active (low) during a first opcode byte fetch.

STATUS pin is active (low) during an interrupt acknowledge.

STATUS pin is low.

STATUS pin is high.

WDTOUTB pin is low (1 cycle minimum, 2 cycles maximum, of 32 kHz).

WDTOUTB pin follows watchdog function.

This bit is ignored.

1:0

/BUFEN pin is active (low) during external I/O cycles.

/BUFEN pin is active (low) during data memory accesses.

/BUFEN pin is low.

/BUFEN pin is high.

Chapter 7 Miscellaneous Functions

7.7 Time/Date Clock (Real-Time Clock)

The time/date clock (RTC) is a 48-bit (ripple) counter that is driven by the 32.768 kHz
oscillator. The RTC is a modified ripple counter composed of six separate 8-bit counters.
The carries are fed into all six 8-bit counters at the same time and then ripple for 8 bits.
The time for this ripple to take place is a few nanoseconds per bit, and certainly should not
should not exceed 200 ns for all 8 bits, even when operating at low voltage.

The 48 bits are enough to count up 272 years at the 32 kHz clock frequency. By conven-
tion, 12 AM on January 1, 1980, is taken as time zero. Rabbit Semiconductor software
ignores the highest order bit, giving the counter a capacity of 136 years from January 1,
1980. To read the counter value, the value is first transferred to a 6-byte holding register.
Then the individual bytes may be read from the holding registers. To perform the transfer,
any data bits are written to RTC0R, the first holding register. The counter may then be
read as six 8-bit bytes at RTC0R through RTC5R. The counter and the 32 kHz oscillator
are powered from a separate power pin that can be provided with power while the remain-
der of the chip is powered down. This design makes battery backup possible. Since the
processor operates on a different clock than the RTC, there is the possibility of performing
a transfer to the holding registers while a carry is taking place, resulting in incorrect infor-
mation. In order to prevent this, the processor should do the clock read twice and make
sure that the value is the same in both reads.

If the processor is itself operating at 32 kHz, the read-clock procedure must be modified
since a number of clock counts would take place in the time needed by the slow-clocked
processor to read the clock. An appropriate modification would be to ignore the lower
bytes and only read the upper 5 bytes, which are counted once every 256 clocks or every
1/128th of a second. If the read cannot be performed in this time, further low-order bits
can be ignored.

The RTC registers cannot be set by a write operation, but they can be cleared and counted
individually, or by subset. In this manner, any register or the entire 48-bit counter can be
set to any value with no more than 256 steps. If the 32 kHz crystal is not installed and the
input pin is grounded, no counting will take place and the six registers can be used as a
small battery-backed memory. Normally this would not be very productive since the cir-
cuitry needed to provide the power switchover could also be used to battery-back a regular
low-power static RAM.

Rabbit 3000 Microprocessor User’s Manual

Table 7-10. Real-Time Clock RTCxR Data Registers

Real-Time Clock x Holding Register

(RTC0R) R/W

(Address = 0x02)

(RTC1R)

(Address = 0x03)

(RTC2R)

(Address = 0x04)

(RTC3R)

(Address = 0x05)

(RTC4R)

(Address = 0x06)

(RTC5R)

(Address = 0x07)

Bit(s)

Value

Description

7:0

Read

The current value of the 48-bit RTC holding register is returned.

Write

Writing to the RTC0R transfers the current count of the RTC to six holding
registers while the RTC continues counting.

Table 7-11. Real-Time Clock Control Register (RTCCR adr = 0x01)

Bit(s)

Value

Description

7:0

0x00

Writing a 0x00 to the RTCCR has no effect on the RTC counter.
However, depending on what the previous command was, writing
a 0x00 may either

1. disable the byte increment function or

2. cancel the RTC reset command

If the 0xC0 command is followed by a 0x00 command, only the
byte increment function will be disabled. The RTC reset will still
take place.

0x40

Arm RTC for a reset with code 0x80 or reset and byte increment
function with code 0x0C0.

0x80

Resets all six bytes of the RTC counter to 0x00 if preceeded by
arm command 0x40.

0xC0

Resets all six bytes of the RTC counter to 0x00 and enters byte
increment mode—precede this command with 0x40 arm
command.

7:6

This bit combination must be used with every byte increment write
to increment clock(s) register corresponding to bit(s) set to "1".
Example: 01001101 increments registers: 0, 2,3. The byte
increment mode must be enabled. Storing 0x00 cancels the byte
increment mode.

5:0

No effect on the RTC counter.

Increment the corresponding byte of the RTC counter.

Chapter 7 Miscellaneous Functions

7.8 Watchdog Timer

The watchdog timer is a 17-bit counter. In normal operation it is driven by the 32.768 kHz
clock. When the watchdog timer reaches any of several values corresponding to a delay of
from 0.25 to 2 seconds, it “times out.” When it times out, it emits a 1-clock pulse from the
watchdog output pin and it resets the processor via an internal circuit. To prevent this tim-
eout, the program must “hit” the watchdog timer before it times out. The hit is accom-
plished by storing a code in WDTCR. Note that although a watchdog timeout resets the
processor, it does not reset the timeout period stored in the WDTCR. This was done inten-
tionally because an application may require the initialization of the processor resulting
from the watchdog timeout to be based on a specific timeout period that is different from
that of the reset initialization.

The watchdog timer may be disabled by storing a special code in the WDTTR register.
Normally this should not be done unless an external watchdog device is used. The purpose
of the watchdog is to unhang the processor from an endless loop caused by a software
crash or a hardware upset.

It is important to use extreme care in writing software to hit the watchdog timer (or to turn
off the watchdog timer). The programmer should not sprinkle instructions to hit the watch-
dog timer throughout his program because such instructions can become part of an endless
loop if the program crashes and thus disable the recovery ability given by having a watch-
dog.

The following is a suggested method for hitting the watchdog. An array of up to 10 bytes
is set up in RAM. Each of these bytes is a virtual watchdog. To hit a virtual watchdog, a
number is stored in a byte. Every virtual watchdog is counted down by an interrupt routine
driven by a periodic interrupt. This can happen every 62.5 ms. If none of the virtual watch-
dogs has counted down to zero, the interrupt routine hits the hardware watchdog. If any
have counted down to zero, the interrupt routine disables interrupts, and then enters an
endless loop waiting for the reset. Hits of the virtual watchdogs are placed in the user’s
program at “must exercise” locations. The

Dynamic C User’s Manual

provides further

information on the use of virtual watchdogs.

Table 7-12. Watchdog Timer Control Register (WDTCR adr = 0x08)

Bit(s)

Value

Description

7:0

0x5A

Restart (hit) the watchdog timer, with a 2-second timeout period.

0x57

Restart (hit) the watchdog timer, with a 1-second timeout period.

0x59

Restart (hit) the watchdog timer, with a 500 ms timeout period.

0x53

Restart (hit) the watchdog timer, with a 250 ms timeout period.

0x5F

Restart the secondary watchdog timer (starting with Rabbit 3000A chip).

other

No effect on watchdog timer.

Rabbit 3000 Microprocessor User’s Manual

The code to do this may also hit the watchdog with a 0.25-second period to speed up the
reset. Such watchdog code must be written so that it is highly unlikely that a crash will
incorporate the code and continue to hit the watchdog in an endless loop. The following
suggestions will help.

1. Place a jump to self before the entry point of the watchdog hitting routines. This pre-

vents entry other than by a direct call or jump to the routine.

2. Before calling the routine, set a data byte to a special value and then check it in the rou-

tine to make sure the call came from the right caller. If not, go into an endless loop with
interrupts disabled.

3. Maintain data corruption flags and/or checksums. If these go wrong, go into an endless

loop with interrupts off.

Table 7-13. Watchdog Timer Test Register (WDTTR adr = 0x09)

Bit(s)

Value

Description

7:0

0x51

Clock the least significant byte of the watchdog timer from the peripheral
clock. (Intended for chip test and code 0x54 below only.)

0x52

Clock the most significant byte of the watchdog timer from the peripheral
clock. (Intended for chip test and code 0x54 below only.)

0x53

Clock both bytes of the watchdog timer, in parallel, from the peripheral
clock. (Intended for chip test and code 0x54 below only.)

0x54

Disable the watchdog timer. This value, by itself, does not disable the
watchdog timer. Only a sequence of two writes, where the first write is
0x51, 0x52, or 0x53, followed by a write of 0x54, actually disables the
watchdog timer. The watchdog timer will be re-enabled by any other write
to this register.

other

Normal clocking (32 kHz oscillator) for the watchdog timer. This is the
condition after reset.

Chapter 7 Miscellaneous Functions

7.9 System Reset

The Rabbit 3000 contains a master reset input (pin 46), which initializes everything in the
device except for the Real-Time Clock (RTC). This reset is delayed until the completion
of any write cycles in progress to prevent potential corruption of memory. If no write
cycles are in progress the reset takes effect immediately. The reset sequence requires a
minimum of 128 cycles of the fast oscillator to complete, even if no write cycles were in
progress at the start of the reset. Reset forces both the processor clock and the peripheral
clock in the divide-by-eight mode. Note that if the processor is being clocked from the 32
kHz clock, the 128 cycles of the fast oscillator will probably not be sufficient to allow any
writes in progress to be completed before the reset sequence completes and the clocks
switch to divide-by-eight mode.

During reset /CS1 is high impedance and all of the other memory and I/O control signals
are held inactive (High). After the /RESET signal becomes inactive (High) the processor
begins fetching instructions and the memory control signals begin normal operation. Note
that the default values in the Memory Bank Control Registers select four wait states per
access, so the initial program fetch memory reads are 48 clock cycles long (8 x (2 + 4)).
Software can immediately adjust the processor timing to whatever the system requires.

/CS1 is high-impedance during reset (and during power-down, when only VBAT is pow-
ered) to allow an external RAM connected to /CS1 to be powered by VBAT. This is possi-
ble because the /CS1 pin is powered by VBAT. In this case an external pull-up resistor (to
VBAT) is required on /CS1 to keep the RAM deselected during power-down. If the exter-
nal RAM connected to /CS1 is not powered by VBAT, so that any information held within
it is lost during power-down, no pull-up resistor on /CS1 is appropriate, as this would add
leakage (through the protection diode) to drain VBAT. The RESOUT signal, which is
High during reset and power-down, can be used to control an external power switch to dis-
connect VDD from supplying VBAT.

The default selection for the memory control signals consists of /CS0 and /OE0, and
writes are disabled. This selection can also be immediately programmed to match the
hardware configuration. A typical sequence would be to speed up the clock to full speed,
followed by selection of the appropriate number of wait states and the chip select signals,
output enable signals and write enable signals. At this point software would usually check
the system status to determine what type of reset just occurred and begin normal opera-
tion.

The default values for all of the peripheral control registers are shown with the following
register listing. The registers within the CPU affected by reset are the Stack Pointer (SP),
the Program Counter (PC), the IIR register, the EIR register, and the IP register. The IP
register is set to all ones (disabling all interrupts), while all of the other listed CPU regis-
ters are reset to all zeros.

Table 7-14 describes the state of the I/O pins after an external reset is recognized by the
Rabbit CPU. Note that the /RESET signal must be held low for three clocks for the proces-
sor to begin the reset sequence. There is no facility to tri-state output lines such as the
address lines and the memory and I/O control lines.

Rabbit 3000 Microprocessor User’s Manual

Table 7-14. Rabbit 3000 Reset Sequence and State of I/O Pins

Pin Name

Direction

/RESET Low

Recognized by CPU

Post-Reset

†

/RESET

Input

Low or High

High

CLK

Output

High

Operational

CLK32K

Input

Not Affected

RESOUT

Output

High

Low

XTALA1

Input

Not Affected

XTALA2

Output

Not Affected

A[19:0]

Output

Last Value

0x00000

D[7:0]

Bidirectional

High Z

/WDTOUT

Output

High

STATUS

Output

High

Operational

(as /IFTCH1)

SMODE[1:0]

Input

Not Affected

/CS0

Output

High

Operational

/CS1

Output

High Z

High

/CS2

Output

High

/OE0

Output

High

Operational

/OE1

Output

High

/WE0

Output

High

/WE1

Output

High

/BUFEN

Output

High

/IORD

Output

High

/IOWR

Output

High

PA[7:0]

Input/Output

zzzzzzzz

PB[7:0]

Input/Output

00zzzzzz

PC[7:0]

4 In/4 Out

z0z1z1z1

PD[7:0]

Input/Output

zzzzzzzz

PE[7:0]

Input/Output

zzzzzzzz

PF[7:0]

Input/Output

zzzzzzzz

PG[7:0]

Input/Output

zzzzzzzz

* A low is recognized internally by the processor after a reset

† The default state of the I/O ports after the completion of the reset and initialization

sequences

Chapter 7 Miscellaneous Functions

7.10 Rabbit Interrupt Structure

An interrupt causes a call to be executed, pushing the PC on the stack and starting to exe-
cute code at the interrupt vector address. The interrupt vector addresses have a fixed lower
byte value for all interrupts. The upper byte is adjustable by setting the registers EIR and
IIR for external and internal interrupts respectively. There are only two external interrupts
generated by transitions on certain pins in Parallel Port E.

The interrupt vectors are shown in Table 6-2.

The interrupts differ from most Z80 or Z180 interrupts in that the 256-byte tables pointed
to EIR and IIR contain the actual instructions beginning the interrupt routines rather than a
16-bit pointer to the routine. The interrupt vectors are spaced 16 bytes apart so that the
entire code will fit in the table for very small interrupt routines.

Interrupts have priority 1, 2 or 3. The processor operates at priority 0, 1, 2 or 3. If an inter-
rupt is being requested, and its priority is higher than the priority of the processor, the
interrupt will take place after then next instruction. The interrupt automatically raises the
processor’s priority to its own priority. The old processor priority is pushed into the 4-
position stack of priorities contained in the IP register. Multiple devices can be requesting
interrupts at the same time. In each case there is a latch set in the device that requests the
interrupt. If that latch is cleared before the interrupt is latched by the central interrupt
logic, then the interrupt request is lost and no interrupt takes place. This is shown in
Table 7-15. The priorities shown in this table apply only for interrupts of the same priority
level and are only meaningful if two interrupts are requested at the same time. Most of the
devices can be programmed to interrupt at priority level 1, 2 or 3.

Rabbit 3000 Microprocessor User’s Manual

In the case of the external interrupts the only action that will clear the interrupt request is
for the interrupt to take place, which automatically clears the request. A special action
must be taken in the interrupt service routine for the other interrupts.

Table 7-15. Interrupts—Priority and Action to Clear Requests

Priority

Interrupt Source

Action Required to Clear the Interrupt

Highest

External 1

Automatically cleared by the interrupt acknowledge.

External 0

Automatically cleared by the interrupt acknowledge.

Periodic (2 kHz)

Read the status from the GCSR.

Quadrature Decoder

Read the status from the QDCSR.

Timer B

Read the status from the TBSR.

Timer A

Read the status from the TASR.

Input Capture

Read the status from the ICCSR.

Slave Port

Rd: Read the data from the SPD0R, SPD1R or SPD2R.

Wr: Write data to the SPD0R, SPD1R, SPD2R or write a
dummy byte to the SPSR.

Serial Port E

Rx: Read the data from the SEDR or SEAR.

Tx: Write data to the SEDR, SEAR, SELR or write a dummy
byte to the SESR.

Serial Port F

Rx: Read the data from the SFDR or SFAR.

Tx: Write data to the SFDR, SFAR, SFLR or write a dummy
byte to the SFSR.

Serial Port A

Rx: Read the data from the SADR or SAAR.

Tx: Write data to the SADR, SAAR, SALR or write a dummy
byte to the SASR.

Serial Port B

Rx: Read the data from the SBDR or SBAR.

Tx: Write data to the SBDR, SBAR, SBLR or write a dummy
byte to the SBSR.

Serial Port C

Rx: Read the data from the SCDR or SCAR.

Tx: Write data to the SCDR, SCAR, SCLR or write a dummy
byte to the SCSR.

Lowest

Serial Port D

Rx: Read the data from the SDDR or SDAR

Tx: Write date to the SDDR, SDAR, SDLR or write a dummy
byte to the SDSR

Chapter 7 Miscellaneous Functions

7.10.1 External Interrupts

There are two external interrupts. Each interrupt has two input pins that can be used to
trigger the interrupt. The inputs have a pulse catcher that can detect rising, falling, or both
edges. The pulse needs to be present for a least three peripheral clocks to be detected.

Figure 7-6. External Interrupt Line Logic

The external interrupts take place on a transition of the input, which is programmable for
rising, falling, or both edges. Each of the interrupt pins has its own catcher device that can
be programmed separately to catch the edge transition and request the interrupt.

When the interrupt takes place, both pulse catchers associated with that interrupt are auto-
matically reset. If both edges are detected before the corresponding interrupt takes place,
because the triggering edges occur nearly simultaneously or because the interrupts are
inhibited by the processor priority, then there will be only one interrupt for the two edges
detected. The interrupt service routine can read the interrupt pins via Parallel Port E and
determine which lines experienced a transition, provided that the transitions are not too
fast. Interrupts can also be generated by setting up the matching port E bit as an output and
toggling the bit.

External interrupts are cleared automatically during the processor Interrupt Acknowledge
cycle. The Interrupt Acknowledge cycle will always immediately follow an Instruction
Fetch 1 cycle. This instruction byte is ignored, and will be the first byte fetched upon
returning from the interrupt. Interrupt Acknowledge cycles are always followed by two
memory writes to push the contents of the PC onto the stack. Execution then begins at the
appropriate interrupt vector location.

pulse

catcher

pulse

catcher

pulse

catcher

INT1A [PE1]

INT1B [PE5]

INT0A [PE0]

INT0B [PE4]

#1 interrupt acknowledge

#0 interrupt acknowledge

pulse

catcher

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7.10.2 Interrupt Vectors: INT0 - EIR,0x00/INT1 - EIR,0x08

When it is desired to expand the number of interrupts for additional peripheral devices, the
user should use the interrupt routine to dispatch interrupts to other virtual interrupt rou-
tines. Each additional interrupting device will have to signal the processor that it is
requesting an interrupt. A separate signal line is needed for each device so that the proces-
sor can determine which devices are requesting an interrupt.

The following code shows how the interrupt service routines can be written.

; External interrupt Routine #0 (programmed priority could be 3)

int2:

PUSH IP ; save interrupt priority

IPSET 1 ; set to priority really desired (1, 2, etc.)

; insert body of interrupt routine here

;

OPP IP ; get back entry priority

IPRES ; restore interrupted routine’s priority

RET ; return from interrupt

Table 7-16. Control Registers for External Interrupts

Reg Name

Reg Address

Bits 7,6

Bits 5,4

Bits 3,2

Bits 1,0

I0CR

10011000

INT0B PE4

INT0A PE0

Enb INT0

I1CR

10011001

INT1B PE5

INT1A PE1

Enb INT1

edge triggered

00-disabled

10-rising

01-falling

11-both

edge triggered

00-disabled

10-rising

01-falling

11-both

interrupt

00-disable

01-pri 1

10-pri 2

11-pri 3

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101

7.11 Bootstrap Operation

The device provides the option of bootstrap from any of three sources: from the Slave
Port, from Serial Port A in clocked serial mode, or from Serial Port A in asynchronous
mode. This is controlled by the state of the SMODE pins after reset. Bootstrap operation is
disabled if (SMODE1, SMODE0) = (0, 0).

Bootstrap operation inhibits the normal fetch of code from memory, and instead substi-
tutes the output of a small internal boot ROM for program fetches. This bootstrap program
reads groups of three bytes from the selected peripheral device. The first byte is the most
significant byte of a 16-bit address, followed by the least-significant byte of a 16-bit
address, followed by a byte of data. The bootstrap program then writes the byte of data to
the downloaded address and jumps back to the start of the bootstrap program. The most
significant bit of the address is used to determine the destination for the byte of data. If this
bit is zero, the byte is written to the memory location addressed by the downloaded
address. If this bit is one, the byte is written to the internal peripheral addressed by the
downloaded address. Note that all of the memory control signals continue to operate nor-
mally during bootstrap.

Execution of the bootstrap program automatically waits for data to become available from
the selected peripheral, and each byte transferred automatically resets the watchdog timer.
However, the watchdog timer still operates, and bytes must be transferred often enough to
prevent the watchdog timer from timing out.

Bootstrap operation is terminated when the SMODE pins are set to zero. The SMODE
pins are sampled just prior to fetching the first instruction of the bootstrap program. If the
SMODE pins are zero, instructions are fetched from normal memory starting at address
0x0000. The Slave Port Control register allows the bootstrap operation to be terminated
remotely. Writing a one to bit 7 of this register causes the bootstrap operation to terminate
immediately. So the sequence 0x80, 0x24, and 0x80 will terminate bootstrap operation.

Bootstrap operation is not restricted to the time immediately after reset because the boot
ROM is addressed by only the four least significant bits of the address. So any time that
the address ends in four zeros, if the SMODE pins are non-zero and bit 7 of the SPCR is
zero, the bootstrap program will begin execution. This allows in-line downloading from
the selected bootstrap port. Upon completion of the bootstrap operation, either by return-
ing the SMODE pins to zero or setting the bit in the SPCR, execution will continue from
where it was interrupted for the bootstrap operation.

The Slave Port is selected for bootstrap operation when (SMODE1, SMODE0) = (0, 1). In
this case the pins of Parallel Port A are used for a byte-wide data bus, and selected pins of
Parallel Ports B and E are used for the Slave Port control signals. Only Slave Port Data
Register 0 is used for bootstrap operation, and any writes to the other data registers will be
ignored by the processor, and can actually interfere with the bootstrap operation by mask-
ing the Write Empty signal.

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Serial Port A is selected for bootstrap operation as a clocked serial port when SMODE =
10. In this case bit 7 of Parallel Port C is used for the serial data and bit 1 of Parallel Port B
is used for the serial clock. Note that the serial clock must be externally supplied for boot-
strap operation. This precludes the use of a serial EEPROM for bootstrap operation.

Serial Port A is selected for bootstrap operation as an asynchronous serial port when
SMODE = 11. In this case bit 7 of Parallel Port C is used for the serial data, and the
32 kHz oscillator is used to provide the serial clock. A dedicated divide circuit allows the
use of the 32 kHz signal to provide the timing reference for the 2400 bps asynchronous
transfer. Only 2400 bps is supported for bootstrap operation, and the serial data must be
eight bits for proper operation. In the case of asynchronous bootstrap, Serial Port A
accepts either regular NRZ data or IrDA-encoded data (RZI coding with 3/16ths bit cell)
automatically. The hardware contians a monostable multivibrator triggered by the falling
edge of serial data into the data path. The one shot stretches any IrDA-encoded pulses
enough to look like NRZ data, but not so much as to interfere with real NRZ data.

When the first phase of a bootstrap is performed using Serial Port A, the TXA signal is not
needed since the bootstrap is a one-way communication. After the reset ends and the boot-
strap mode begins, TXA will be low, reflecting its function as a parallel port output bit that
is cleared by the reset. This may be interpreted as a break signal by some serial communi-
cation devices. TXA can be forced high by sending the triplet 0x80, 0x50, 0x40, which
stores 0x40 in Parallel Port C. An alternate approach is to send the triplet 0x80, 0x55,
0x40, which will enable the TXA output from bit 6 of Parallel Port C by writing to the
Parallel Port C function register (0x55).

NOTE:

Although the TXA signal is not needed during the first phase of the boot

procedure, sending the “byte triplets,” two-way communication is required once
the cold loader has been loaded.

The transfer rate in any bootstrap operation must not be too fast for the processor to exe-
cute the instruction stream. The Write Empty signal acts as an interlock when using the
Slave Port for bootstrap operation, because the next byte should not be written to the Slave
Port until the Write Empty signal is active. No such interlock exists for the clocked serial
and asynchronous bootstrap operation. In these cases, remember that the processor clock
starts out in divide-by-eight mode with four wait states, and limit the transfer rate accord-
ingly. In asynchronous mode at 2400 bps it takes about 4 ms to send each character, so no
problem is likely unless the system clock is extremely slow.

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103

7.12 Pulse Width Modulator

PWM interrupt and suppression features were added, starting with Rev. A of the Rabbit
3000 microprocessor. These are described in complete detail in Appendix B.1.13.

The Pulse Width Modulator consists of a ten-bit free running counter, and four width reg-
isters. Each PWM output is High for

+ 1 counts out of the 1024-clock count cycle, where

is the value held in the width register. The PWM output high time can optionally be

spread throughout the cycle to reduce ripple on the externally filtered PWM output. The
PWM is clocked by the output of Timer A9.

The spreading function is implemented by dividing each 1024-clock cycle into four quad-
rants of 256 clocks each. Within each quadrant, the Pulse Width Modulator uses the eight
MSBs of each pulse-width register to select the base width in each of the quadrants. This
is the equivalent to dividing the contents of the pulse-width register by four and using this
value in each quadrant. To get the exact High time, the Pulse Width Modulator uses the
two LSBs of the pulse-width register to modify the High time in each quadrant according
to the table below. The "n/4" term is the base count, formed from the eight MSBs of the
pulse-width register.

The diagram below shows a PWM output for several different width values, for both
modes of operation. Operation in the spread mode reduces the filtering requirements on
the PWM output in most cases.

Register Name

Mnemonic

I/O Address

R/W

Reset

PWM LSB 0 Register

PWL0R

0x88

xxxxxxxx

PWM MSB 0 Register

PWM0R

0x89

xxxxxxxx

PWM LSB 1 Register

PWL1R

0x8A

xxxxxxxx

PWM MSB 1 Register

PWM1R

0x8B

xxxxxxxx

PWM LSB 2 Register

PWL2R

0x8C

xxxxxxxx

PWM MSB 2 Register

PWM2R

0x8D

xxxxxxxx

PWM LSB 3 Register

PWL3R

0x8E

xxxxxxxx

PWM MSB 3 Register

PWM3R

0x8F

xxxxxxxx

Pulse Width LSBs

1st

2nd

3rd

4th

n/4 + 1

n/4

n/4 + 1

n/4

n/4 + 1

n/4

n/4 + 1

n/4

n/4 + 1

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Table 7-17. PWM LSB x Register

PWM LSB x Register

(PWL0R)

(Address = 0x88)

(PWL1R)

(Address = 0x8A)

(PWL2R)

(Address = 0x8C)

(PWL3R)

(Address = 0x8E)

Bit(s)

Value

Description

7:6

write

The least significant two bits for the Pulse Width Modulator count are stored.

5:1

* See Table B-25 to Table B-27 for configuration information involving bits 5:1 reflecting the additional

capabilities of Rev. A and later Rabbit 3000 microprocessors.

These bits are ignored.

PWM output High for single block.

Spread PWM output throughout the cycle.

Table 7-18. PWM MSB x Register

PWM MSB x Register

(PWM0R)

(Address = 0x89)

(PWM1R)

(Address = 0x8B)

(PWM2R)

(Address = 0x8D)

(PWM3R)

(Address = 0x8F)

Bit(s)

Value

Description

7:0

write

The most significant eight bits for the Pulse Width Modulator count are stored.
With a count of "n", the PWM output will be High for "n + 1" clocks out of the
1024 clocks of the PWM counter.

n = 255, normal

n = 255, spread

n = 256, spread

n = 257, spread

n = 258, spread

n = 259, spread

n = 259, normal

(256 counts)

(64 counts)

(65 counts)

(64 counts)

(65 counts)

(260 counts)

Chapter 7 Miscellaneous Functions

105

7.13 Input Capture

The two-channel Input Capture can be used to time input signals from various port pins.
Each Input Capture channel consists of a sixteen-bit counter that is clocked by the output
of Timer A8, and can be connected to one or two out of sixteen parallel port pins. The
Input Capture channel captures the state of its counter upon either of two programmed
conditions and can then generate an interrupt. The programmed conditions can also be
used to start and stop the counter.

Because the Input Capture channels synchronize their inputs to the peripheral clock (fur-
ther divided by Timer A8), there is some delay between the input transition and when an
interrupt is requested, as shown below. The status bits in the ICSxR are set coincident with
the interrupt request and are reset when read from the ICSxR.

Each Input Capture channel has two inputs, called the Start condition and the Stop condi-
tion. Each of these two inputs can be programmed to come from one of four bits (bits 1, 3,
5 or 7) in Parallel Port C, D, F or G. The two inputs can come from the same or different
pins, and are edge-sensitive. Each input can be disabled, rising-edge-sensitive, falling-
edge-sensitive or responsive to either edge polarity. Either or both inputs can generate an
Input Capture interrupt, and either or both inputs can cause the current count to be latched.

Register Name

Mnemonic

I/O Address

R/W

Reset

Input Capture Ctrl/Status Register

ICCSR

0x56

R/W

00000000

Input Capture Control Register

ICCR

0x57

xxxxxx00

Input Capture Trigger 1 Register

ICT1R

0x58

00000000

Input Capture Source 1 Register

ICS1R

0x59

xxxxxxxx

Input Capture LSB 1 Register

ICL1R

0x5A

xxxxxxxx

Input Capture MSB 1 Register

ICM1R

0x5B

xxxxxxxx

Input Capture Trigger 2 Register

ICT2R

0x5C

00000000

Input Capture Source 2 Register

ICS2R

0x5D

xxxxxxxx

Input Capture LSB 2 Register

ICL2R

0x5E

xxxxxxxx

Input Capture MSB 2 Register

ICM2R

0x5F

xxxxxxxx

PERI CLOCK

TIMER A8

CPT INPUT

INTERRUPT

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Each Input Capture counter operates in one of three modes, or can be disabled. The
counter is never automatically reset, but must be reset by a software command. Although
it does not generate an interrupt, there is a status bit which is set when the counter over-
flows (counts from 0xFFFF to 0x0000) so that software can recognize this condition. To
prevent potential stale-data problems, whenever the LSB of the latched count is read from
the ICLxR, the corresponding MSB of the latched count is transferred to a holding register
until read from the ICMxR.

In the first mode the counter starts counting at the Start condition and stops counting at the
Stop condition. This mode is useful for pulse width measurement if the Start condition and
Stop condition are assigned to the same pin. The Input Capture inputs were chosen to take
maximum advantage of this mode, to allow baud-rate detection for the serial ports and
rotational speed measurement for the Quadrature Decoder channels. Using this mode with
different inputs for the Start and Stop condition allows time-delay measurements between
two signals. This is the mode to use for high-speed pulse measurement, because only one
count latch is available, and it may be overwritten if the processor is not able to read the
latched value quickly enough. When the counter starts from a known count only the stop
count is necessary to determine the pulse width.

In the second mode the counter runs continuously and the Start and Stop conditions
merely latch the current count. This mode is useful for time-stamping the input conditions
against the time reference of the counter. If the time-stamp feature is not needed, this
mode gives the Rabbit 3000 up to four more external interrupt inputs. This mode works
well for slower-speed pulse measurement, where the processor has enough time to read
the count latched by the Start condition before the Stop condition occurs and latches a new
count.

In the third mode the counter runs continuously until the Stop condition occurs. This mode
measures the time from the software-defined counter start until the Stop condition occurs
on an input. Note that once the counter stops because of the Stop condition, it will not
resume counting until re-enabled by software.

Chapter 7 Miscellaneous Functions

107

Table 7-19. Input Capture Control/Status Register

Input Capture Control/Status Register

(ICCSR)

(Address = 0x56)

Bit(s)

Value

Description

7:2

(read)

These status bits (but not the interrupt enable bits) are cleared by the read of this
register, as is the Input Capture Interrupt.

The Input Capture 2 Start condition has not occurred.

(read)

The Input Capture 2 Start condition has occurred.

The corresponding Input Capture 2 Start interrupt is disabled.

(write)

The corresponding Input Capture 2 Start interrupt is enabled.

The Input Capture 2 Stop condition has not occurred.

(read)

The Input Capture 2 Stop condition has occurred.

The corresponding Input Capture 2 Stop interrupt is disabled.

(write)

The corresponding Input Capture 2 Stop interrupt is enabled.

The Input Capture 1 Start condition has not occurred.

(read)

The Input Capture 1 Start condition has occurred.

The corresponding Input Capture 1 Start interrupt is disabled.

(write)

The corresponding Input Capture 1 Start interrupt is enabled.

The Input Capture 1 Stop condition has not occurred.

(read)

The Input Capture 1 Stop condition has occurred.

The corresponding Input Capture 1 Stop interrupt is disabled.

(write)

The corresponding Input Capture 1 Stop interrupt is enabled.

The Input Capture 2 counter has not rolled over to all zeros.

(read)

The Input Capture 2 counter has rolled over to all zeros.

No effect on Input Capture 2 counter. This bit always reads as zero.

(write)

Reset Input Capture 2 counter to all zeros and clears the rollover latch.

The Input Capture 1 counter has not rolled over to all zeros.

(read)

The Input Capture 1 counter has rolled over to all zeros.

No effect on Input Capture 1 counter. This bit always reads as zero.

(write)

Reset Input Capture 1 counter to all zeros and clears the rollover latch.

1:0

Normal Input Capture operation.

Reserved for test. The Input Capture counter increments at both bit 0 and bit 8.
There is no carry from lower byte to higher byte.

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Rabbit 3000 Microprocessor User’s Manual

Table 7-20. Input Capture Control Register

Input Capture Control Register

(ICCR)

(Address = 0x57)

Bit(s)

Value

Description

7:2

These bits are ignored.

1:0

Input Capture interrupts are disabled.

Input Capture interrupt use Interrupt Priority 1.

Input Capture interrupt use Interrupt Priority 2.

Input Capture interrupt use Interrupt Priority 3.

Table 7-21. Input Capture Trigger x Register

Input Capture Trigger x Register

(ICT1R)

(Address = 0x58)

(ICT2R)

(Address = 0x5C)

Bit(s)

Value

Description

7:6

Disable the counter.

The counter runs from the Start condition until the Stop condition.

The counter runs continuously.

The counter runs continuously, until the Stop condition.

5:4

Disable the count latching function.

Latch the count on the Stop condition only.

Latch the count on the Start condition only.

Latch the count on either the Start or Stop condition.

3:2

Ignore the starting input.

The Start condition is the rising edge of the starting input.

The Start condition is the falling edge of the starting input.

The Start condition is either edge of the starting input.

1:0

Ignore the ending input.

The Stop condition is the rising edge of the ending input.

The Stop condition is the falling edge of the ending input.

The Stop condition is either edge of the ending input.

Chapter 7 Miscellaneous Functions

109

Table 7-22. Input Capture Source x Register

Input Capture Source x Register

(ICS1R)

(Address = 0x59)

(ICS2R)

(Address = 0x5D)

Bit(s)

Value

Description

7:6

Parallel Port C used for Start condition input.

Parallel Port D used for Start condition input.

Parallel Port F used for Start condition input.

Parallel Port G used for Start condition input.

5:4

Use port bit 1 for Start condition input.

Use port bit 3 for Start condition input.

Use port bit 5 for Start condition input.

Use port bit 7 for Start condition input.

3:2

Parallel Port C used for Stop condition input.

Parallel Port D used for Stop condition input.

Parallel Port F used for Stop condition input.

Parallel Port G used for Stop condition input.

1:0

Use port bit 1 for Stop condition input.

Use port bit 3 for Stop condition input.

Use port bit 5 for Stop condition input.

Use port bit 7 for Stop condition input.

Table 7-23. Input Capture LSB x Register

Input Capture LSB x Register

(ICL1R)

(Address = 0x5A)

(ICL2R)

(Address = 0x5E)

Bit(s)

Value

Description

7:0

read

The least significant eight bits of the latched Input Capture count are returned.
Reading the lsb of the count latches the msb of the count to avoid reading stale
data. Reading the msb of the count opens the latches.

Table 7-24. Input Capture MSB x Register

Input Capture MSB x Register

(ICM1R)

(Address = 0x5B)

(ICM2R)

(Address = 0x5F)

Bit(s)

Value

Description

7:0

read

The most significant eight bits of the latched Input capture count are returned.

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Rabbit 3000 Microprocessor User’s Manual

7.14 Quadrature Decoder

The two-channel Quadrature Decoder accepts inputs via Parallel Port F from two external
optical incremental encoder modules. Each channel of the Quadrature Decoder accepts an
in-phase (I) and a quadrature-phase (Q) signal, and provides 8-bit counters to track shaft
rotation and provide interrupts when the count goes from 0x00 to 0xFF or from 0xFF to
0x00. The Quadrature Decoder contains digital filters on the inputs to prevent false
counts. The Quadrature Decoder is clocked by the output of Timer A10.

Each Quadrature Decoder channel accepts inputs from either the upper nibble or lower
nibble of Parallel Port F. The I signal is input on an odd-numbered port bit, while the Q
signal is input on an even-numbered port bit. There is also a disable selection, which is
guaranteed not to generate a count increment or decrement on either entering or exiting
the disable state.

The operation of the counter as a function of the I and Q inputs is shown below.

Register Name

Mnemonic

I/O Address

R/W

Reset

Quad Decode Ctrl/Status Register

QDCSR

0x90

R/W

xxxxxxxx

Quad Decode Control Register

QDCR

0x91

00xx0000

Quad Decode Count 1 Register

QDC1R

0x94

xxxxxxxx

Quad Decode Count 2 Register

QDC2R

0x96

xxxxxxxx

01 02 03 04 05 06 07 08 07 06 05 04 03 02 01 00 FF

I input

Q input

Counter

Interrupt

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Table 7-25. Quadrature Decoder Control/Status Register

Quad Decode Control/Status Register

(QDCSR)

(Address = 0x90)

Bit(s)

Value

Description

Quadrature Decoder 2 did not increment from 0xFF.

(read-only)

Quadrature Decoder 2 incremented from 0xFF to 0x00. This bit is cleared by a
read of his register.

Quadrature Decoder 2 did not decrement from 0x00.

(read-only)

Quadrature Decoder 2 decremented from 0x00 to 0xFF. This bit is cleared by a
read of this register.

This bit always reads as zero.

No effect on the Quadrature Decoder 2.

(write-only)

Reset Quadrature Decoder 2 to 0x00 without causing an interrupt.

Quadrature Decoder 1 did not increment from 0xFF.

(read-only)

Quadrature Decoder 1 incremented from 0xFF to 0x00. This bit is cleared by a
read of this register.

Quadrature Decoder 1 did not decrement from 0x00.

(read-only)

Quadrature Decoder 1 decremented from 0x00 to 0xFF. This bit is cleared by a
read of this register.

This bit always reads as zero.

No effect on the Quadrature Decoder 1.

(write-only)

Reset Quadrature Decoder 1 to 0x00 without causing an interrupt.

Chapter 7 Miscellaneous Functions

113

Table 7-26. Quadrature Decoder Control Register

Quad Decode Control Register

(QDCR)

(Address = 0x91)

Bit(s)

Value

Description

7:6

Disable Quadrature Decoder 2 inputs. Writing a new value to these bits will not
cause Quadrature Decoder 2 to increment or decrement.

This bit combination is reserved and should not be used.

Quadrature Decoder 2 inputs from Port F bits 3 and 2.

Quadrature Decoder 2 inputs from Port F bits 7 and 6.

5:4

These bits are ignored.

3:2

Disable Quadrature Decoder 1 inputs. Writing a new value to these bits will not
cause Quadrature Decoder 1 to increment or decrement.

This bit combination is reserved and should not be used.

Quadrature Decoder 1 inputs from Port F bits 1 and 0.

Quadrature Decoder 1 inputs from Port F bits 5 and 4.

1:0

Quadrature Decoder interrupts are disabled.

Quadrature Decoder interrupt use Interrupt Priority 1.

Quadrature Decoder interrupt use Interrupt Priority 2.

Quadrature Decoder interrupt use Interrupt Priority 3.

Table 7-27. Quadrature Decoder Count Register

Quad Decode Count Register

(QDC1R)

(Address = 0x94)

(QDC2R)

(Address = 0x96)

Bit(s)

Value

Description

7:0

read

The current value of the Quadrature Decoder counter is reported.

Chapter 8 Memory Interface and Mapping

115

8. M

EMORY

NTERFACE

AND

APPING

8.1 Interface for Static Memory Chips

Static memory chips generally have address lines, data line, a chip select line, an output
enable line and a write enable. The Rabbit 3000 has these same lines that can connect
directly to a number of static memory chips. The chip selects are not completely inter-
changeable because certain chip selects have special functions. When the processor starts
up, not in cold boot mode, execution starts at address zero in the memory attached to /CS0.
A static RAM should be connected to /CS1 because Dynamic C development tools
assume a static RAM connected to /CS1.

In addition /CS1 has special features that support battery backing of static RAM. When
the processor power is removed but battery power is supplied to the battery power pin
(VBAT) /CS1 is held in a high impedance state. This allows a pull up resistor to the bat-
tery backup power to hold /CS1 high and thus hold the static memory chip in standby
mode. The RESOUT pin is also held high while the processor is powered down and bat-
tery power is supplied to VBAT. This allows the RESOUT pin to be used to control power
to the processor and the static RAM chip via a transistor.

It is also possible to force /CS1 to be enabled at all times. This is convenient if an external
battery backup device is used that might slow down the transition of /CS1 during the
memory cycle. Most users will not use this feature.

Figure 8-1. Battery-Backup Circuit

Rabbit 3000

RESOUT

3.3 V

Main Power

Rabbit 3000

VBAT

SRAM

VDD

/CS

Rabbit 3000

/CS

100 k

5 k

3 V

(

channel)

FDV302P

Chapter 8 Memory Interface and Mapping

117

8.2 Memory Mapping Overview

See Section 3.2, “Memory Mapping,” for a discussion of Rabbit memory mapping.

Figure 8-3 shows an overview of the Rabbit memory mapping. The task of the memory
mapping unit is to accept 16-bit addresses and translate them to 20-bit addresses. The
memory interface unit accepts the 20-bit addresses and generates control signals applied
directly to the memory chips.

Figure 8-3. Overview of Rabbit Memory Mapping

8.3 Memory-Mapping Unit

The 64K 16-bit address space accessed by processor instructions is divided into segments.
Each segment has a length that is a multiple of 4K. Except for the extended code segment,
the segments have adjustable sizes and some segments can be reduced to zero size and
thus vanish from the memory map.

The four segments are shown in the example in Figure 8-4. The segment size register
(SEGSIZE) determines the boundaries marked in the diagram. The extended code seg-
ment always occupies the addresses 0x0E000–0x0FFFF. The stack segment stretches from
the address specified by the upper 4 bits of the SEGSIZE register to 0x0DFFF. For exam-
ple, if the upper 4 bits of SEGSIZE are 0x0D, then the stack segment will occupy
0x0D000–0x0DFFF, or 4K. If the upper 4 bits of SEGSIZE are greater than or equal to
0x0E, the stack segment vanishes. If these bits are set to zero, the two segments below the
stack segment will vanish.

The lower 4 bits of SEGSIZE determine the lower boundary shown in the figure. If this
boundary is equal to the upper boundary or greater than 0x0E, the data segment will van-
ish. If this segment is placed at zero the code segment will vanish.

Memory

Chips

Processor

Memory

Mapping

Unit

Memory

Interface

Unit

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Figure 8-4. Memory Segments

The memory management unit accepts a 16-bit address from the processor and translates
it into a 20-bit address. The procedure to do this works as follows.

1. It is determined which segment the 16-bit address belongs to by inspecting the upper 4

bits of the address. Every address must belong to one of the possible 4 segments.

2. Each segment has an 8-bit segment register. The 8-bit segment register is added to the

upper 4 bits of the 16-bit address to create a 20-bit address. Wraparound occurs if the
addition would result in an address that does not fit in 20 bits.

Table 8-1. Segment Registers

Segment Register

Function

XPC

Locates extended code segment in physical memory. Read and written by
processor instructions:

ld a,xpc

ld xpc,a

lcall

lret

ljp

STACKSEG = 0x11

Locates stack segment in physical memory.

DATASEG = 0x12

Locates data segment in physical memory.

Table 8-2. Segment Size Register

Bits 7..4

Bits 3..0

SEGSIZE = 0x13

Boundary address stack segment.

Boundary address data segment.

Extended code

XPC segment
(8K)

Stack segment

(4K typ)

Root segment

Data segment

64K

Boundary SEGSIZE[4..7]

Boundary SEGSIZE[0..3]

XPC

STACKSEG

DATASEG

16-bit address

20-bit address

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8.5 Memory Bank Control Registers

Table 8-3 describes the operation of the four memory bank control registers. The registers
are write-only. Each register controls one quadrant in the 1M address space.

Bits 7,6—The number of wait states used in access to this quadrant. Without wait states, read requires

2 clocks and write requires 3 clocks. The wait state adds to these numbers. Wait states should only
be used for memory data accesses (RAM or data flash), not for memory from which instructions are
executed (code memory).

Bits 5, 4—These bits allow the upper address lines to be inverted. This inversion occurs after the logic

that selects the bank register, so setting these lines has no effect on which bank register is used. The
inversion may be used to install a 1M memory chip in the space normally allocated to a 256K chip.
The larger memory can then be accessed as 4 pages of 256K each. There is no effect outside the
quadrant that the memory bank control register is controlling.

Table 8-3. Memory Bank Control Register x (MBxCR = 0x014 + x)

Memory Bank x Control Register

(MB0CR)

(Address = 0x014)

(MB1CR)

(Address = 0x015)

(MB2CR)

(Address = 0x016)

(MB3CR)

(Address = 0x017)

Bit(s)

Value

Description

7:6

Four wait states for accesses in this bank.

Two wait states for accesses in this bank.

One wait states for accesses in this bank.

Zero wait states for accesses in this bank.

Pass A[19] for accesses in this bank.

Invert A[19] for accesses in this bank.

Pass A[18] for accesses in this bank.

Invert A[18] for accesses in this bank.

3:2

/OE0 and /WE0 are active for accesses in this bank

/OE1 and /WE1 are active for accesses in this bank

/OE0 only is active for accesses in this bank (i.e. read-only). Transactions are
normal in every other way.

/OE1 only is active for accesses in this bank (i.e. read-only). Transactions are
normal in every other way.

1:0

/CS0 is active for accesses in this bank.

/CS1 is active for accesses in this bank.

/CS2 is active for accesses in this bank.

Chapter 8 Memory Interface and Mapping

121

Bit 3—Inhibits the write pulse to memory accessed in this quadrant. Useful for protecting flash mem-

ory from an inadvertent write pulse, which will not actually write to the flash because it is protected
by lock codes, but will temporarily disable the flash memory and crash the system if the memory is
used for code.

Bit 2—Selects which set of the two lines /OEx and /WEx will be driven for memory accesses in this

quadrant.

Bits 1,0—Determines which of the three chip select lines will be driven for memory accesses to this

quadrant.

All bits of the control register are initialized to zero on reset.

8.5.1 Optional A16, A19 Inversions by Segment (/CS1 Enable)

The inversion of A19 or A16 controlled by the read/write MMIDR register is used to
redirect mapping of the root segment and the data segment by inverting certain bits when
these segments are accessed.

The optional enable of /CS1 is valuable for systems that are pushing the access time of
battery-backed RAM. By enabling /CS1, the delay time of the switch that forces /CS1
high when power is off can be bypassed. This feature increases power consumption since
the RAM is always enabled and its access is controlled normally by /OE1.

Table 8-4. MMU Instruction/Data Register (MMIDR = 0x010)

* See Table B-20 for information on bit 7 for Rabbit 3000A and later versions.

MMU Instruction/Data Register

(MMIDR)

(Address = 0x010)

Bit(s)

Value

Description

7:6

These bits are ignored and always return zeros when read.

Enable A16 and A19 inversion independent of instruction/data.

Enable A16 and A19 inversion (controlled by bits 0–3) for data accesses only.
This enables the instruction/data split. This is separate I and D space.

Normal /CS1 operation.

Force /CS1 always active. This will not cause any conflicts as long as the
memory using /CS1 does not also share an Output Enable or Write Enable with
another memory.

Normal operation.

For a DATASEG access, invert A19 before MBxCR (bank select) decision.

Normal operation.

For a DATASEG access: invert A16

Normal operation.

For root access, invert A19 before MBxCR (bank select) decision.

Normal operation.

For root access, invert A16

Chapter 8 Memory Interface and Mapping

123

The Memory Timing Control Register (MTCR) enables the extended timing for the memory
output enables and write enables. See Figure 7-2 for details on how the timing of the mem-
ory read and write strobes is affected when using the early output enable and write enable
options. Figure 16-3 shows extended output enable and write enable timing diagrams.

Table 8-5. MMU Expanded Code Register (MECR = 0x018)

MMU Expanded Code Register

(MECR)

(Address = 0x018)

Bit(s)

Value

Description

7:3

These bits are ignored for write, and return zeros when read.

2:0

0xx

Normal operation.

100

For an XPC access, use MB0CR independent of A19-A18.

101

For an XPC access, use MB1CR independent of A19-A18.

110

For an XPC access, use MB2CR independent of A19-A18.

111

For an XPC access, use MB3CR independent of A19-A18.

Table 8-6. Memory Timing Control Register (MTCR, adr = 0x019)

Memory Timing Control Register

(MTCR)

(Address = 0x019)

Bit(s)

Value

Description

7:4

xxxx

These bits are reserved and should not be used.

Normal timing for /OE1B (rising edge to rising edge, one clock minimum).

Extended timing for /OE1B (one-half clock earlier than normal).

Normal timing for /OE0B (rising edge to rising edge, one clock minimum).

Extended timing for /OE0B (one-half clock earlier than normal).

Normal timing for /WE1B (rising edge to falling edge, one and one-half clocks
minimum).

Extended timing for /WE1B (falling edge to falling edge, two clocks minimum).

Normal timing for /WE0B (rising edge to falling edge, one and one-half clocks
minimum).

Extended timing for /WE0B (falling edge to falling edge, two clocks minimum).

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The Breakpoint/Debug controller allows the RST 28 instruction to be used as a software
breakpoint. Normally the RST 28 instruction causes a call to a particular location in mem-
ory, but the operation of this instruction is modified when the breakpoint/debug feature is
enabled. The RST 28 instruction is treated as a NOP in the breakpoint/debug mode.

8.6 Allocation of Extended Code and Data

The Dynamic C compiler compiles code to root code space or to extended code space.
Root code starts in low memory and compiles upward.

Allocation of extended code starts above the root code and data. Allocation normally con-
tinues to the end of the flash memory.

Data variables are allocated to RAM working backwards in memory. Allocation normally
starts at 52K in the 64K D space and continues. The 52K space must be shared with the
root code and data, and is allocated upward from zero.

Dynamic C also supports extended data constants. These are mixed in with the extended
code in flash.

Table 8-7. Breakpoint/Debug Control Register (BDCR, adr = 0x01C )

Breakpoint/Debug Control Register

(BDCR)

(Address = 0x01C)

Bit(s)

Value

Description

Normal RST 28 operation.

RST 28 is NOP.

6:0

These bits are reserved and should not be used.

Chapter 8 Memory Interface and Mapping

125

8.7 Instruction and Data Space Support

Instruction and Data space (I and D space) support is accomplished by optionally invert-
ing address lines A16 and/or A19 when the processor accesses D space, but not inverting
those lines when the processor accesses I space. The MMIDR register (see Table 8-8) is
used to control this inversion. It is important to understand that the bit inversion of A16
and A19 associated with I and D space occurs

before

the upper 2 bits of the 20-bit address

are used to determine the quadrant and thus the bank register that is going to control mem-
ory access. This contrasts with the optional address bit inversion of A19 and A18 con-
trolled by the 4 memory bank control registers (see Table 8-3) that takes place

after

the

quadrant has been computed.

To make this clear, let’s look at an example. Suppose a 1 megabyte flash memory is con-
trolled by /CS0, /WE0, and /OE0. Suppose this memory is accessed as part of the first
quadrant and MB0CR is set up to enable /CS0 and /WE0 or /OE0 on accesses to this bank.
Then if A18 and A19 are zero, the first 256K of the flash memory will be visible in the
first 256K of the physical memory. If access is made to the second quadrant, the memory
will not be selected unless MB1CR is mapped to the flash memory. However, if A18 is
inverted by setting bit 4 in MB0CR to a 1, then the second 256K of the flash will be
mapped into the first quadrant. A18 will have been inverted, but he quadrant does not
change because this inversion occurs after the quadrant has been selected.

The inversion of A19 or A16 controlled by the MMIDR register on D space accesses is
used to separate I and D space to different memory locations. The separation of I and D
space can only occur for the first two memory zones in the64K space. For each zone, the
root code segment and the data segment either or both of A19 and A16 can be inverted.
The reasoning behind these choices is that a normal memory map places flash memory in
the lower 512K of the physical memory space. RAM memory begins at 512K. By invert-
ing A19 on D space accesses, memory mapped to the lower 512K and held in flash will be
switched to RAM for D accesses. By inverting A16, D accesses will be switched to an
adjacent 64K page, which would normally still be in the lower 512K memory or flash. To
see how this works consider that data are of two different types—constants stored in flash
memory and variables, which must be stored in RAM. Because there are two types of data,
it is desirable to divide the D space into two zones, one for constants and one for variables,
as shown in Figure 8-5. In a combined I and D space model the root code segment holds
both code and data constants in flash memory. The data segment holds data variables in
RAM. In the separate I and D space model, the root code segment and the data segment

Table 8-8. Use of MMIDR Register to Control Inversion of Address Lines A16 and A19

Bits 7:5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

000

1–force
/CS1
always
enabled

1–Invert A19 for
data accesses in data
segment before
quadrant selection

1–Invert A16 for
data accesses in
data segment

1–Invert A19 for
data accesses in root
segment before
quadrant selection

1–Invert A16 for
data accesses in
root segment.

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are mapped into contiguous regions of memory to create a continuous root code segment
starting at the bottom of physical memory in flash. In the I space the division between the
root segment and the data segment is irrelevant because the DATASEG register contains
zero and the division between the segments defined by the lower 4 bits of the SEGSIZE
register does not mark a division in physical memory for code space. However, if for D
space accesses A16 is inverted for the root segment and A19 is inverted for the data seg-
ment, then root segment data is mapped to the next 64k of flash and data segment data is
mapped to a place in memory 512K higher in the RAM. This divides the data space into
two separate segments for constants and variables. If the stack segment (which is still
combined I and D space) and the extended code segment (also combined I and D space)
occupy 12K at the top of the 64K space, then the remaining 52K is doubled into a 52K
code space in flash and a 52K data space, which may be split into two parts, one for con-
stants and one for variables. The relative size of the two parts depends on the lower 4 bits
of the SEGSIZE register, which define the 4K page boundary between the root segment
and the data segment.

Figure 8-5. Combined versus Separate I & D Space

The use of physical memory that goes with this map is shown in Figure 8-6, “Use of Phys-
ical Memory Separate I & D Space Model,” on page 127. In this figure "n" is the number
of 4k pages devoted to D space constants. In the figure it is assumed that the lower 512k of
memory is entirely composed of flash memory and the upper 512K is entirely RAM. This
does not have to be the case. For example, if a low-cost 32K x 8 RAM is used and mapped
to the 3rd quadrant using /CS1, the RAM memory will begin at 512K and will be repeated
8 times in the 3rd quadrant from addresses 512K to 768K. Since the memory repeats, it
can be considered to start at any address and continue for 32K. At least 4K of RAM is
needed for the stack segment, so if a 32K RAM is used, a maximum of 28K would be
available for storing data variables. If more stack segments are needed, the amount of data
variable space would be corresponding reduced.

Combined I & D

Root

Code

I-Space

64k

D-Space

Const

D-Space

Var

(RAM)

(flash)

Extended Code

Stack

RAM

Root

Code &

Data

(flash)

Separate I & D

52k

(4*n) k

Allocate
vars

Allocate
consts

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8.8 How the Compiler Compiles to Memory

The compiler actually generates code for root code and constants and extended code and
extended constants. It allocates space for data variables, but does not generate data bits to
be stored in memory.

In any but the smallest programs, most of the code is compiled to extended memory. This
code executes in the 8K window from E000 to FFFF. This 8K window uses paged access.
Instructions that use 16-bit addressing can jump within the page and also outside of the
page to the remainder of the 64K space. Special instructions, particularly long call, long
jump and long return, are used to access code outside of the 8K window. When one of
these transfer of control instructions is executed, both the address and the view through the
8K window or page are changed. This allows transfer to any instruction in the 1M memory
space. The 8-bit XPC register controls which of the 256 4K pages the 8K window aligns
with. The 16-bit PC controls the address of the instruction, usually in the region E000 to
FFFF. The advantage of paged access is that most instructions continue to use 16-bit
addressing. Only when an out-of-range transfer of control is made does a 20-bit transfer of
control need to be made. The beauty of having a 4K minimum step in page alignment
while the size of the page is 8K is that code can be compiled continuously without gaps
caused by change of page. When the page is moved by 4K, the previous end of code is still
visible in the window, provided that the midpoint of the page was crossed before moving
the page alignment.

As the compiler compiles code in the extended code window, it checks at opportune times
to see if the code has passed the midpoint of the window or F000. When the code passes
F000, the compiler slides the window down by 4K so that the code at F000+x becomes
resident at E000+x. This results in the code being divided into segments that are typically
4K long, but which can very short or as long as 8K. Transfer of control can be accom-
plished within each segment by 16-bit addressing; 20-bit addressing is required between
segments.

Chapter 9 Parallel Ports

129

9. P

ARALLEL

ORTS

The Rabbit has seven 8-bit parallel ports designated A, B, C, D, E, F, and G. The pins used
for the parallel ports are also shared with numerous other functions as shown in Table 5-2.
The important properties of the ports are summarized below.

•

Port A—Shared with the slave port data interface and auxiliary I/O data bus.

•

Port B—Shared with control lines for slave port, auxiliary I/O address bus, and clock
I/O for clocked serial mode option for Serial Ports A and B.

•

Port C—Shared with serial port data I/O.

•

Port D—4 bits shared with alternate I/O pins for Serial Ports A and B. 4 bits not shared.
Port D can be configured as open drain outputs. Port D also contains output preload
registers that can be clocked into the output registers under timer control for pulse gen-
eration.

•

Port E—All bits of Port E can be configured as I/O strobes. 4 bits of port E can be used
as external interrupt inputs. One bit of port E is shared with the slave port chip select.
Port E has output preload registers that can be clocked into the output registers under
timer control for pulse generation.

•

Port F— As outputs, Port F can be configured as open drain outputs. Alternatively, Par-
allel Port F outputs can carry the four Pulse-Width Modulator outputs. As inputs, Paral-
lel Port F inputs can carry the inputs to the two channels of the quadrature decoders.
Port F pins can also be configured to be used as clock pins for clocked Serial Ports C
and D.

•

Port G—As outputs, Port G can be configured as open drain outputs. Port G inputs and
outputs are also used for access to other serial peripherals on the chip such as those
used for asynchronous or SDLC/HDLC communication.

•

Parallel Ports D–G behave in the same manner when used as digital I/O.

NOTE:

There may be a conflict in using Parallel Port A and Parallel Port F. Either Paral-

lel Port A can be used as inputs, in which case Parallel Port F has full function, or if
Parallel Port A cannot be used as inputs, use any pins on Parallel Port F not used for
PWM or serial clock outputs as inputs and take the precaution of setting up Parallel Port
F before the conflicting functionality of Parallel Port A is enabled. Refer to
Section 9.6.1, “Using Parallel Port A and Parallel Port F,” for more information.

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9.1 Parallel Port A

Parallel Port A has a single read/write register:

This register should not be used if the slave port or auxiliary I/O bus is enabled.

The slave port control register is used to control whether Parallel Port A is configured as
slave databus, auxiliary I/O data bus, parallel Input or parallel output. To make the port an
input, store 0x080 in the SPCR (slave port control register). To make the port an output,
store 0x084 in SPCR. Parallel Port A is set up as an input port on reset.

When the port is read, the value read reflects the voltages on the pins, "1" for high and "0"
for low. This could be different than the value stored in the output register if the pin is
forced to a different state by an external voltage.

NOTE:

Refer to Section 9.6.1, “Using Parallel Port A and Parallel Port F,” for more

information.

Table 9-1. Parallel Port A Registers

Register Name

Mnemonic

I/O address

R/W

Reset

Port A Data Register

PADR

0x30

R/W

xxxxxxxx

Slave Port Control Register

SPCR

0x24

R/W

0xx00000

Table 9-2. Parallel Port A Data Register Bit Functions

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PADR (R/W)

adr = 0x030

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

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131

9.2 Parallel Port B

Parallel Port B, has eight pins that can programmed individually to be inputs and outputs.

After reset, Parallel Port B comes up as six inputs (PB[5:0]) and two outputs (PB7 and
PB6). The output value on pins PB6 and PB7 (package pins 99, 100) will be low.

When the auxiliary I/O bus is enabled, Parallel Port B bits 2:7 provide 6 address lines, the
least significant 6 lines of the 16 lines that define the full I/O space.

When the slave port is enabled, parallel port lines PB2–PB7 are assigned to various slave
port functions. However, it is still possible to read PB0–PB5 using the Port B data register
even when lines PB2–PB7 are used for the slave port. It is also possible to read the signal
driving PB6 and PB7 (this signal is on the signaling lines from the slave port logic).

Regardless of whether the slave port is enabled, PB0 reflects the input of the pin unless
Serial Port B has its internal clock enabled, which causes this line to be driven by the serial
port clock. PB1 reflects the input of the pin unless Serial Port A has its internal clock
enabled.

•

PBDR—Parallel Port B data register. Read/Write.

•

PBDDR—Parallel Port B data direction register. A "1" makes the corresponding pin an
output. This register is write only.

Table 9-3. Parallel Port B Registers

Register Name

Mnemonic

I/O address

R/W

Reset

Port B Data Register

PBDR

0x40

R/W

00xxxxxx

Port B Data Direction Register

PBDDR

0x47

11000000

Table 9-4. Parallel Port B Register Bit Functions

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PBDR
(R/W)

adr = 0x040

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PBDDR
(W)
adr = 0x047

dir =

out

dir =

out

dir =

out

dir =

out

dir =

out

dir =

out

dir =

out

dir =

out

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9.3 Parallel Port C

Parallel Port C, shown in Table 9-6, has four inputs and four outputs. The even-numbered
ports, PC0, PC2, PC4, and PC6, are outputs. The odd-numbered ports, PC1, PC3, PC5,
and PC7, are inputs. When the data register is read, bits 1,3,5,7 return the value of the volt-
age on the pin. Bits 0,2,4,6 return the value of the signal driving the output buffers. The
signal driving the output buffers and the value of the output pin are normally the same.
Either the Port C data register is driving these pins or one of the serial port transmit lines is
driving the pin. The bits set in the PCFR Parallel Port C Function Register identify
whether the data register or the serial port transmit lines were driving the pins.

Parallel Port C shares its pins with serial ports A-D. The parallel port inputs can be config-
ured as serial port inputs while the dedicated outputs as serial port outputs.

When serving as serial inputs, the data lines can still be read from the Parallel Port C data
register. The parallel port outputs can be selected to be serial port outputs by setting the
corresponding bit positions in the Port C Function register (PCFR). When a parallel port
output pin is selected to be a serial port output, the value stored in the data register is
ignored.

On reset the active (even-numbered) function register bits are zeroed resulting in Port C to
behave as an I/O port. Bit 6 of the Port C data register is zeroed while the remaining even
numbered bits are set to 1.

Table 9-5. Parallel Port C Registers

Register Name

Mnemonic

I/O address

R/W

Reset

Port C Data Register

PCDR

0x50

R/W

x0x1x1x1

Port C Function Register

PCFR

0x55

x0x0x0x0

Table 9-6. Parallel Port C Register Bit Functions

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PCDR (r)

adr = 0x050

PC7 in

Echo
drive

PC5 in

Echo
drive

PC3 in

Echo
drive

PC1 in

Echo
drive

PCDR (w)

adr = 0x050

PC6

PC4

PC2

PC0

PCFR (w)

adr = 0x055

Drive
TXA

Drive
TXB

Drive

TXC

Drive
TXD

Chapter 9 Parallel Ports

133

9.4 Parallel Port D

Parallel Port D, shown in Figure 9-1, has eight pins that can be programmed individually
to be inputs or outputs. When programmed as outputs, the pins can be individually
selected to be open-drain outputs or standard outputs. Port D pins can be addressed by bit
if desired. The output registers are cascaded and timer-controlled, making it possible to
generate precise timing pulses. Port D bits 4 and 5 can be used as alternate bits for Serial
Port B, and bits 6 and 7 can be used as alternate bits for Serial Port A. Alternate serial port
bit assignments make it possible for the same serial port to connect to different communi-
cations lines that are not operating at the same time.

On reset, the data direction register is zeroed, making all pins inputs. In addition certain
bits in the control register are zeroed (bits 0,1,4,5) to ensure that data is clocked into the
output registers when loaded. All other registers associated with port D are not initialized
on reset.

Table 9-7. Parallel Port D Registers

Register Name

Mnemonic

I/O address

R/W

Reset

Port D Data Register

PDDR

0x60

R/W

xxxxxxxx

Port D Control Register

PDCR

0x64

xx00xx00

Port D Function Register

PDFR

0x65

xxxxxxxx

Port D Drive Control Register

PDDCR

0x66

xxxxxxxx

Port D Data Direction Register

PDDDR

0x67

00000000

Port D Bit 0 Register

PDB0R

0x68

xxxxxxxx

Port D Bit 1 Register

PDB1R

0x69

xxxxxxxx

Port D Bit 2 Register

PDB2R

0x6A

xxxxxxxx

Port D Bit 3 Register

PDB3R

0x6B

xxxxxxxx

Port D Bit 4 Register

PDB4R

0x6C

xxxxxxxx

Port D Bit 5 Register

PDB5R

0x6D

xxxxxxxx

Port D Bit 6 Register

PDB6R

0x6E

xxxxxxxx

Port D Bit 7 Register

PDB7R

0x6F

xxxxxxxx

Chapter 9 Parallel Ports

135

Table 9-8. Parallel Port D Register functions

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PDDR (R/W)
adr = 0x060

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PDDCR (W)
adr = 0x066

out =
open
drain

PDFR (W)
adr = 0x065

alt TXA

alt TXB

PDDDR (W)
adr = 0x067

dir =
out

PDB0R (W)

adr = 0x068

PD0

PDB1R (W)

adr = 0x069

PD1

PDB2R (W)

adr =0x 06A

PD2

PDB3R (W)

adr = 0x06B

PD3

PDB4R (W)

adr = 0x06C

PD4

PDB5R (W)

adr = 0x06D

PD5

PDB6R (W)

adr = 0x06E

PD6

PDB7R (W)

adr = 0x06F

PD7

Table 9-9. Parallel Port D Control Register (adr = 0x064)

Bits 7, 6

Bits 5, 4

Bits 3, 2

Bits 1, 0

x,x

00—clock upper nibble on pclk/2

01—clock on timer A1

10—clock on timer B1

11—clock on timer B2

x,x

00—clock lower nibble on pclk/2

01—clock on timer A1

10—clock on timer B1

11—clock on timer B2

Chapter 9 Parallel Ports

137

9.5 Parallel Port E

Parallel Port E, shown in Figure 9-2, has eight I/O pins that can be individually pro-
grammed as inputs or outputs. PE7 is used as the slave port chip select when the slave port
is enabled. Each of the port E outputs can be configured as an I/O strobe. In addition, four
of the port E lines can be used as interrupt request inputs. The output registers are cas-
caded and timer-controlled, making it possible to generate precise timing pulses.

Figure 9-2. Parallel Port E Block Diagram

PE7

PE4

I/O Data

perclk/2

Timer A1

Timer B1

Timer B2

perclk/2

Timer A1

Timer B1

Timer B2

PE3

PE0

/SCS

Inputs

INT1

INT0

INT1

INT0

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The following registers are described in Table 9-11 and in Table 9-12.

•

PEDR—Port E data register. Reads value at pins. Writes to port E preload register.

•

PEDDR—Port E data direction register. Set to "1" to make corresponding pin an out-
put. This register is zeroed on reset.

•

PEFR—Port E function register. Set bit to "1" to make corresponding output an I/O
strobe. The nature of the I/O strobe is controlled by the I/O bank control registers
(IBxCR). The data direction must be set to output for the I/O strobe to work.

•

PEBxR—These are individual registers to set individual output bits on or off.

•

PECR—Parallel Port E control register. This register is used to control the clocking of
the upper and lower nibble of the final output register of the port. On reset, bits 0, 1, 4,
and 5 are reset to zero.

On reset, the data direction register and function register are zeroed, making all pins
inputs, and disabling the alternate output functions. In addition certain bits in the control
register are zeroed (bits 0,1,4,5) to ensure that data is clocked into the output registers
when loaded. All other registers associated with Port E are not initialized on reset.

Table 9-10. Parallel Port E Registers

Register Name

Mnemonic

I/O address

R/W

Reset

Port E Data Register

PEDR

0x70

R/W

xxxxxxxx

Port E Control Register

PECR

0x74

xx00xx00

Port E Function Register

PEFR

0x75

00000000

Port E Data Direction Register

PEDDR

0x77

00000000

Port E Bit 0 Register

PEB0R

0x78

xxxxxxxx

Port E Bit 1 Register

PEB1R

0x79

xxxxxxxx

Port E Bit 2 Register

PEB2R

0x7A

xxxxxxxx

Port E Bit 3 Register

PEB3R

0x7B

xxxxxxxx

Port E Bit 4 Register

PEB4R

0x7C

xxxxxxxx

Port E Bit 5 Register

PEB5R

0x7D

xxxxxxxx

Port E Bit 6 Register

PEB6R

0x7E

xxxxxxxx

Port E Bit 7 Register

PEB7R

0x7F

xxxxxxxx

Chapter 9 Parallel Ports

139

Table 9-11. Parallel Port E Register functions

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PEDR (R/W)

adr = 0x070

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

PEFR (W)

adr = 0x075

alt /I7

alt /I6

alt /I5

alt /I4

alt /I3

alt /I2

alt /I1

alt /I0

PEDDR (W)
adr = 0x077

dir =
out

PEB0R (W)

adr = 0x078

PE0

PEB1R (W)

adr = 0x079

PE1

PEB2R (W)

adr = 0x07A

PE2

PEB3R (W)

adr = 0x07B

PE3

PEB4R (W)

adr = 0x07C

PE4

PEB5R (W)

adr = 0x07D

PE5

PEB6R (W)

adr = 0x07E

PE6

PEB7R (W)

adr = 0x07F

PE7

Table 9-12. Parallel Port E Control Register (adr = 0x074)

Bits 7, 6

Bits 5, 4

Bits 3, 2

Bits 1, 0

x,x

00—clock upper nibble on pclk/2

01—clock on timer A1

10—clock on timer B1

11—clock on timer B2

x,x

00—clock lower nibble on pclk/2

01—clock on timer A1

10—clock on timer B1

11—clock on timer B2

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9.6 Parallel Port F

Parallel Port F is a byte-wide port with each bit programmable for data direction and drive.
These are simple inputs and outputs controlled and reported in the Port F Data Register.
As outputs, the bits of the port are buffered, with the data written to the Port F Data Regis-
ter transferred to the output pins on a selected timing edge. The outputs of Timer A1,
Timer B1, or Timer B2 can be used for this function, with each nibble of the port having a
separate select field to control this timing.

These inputs and outputs are also used for access to other peripherals on the chip. As out-
puts, the Parallel Port F outputs can carry the four Pulse-Width Modulator outputs. As
inputs, Parallel Port F inputs can carry the inputs to the quadrature decoders. When Serial
Port C or Serial Port D is used in the clocked serial mode, two pins of Parallel Port F are
used to carry the serial clock signals. When the internal clock is selected in these serial
ports, the corresponding bit of Parallel Port F is set as an output.

The Parallel Port F registers and their functions are described in Table 9-14 and in Table 9-15.

Table 9-13. Parallel Port F Registers

Register Name

Mnemonic

I/O address

R/W

Reset

Port F Data Register

PFDR

0x38

R/W

xxxxxxxx

Port F Control Register

PFCR

0x3C

xx00xx00

Port F Function Register

PFFR

0x3D

xxxxxxxx

Port F Drive Control Register

PFDCR

0x3E

xxxxxxxx

Port F Data Direction Register

PFDDR

0x3F

00000000

Table 9-14. Parallel Port F Register Functions

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PFDR (R/W)
adr = 0x038

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

PFFR (W)
adr = 0x03D

pwm[3]

pwm[2]

pwm[1]

pwm[0]

sclk_c

sclk_d

PFDCR (W)
adr = 0x03E

out =
open
drain

PFDDR (W)
adr = 0x03F

dir =
out

Chapter 9 Parallel Ports

141

The following registers are described in Table 9-14 and in T able 9-15.

•

PFDR—Port F data register. Reads value at pins. Writes to port F preload register.

•

PFCR—Parallel Port F control register. This register is used to control the clocking of
the upper and lower nibble of the final output register of the port. On reset, bits 0, 1, 4,
and 5 are reset to zero.

•

PFFR—Port F function register. Set bit to "1" to enable alternate output function. Bits
7-4 enable the PWM outputs and bits 1-0 enable synchronous serial ports C and D
clock outputs for when the serial port is configured for internal clock generation.

•

PFDCR—Parallel Port F drive control register. A "0" makes the corresponding pin a
regular output. A "1" makes the corresponding pin an open-drain output. Write only.

•

PFDDR—Port F data direction register. Set to "1" to make corresponding pin an output.
This register is zeroed on reset.

On reset, the data direction register is zeroed, making all pins inputs. In addition certain bits
in the control register are zeroed (bits 0,1,4,5) to ensure that data is clocked into the output
registers when loaded. All other registers associated with port F are not initialized on reset.

9.6.1 Using Parallel Port A and Parallel Port F

A bug has been discovered in the Rabbit 3000 that results in a conflict between Parallel
Port F and Parallel Port A under certain conditions. This bug has been corrected in ver-
sions of the Rabbit chip designated 3000A and later. See Appendix B for further details.

The bug is rooted in an incomplete address decode for the data output register for Parallel
Port A. This register responds to any of 16 addresses 30 to 3F (hex). When Parallel Port F
was added, the addresses 38 to 3F were used, and the decode for Parallel Port A was not
updated.

There are five registers in Parallel Port F at addresses in the range of 38 to 3F. Writing to
any of these registers will also cause a write to the Parallel Port A output register, which is
identical to the slave port number zero output register. If Parallel Port A is used as in input
register or if the auxiliary I/O bus (which uses the pins of Parallel Port A as a data bus) is
enabled, then the spurious write has no effect on operation because the Parallel Port A out-
put register is not used. However if Parallel Port A is used as an output or is used as the
bidirectional bus of the slave port, then writing to any of the Parallel Port F registers will
cause a spurious write to the Parallel Port A register, which will have a spurious effect on
the operation of the Rabbit 3000 chip.

Table 9-15. Parallel Port F Control Register (adr = 0x03C)

Bits 7, 6

Bits 5, 4

Bits 3, 2

Bits 1, 0

x,x

00—clock upper nibble on pclk/2

01—clock on timer A1

10—clock on timer B1

11—clock on timer B2

x,x

00—clock lower nibble on pclk/2

01—clock on timer A1

10—clock on timer B1

11—clock on timer B2

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The functionality of the Parallel Port F pins is not affected for pulse width modulation out-
puts and serial clock outputs, except that the Parallel Port F function and direction regis-
ters should be set up before a conflicting function on Parallel Port A is in use, since
writing to these registers also writes to the Parallel Port A output register.

9.6.1.1 Summary

•

If you enable the auxiliary I/O bus, which uses Parallel Port A, then the bug does not
manifest itself and you can use the full functionality of Parallel Port F.

•

If you use Parallel Port A as inputs, then the bug does not manifest itself and the full
functionality of Parallel Port F is available.

•

If you use Parallel Port A as outputs, then you cannot use Parallel Port F pins as outputs
too, except that you can use the PWM and clock outputs provided that you are aware
that writing to the control registers of Parallel Port F will also write to the data output
register of Parallel Port A. A simple way to resolve this is to leave Parallel Port A as an
input until you complete the setup of Parallel Port F and then switch Parallel Port A to
be an output. You can always use pins on Parallel Port F as inputs.

•

If you enable the slave port, then you cannot use Parallel Port F as parallel outputs, but
you can still use the other output functions of Parallel Port F following the precautions
regarding setup described above.

The easiest approach to avoid any problem when there is a conflict is to assign inputs and
outputs in such a manner as to avoid the bug. Either Parallel Port A can be used as inputs,
in which case Parallel Port F has full function, or if Parallel Port A cannot be used as
inputs, use any pins on Parallel Port F not used for PWM or serial clock outputs as inputs
and take the precaution of setting up Parallel Port F before the conflicting functionality of
Parallel Port A is enabled.

Parallel Port A

Parallel Port F

•

Parallel Inputs

•

Full Functionality

•

Parallel Outputs

•

Parallel Inputs, PWM, Serial Port Clocks

•

Slave Port

•

Parallel Inputs, PWM, Serial Port Clocks

•

Auxiliary I/O Bus

•

Full Functionality

Chapter 9 Parallel Ports

143

9.7 Parallel Port G

Parallel Port G is a byte-wide port with each bit programmable for data direction and
drive. These are simple inputs and outputs controlled and reported in the Port G Data Reg-
ister. As outputs, the bits of the port are buffered, with the data written to the Port G Data
Register transferred to the output pins on a selected timing edge. The outputs of Timer A1,
Timer B1, or Timer B2 can be used for this function, with each nibble of the port having a
separate select field to control this timing.

These inputs and outputs are also used for access to other peripherals on the chip. As out-
puts, Port G can carry the data and clock outputs from Serial Ports E and F. As inputs, Port
G can carry the data and clock inputs for these two serial ports.

The following registers are described in Table 9-17 and in T able 9-18.

Table 9-16. Parallel Port G Registers

Register Name

Mnemonic

I/O address

R/W

Reset

Port G Data Register

PGDR

0x48

R/W

xxxxxxxx

Port G Control Register

PGCR

0x4C

xx00xx00

Port G Function Register

PGFR

0x4D

xxxxxxxx

Port G Drive Control Register

PGDCR

0x4E

xxxxxxxx

Port G Data Direction Register

PGDDR

0x4F

00000000

Table 9-17. Parallel Port G Data Register Functions

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PGDR (R/W)
adr = 0x048

PG7

PG6

PG5

PG4

PG3

PG2

PG1

PG0

PGFR (W)
adr = 0x04D

SOUT_E

RCLK_E

TCLK_E

SOUT_F

RCLK_F

TCLK_F

PGDCR (W)
adr = 0x04E

out =
open
drain

PGDDR (W)
adr = 0x04F

dir =
out

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The following registers are described in Table 9-17 and in T able 9-18.

•

PGDR—Port G data register. Reads value at pins. Writes to port G preload register.

•

PGCR—Parallel Port G control register. This register is used to control the clocking of
the upper and lower nibble of the final output register of the port. On reset, bits 0, 1, 4,
and 5 are reset to zero.

•

PGFR—Port G function register. Set bit to "1" to enable alternate output function. Bits
6 and 2 enable the asycnhronous or SDLC/HDLC serial ports E and F outputs. And
bits 5-4 and 1-0 enable the SDLC/HDLC transmit and receive clock outputs for serial
ports E and F.

•

PGDCR—Parallel Port G drive control register. A "0" makes the corresponding pin a
regular output. A "1" makes the corresponding pin an open-drain output. Write only.

•

PGDDR—Port G data direction register. Set to "1" to make corresponding pin an out-
put. This register is zeroed on reset.

Table 9-18. Parallel Port G Control Register (adr= 0x04C)

Bits 7, 6

Bits 5, 4

Bits 3, 2

Bits 1, 0

x,x

00—clock upper nibble on pclk/2

01—clock on timer A1

10—clock on timer B1

11—clock on timer B2

x,x

00—clock lower nibble on pclk/2

01—clock on timer A1

10—clock on timer B1

11—clock on timer B2

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Table 10-1 shows how the eight I/O bank control registers are organized.

Table 10-1. I/O Bank x Control Register

I/O Bank x Control Register

(IB0CR)

(Address = 0x0080)

(IB1CR)

(Address = 0x0081)

(IB2CR)

(Address = 0x0082)

(IB3CR)

(Address = 0x0083)

(IB4CR)

(Address = 0x0084)

(IB5CR)

(Address = 0x0085)

(IB6CR)

(Address = 0x0086)

(IB7CR)

(Address = 0x0087)

Bit(s)

Value

Description

7:6

Fifteen wait states for accesses in this bank.

Seven wait states for accesses in this bank.

Three wait states for accesses in this bank.

One wait state for accesses in this bank.

5:4

The Ix signal is an I/O chip select.

The Ix signal is an I/O read strobe.

The Ix signal is an I/O write strobe.

The Ix signal is an I/O data (read or write) strobe.

Writes are not allowed to this bank. Transactions are normal in every other way;
only the write strobe is inhibited.

Writes are allowed to this bank.

* Bit 2 is ignored in versions of the Rabbit 3000 before the Rabbit 3000A.

I/O strobe (Ix) is active low.

I/O strobe (Ix) is active high.

1:0

These bits are ignored.

Chapter 10 I/O Bank Control Registers

147

The eight I/O bank control registers determine the number of I/O wait states applied to an
external I/O access within the zone controlled by each register even if the associated
strobes are not enabled. Note that the /IORD and /IOWR signals reflect these registers as
well.

The control over the generation of wait states is independent of whether or not the associ-
ated strobe in Port E is enabled. The upper 2 bits of each register determine the number of
wait states. The four choices are 1, 3, 7, or 15 wait states. On reset, the bits are cleared,
resulting in 15 wait states. There is always at least one external I/O wait state, and thus the
minimum external I/O read cycle is three clocks long. The inhibit write function applies to
both the Port E write strobes and the /IOWR signal.

These control bits have no effect on the internal I/O space, which does not have wait states
associated with read or write access. Internal I/O read or write cycles are two clocks long.

The I/O strobes greatly simplify the interfacing of external devices. On reset, the upper 5
bits of each register are cleared. Parallel Port E will not output these signals unless the
data-direction register bits are set for the desired output positions. In addition, the Port E
function register must be set to "1" for each position.

Each I/O bank is selected by the three most significant bits of the 16-bit I/O address.
Table 10-2 shows the relationship between the I/O control register and its corresponding
space in the 64K address space.

Table 10-2. External I/O Register Address Range and Pin Mapping

Control Register

Port E

Pin

I/O Address

A[15:13]

I/O Address

Range

IB0CR

PE0

000

0x0000–0x1FFF

IB1CR

PE1

001

0x2000–0x3FFF

IB2CR

PE2

010

0x4000–0x5FFF

IB3CR

PE3

011

0x6000–0x7FFF

IB4CR

PE4

100

0x8000–0x9FFF

IB5CR

PE5

101

0xA000–0xBFFF

IB6CR

PE6

110

0xC000–0xDFFF

IB7CR

PE7

111

0xE000–0xFFFF

Chapter 11 Timers

149

11. T

IMERS

There are two timers—Timer A and Timer B. Timer A is intended mainly for generating
the clock for various peripherals, baud clock for the serial ports, a periodic clock for
clocking Parallel Ports D and E, or for generating periodic interrupts. Timers A1–A7 are
general-purpose timers, and Timers A8–A10 are dedicated to specific peripherals. Timer
B can be used for the same functions, but it cannot generate the baud clock. Timer B is
more flexible when it can be used because the program can read the time from a continu-
ously running counter and events can be programmed to occur at a specified future time.

Figure 11-1. Block Diagram of Timers A and B

perclk/2

Timer A System

match reg

compare

Timer B System

match preload

10 bits

Timer_B1

Timer_B2

perclk

10-bit counter

Serial E

Serial F

Serial A

Serial B

Serial C

Serial D

Input
Capture

PWM

Quadrature
Decode

A10

Timer A1

perclk/2

Control Timer
Synchronized
outputs

perclk/16

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Rabbit 3000 Microprocessor User’s Manual

11.1 Timer A

Timer A consists of ten separate countdown timers A1–A10 as shown in Figure 11-1.

Timers A1 and A2–A10 are 8-bit countdown registers as shown in Figure 11-2. The reload
register can contain any number in the range from 0 to 255. The counter divides by (n+1).
For example, if the reload register contains 127, then 128 pulses enter on the left before a
pulse exits on the right. If the reload register contains zero, then each pulse on the left
results in a pulse on the right, that is, there is division by one.

Figure 11-2. Reload Register Operation

The timer systems can be driven by the peripheral clock, or peripheral clock divided by
two. This clock is always the same as the processor clock, or it is faster than the processor
clock by a factor of eight. The output pulses are always one clock long. Clocking of the
counters takes place on the negative edge of this pulse. When the counter reaches zero, the
reload register is loaded on the next input pulse instead of a count being performed. The
reload registers may be reloaded at any time since the peripheral clock is synchronous
with the processor clock.

Timers A2, A3, A4, A5, A6 and A7 always provide the baud clock for Serial Ports E, F, A,
B, C, and D respectively. Except for very low baud rates, clock A1 does not need to be
used to prescale the input clock for timers A2–A7. For example, if the system clock is
11.0592 MHz, and the timer A4 divides by 144, an asynchronous baud rate of 2400 bps can
be achieved in one step (assuming that the timer is clocked by peripheral clock divided by
two). The clock input to the serial port can be 8 or 16 times the baud rate for asynchronous
mode and 8 times the baud rate for synchronous mode. The maximum asynchronous baud
rate with a 11.0592 MHz clock would be (11,059,200/(1*8) = 1,382,400.

8-bit down counter

8-bit reload register

Clock in

pulse on zero count out

load

Input clock
Count value

N - 1

Output pulse

Chapter 11 Timers

151

For seven of the counters (A1–A7), the terminal count condition is reported in a status regis-
ter and can be programmed to generate an interrupt. There is one interrupt vector for Timer
A and a common interrupt priority. A common status register (TACSR) has a bit for each
timer that indicates if the output pulse for that timer has taken place since the last read of the
status register. When the status register is read, these bits are cleared. No bit will be lost.
Either it will be read by the status register read or it will be set after the status register read is
complete. If a bit is on and the corresponding interrupt is enabled, an interrupt will occur
when priorities allow. However, a separate interrupt is not guaranteed for each bit with an
enabled interrupt. If the bit is read in the status register, it is cleared and no further interrupt
corresponding to that bit will be requested. It is possible that one bit will cause an interrupt,
and then one or more additional bits will be set before the status register is read. After these
bits are cleared, they cannot cause an interrupt. If any bits are on, and the corresponding
interrupt is enabled, then the interrupt will take place as soon as priorities allow. However, if
the bit is cleared before the interrupt is latched, the bit will not cause an interrupt. The proper
rule to follow is for the interrupt routine to handle all bits that it sees set.

Although timers A8–A10 are part of Timer A, they are dedicated to the input pulse cap-
ture, PWM, and quadrature decoder peripherals respectively. The peripherals clocked by
these timers can generate interrupts but the timers themselves cannot. Furthermore, these
timers cannot be cascaded with Timer A1.

11.1.1 Timer A I/O Registers

The I/O registers for Timer A are listed in Table 11-1.

Table 11-1. Timer A I/O Registers

Register Name

Mnemonic

I/O address

R/W

Reset

Timer A Control/Status Register

TACSR

0xA0

R/W

00000000

Timer A Prescale Register

TAPR

0xA1

xxxxxxx1

Timer A Time Constant 1 Register

TAT1R

0xA3

xxxxxxxx

Timer A Control Register

TACR

0xA4

00000000

Timer A Time Constant 2 Register

TAT2R

0xA5

xxxxxxxx

Timer A Time Constant 8 Register

TAT8R

0xA6

xxxxxxxx

Timer A Time Constant 3 Register

TAT3R

0xA7

xxxxxxxx

Timer A Time Constant 9 Register

TAT9R

0xA8

xxxxxxxx

Timer A Time Constant 4 Register

TAT4R

0xA9

xxxxxxxx

Timer A Time Constant 10 Register

TAT10R

0xAA

xxxxxxxx

Timer A Time Constant 5 Register

TAT5R

0xAB

xxxxxxxx

Timer A Time Constant 6 Register

TAT6R

0xAD

xxxxxxxx

Timer A Time Constant 7 Register

TAT7R

0xAF

xxxxxxxx

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Rabbit 3000 Microprocessor User’s Manual

The following table summarizes Timer A’s capabilities.

The control/status register for Timer A (TACSR) is laid out as shown in Table 11-3.

Table 11-2. Timer A Capabilities

Timer

Cascade

Interrupt

Dedicated Connection

none

yes

Parallel Ports D-G, Timer B

from A1

yes

Serial Port E

from A1

yes

Serial Port F

from A1

yes

Serial Port A

from A1

yes

Serial Port B

from A1

yes

Serial Port C

from A1

yes

Serial Port D

none

Input Capture

none

Pulse Width Modulator

A10

none

Quadrature Decoder

Table 11-3. Timer A Control and Status Register

Timer A Control and Status Register

(TACSR)

(Address = 0x00A0)

Bit(s)

Value

Description

(read)

A7 counter has not reached its terminal count.

A7 count done. This status bit is cleared by a read of this register.

(write)

A7 interrupt disabled.

A7 interrupt enabled.

(read)

A6 counter has not reached its terminal count.

A6 count done. This status bit is cleared by a read of this register.

(write)

A6 interrupt disabled.

A6 interrupt enabled.

(read)

A5 counter has not reached its terminal count.

A5 count done. This status bit is cleared by a read of this register.

(write)

A5 interrupt disabled.

A5 interrupt enabled.

(read)

A4 counter has not reached its terminal count.

A4 count done. This status bit is cleared by a read of this register.

Chapter 11 Timers

153

(write)

A4 interrupt disabled.

A4 interrupt enabled.

(read)

A3 counter has not reached its terminal count.

A3 count done. This status bit is cleared by a read of this register.

(write)

A3 interrupt disabled.

A3 interrupt enabled.

(read)

A2 counter has not reached its terminal count.

A2 count done. This status bit is cleared by a read of this register.

(write)

A2 interrupt disabled.

A2 interrupt enabled.

(read)

A1 counter has not reached its terminal count.

A1 count done. This status bit is cleared by a read of this register.

(write)

A1 interrupt disabled.

A1 interrupt enabled.

(write-only)

Disable Timer A main clock (perclk/2).

Enable Timer A main clock (perclk/2).

Table 11-3. Timer A Control and Status Register (continued)

Timer A Control and Status Register

(TACSR)

(Address = 0x00A0)

Bit(s)

Value

Description

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Rabbit 3000 Microprocessor User’s Manual

The control register (TACR) is laid out as shown in Table 11-4.

The Timer A Prescale Register (TAPR) specifies the main clock for Timer A. This will
affect all of the timer A countdown timers. By default Timer A is clocked by peripheral
clock divided by two.

The prescale register (TAPR) is laid out as shown in Table 11-5.

Table 11-4. Timer A Control Register

Timer A Control Register

(TACR)

(Address = 0x00A4)

Bit(s)

Value

Description

Timer A7 clocked by the main Timer A clock.

Timer A7 clocked by the output of Timer A1.

Timer A6 clocked by the main Timer A clock.

Timer A6 clocked by the output of Timer A1.

Timer A5 clocked by the main Timer A clock.

Timer A5 clocked by the output of Timer A1.

Timer A4 clocked by the main Timer A clock.

Timer A4 clocked by the output of Timer A1.

Timer A3 clocked by the main Timer A clock.

Timer A3 clocked by the output of Timer A1.

Timer A2 clocked by the main Timer A clock.

Timer A2 clocked by the output of Timer A1.

1:0

Timer A interrupts are disabled.

Timer A interrupts use Interrupt Priority 1.

Timer A interrupts use Interrupt Priority 2.

Timer A interrupts use Interrupt Priority 3.

Table 11-5. Timer A Prescale Register

Timer A Prescale Register

(TAPR)

(Address = 0x00A1)

Bit(s)

Value

Description

7:1

These bits are ignored.

The main clock for Timer A is the peripheral clock.

The main clock for Timer A is the peripheral clock divided by two.

Chapter 11 Timers

155

The time constant register for each timer (TATxR) is simply an 8-bit data register holding
a number between 0 and 255. This time constant will take effect the next time that the
Timer A counter counts down to zero. The timer counts modulo (divide-by) n+1, where n
is the programmed time constant. The time constant registers are write only. The time
constant registers are listed in Table 11-1.

11.1.2 Practical Use of Timer A

Timer A is disabled (bit 0 in control and status register) on power-up. Timer A is normally
set up while the clock is disabled, but the timer setup can be changed while the timer is
running when there is a need to do so. Timers that are not used should be driven from the
output of A1 and the reload register should be set to 255. This will cause counting to be as
slow as possible and consume minimum power.

As for general-purpose timers, Timer A has seven separate subtimer units, A1 and A2–A7,
that are also referred to as timers.

Most likely, if a serial port is going to be used and a timer is needed to provide the baud clock,
that timer will be set up to be driven directly from the clock, and the interrupt associated with
that timer will be disabled. (Serial port interrupts are generated by the serial port logic.)

The value in the reload register can be changed while the timer is running to change the period
of the next timer cycle. When the reload register is initialized, the contents of the count-
down counter may be unknown, for example, during power-up initialization. If interrupts
are enabled, then the first interrupt may take place at an unknown time. Similarly, if the timer
output is being used to drive the clock for a parallel port or serial port, the first clock may
come at a random time. If a periodic clock is desired, it is probably not important when the
first clock takes place unless a phase relationship is desired relative to a different timers.

A phase relationship between two timers can be obtained in several ways. One way is to
set both reload registers to zero and to wait long enough for both timers to reload (maxi-
mum 256 clocks). Then both timers’ reload registers can be set to new values before or
after both are clocked.

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11.2 Timer B

Figure 11-1 shows a block diagram of Timer B. The Timer B counter can be driven
directly by perclk/2, by that clock divided by 8, or by the output of Timer A1. Timer B has
a continuously running 10-bit counter. The counter is compared against two match regis-
ters, the B1 match register and the B2 match register. When the counter transitions to a
value equal to a match register, an internal pulse with a length of 1 peripheral clock is gen-
erated. The match pulse can be used to cause interrupts and/or clock the output registers of
Parallel Ports D and E.

The match registers are loaded from the match preload registers that are written to by an
I/O instruction. The data byte in the match preload register is advanced to the next match
register when the match pulse is generated.

Every time a match condition occurs, the processor sets an internal bit that marks the match
value in TBLxR as invalid. Reading TBCSR clears the interrupt condition. TBLxR must be
reloaded to re-enable the interrupt. TBMxR does

not

need to be reloaded every time.

If both match registers need to be changed, the most significant byte needs to be changed
first.

The I/O registers for Timer B are listed in Table 11-6.

Table 11-6. Timer B Registers

Register Name

Mnemonic

I/O

address

R/W

Reset

Timer B Control/Status Register

TBCSR

0xB0

R/W

xxxxx000

Timer B Control Register

TBCR

0xB1

xxxx0000

Timer B MSB 1 Register

TBM1R

0xB2

xxxxxxxx

Timer B LSB 1 Register

TBL1R

0xB3

xxxxxxxx

Timer B MSB 2 Register

TBM2R

0xB4

xxxxxxxx

Timer B LSB 2 Register

TBL2R

0xB5

xxxxxxxx

Timer B Count MSB Register

TBCMR

0xBE

xxxxxxxx

Timer B Count LSB Register

TBCLR

0xBF

xxxxxxxx

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157

The control/status register for Timer B (TBCSR) is laid out as shown in Table 11-7.

The control register for Timer B (TBCR) is laid out as shown in Table 11-8.

Table 11-7. Timer B Control and Status Register

Timer B Control and Status Register

(TBCSR)

(Address = 0x00B0)

Bit(s)

Value

Description

7:3

These bits are always read as zero.

(read)

Timer B2 comparator has not encountered a match condition.

Timer B2 comparator has encountered a match condition. This status bit and the
Timer B2 interrupt (but not interrupt enable) are cleared by a read of this register.

(write)

Timer B2 interrupt disabled.

Timer B2 interrupt enabled.

(read)

Timer B1 comparator has not encountered a match condition.

Timer B1 comparator has encountered a match condition. This status bit and the
Timer B1 interrupt (but not interrupt enable) are cleared by a read of this register.

(write)

Timer B1 interrupt disabled.

Timer B1 interrupt enabled.

Disable the main clock for Timer B.

Enable the main clock for Timer B.

Table 11-8. Timer B Control Register

Timer B Control Register

(TBCR)

(Address = 0x00B1)

Bit(s)

Value

Description

7:4

These bits are reserved and should be written with zeroes.

3:2

Timer B clocked by the main Timer B clock (perclk/2).

Timer B clocked by the output of Timer A1.

Timer B clocked by the main Timer B clock (perclk/2) divided by 8.

1:0

Timer B interrupts are disabled.

Timer B interrupts use Interrupt Priority 1.

Timer B interrupts use Interrupt Priority 2.

Timer B interrupts use Interrupt Priority 3.

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The MSB

registers for Timer B (TBM1R/TBM2R) are laid out as shown in Table 11-9.

The LSB

registers for Timer B (TBL1R/TBL2R) are laid out as shown in Table 11-10.

Table 11-9. Timer B Count MSB x Registers

Timer B Count MSB x Register

(TBM1R)

(Address = 0xB2)

(TBM2R)

(Address = 0xB4)

Bit(s)

Value

Description

7:6

Write

The two MSBs of the comparae value for the Timer B comparator are stored.
This compare value will be loaded into the actual comparator when the current
compare detects a match.

5:0

These bits are always read as zeroes.

Table 11-10. Timer B Count LSB x Registers

Timer B Count LSB x Register

(TBL1R)

(Address = 0xB3)

(TBL2R)

(Address = 0xB5)

Bit(s)

Value

Description

7:0

Write

The eight LSBs of the comparae value for the Timer B comparator are stored.
This compare value will be loaded into the actual comparator when the current
compare detects a match.

Table 11-11. Timer B Count MSB Register

Timer B Count MSB Register

(TBCMR)

(Address = 0xBE)

Bit(s)

Value

Description

7:6

Read

The current value of the two MSBs of the Timer B counter are reported.

5:0

These bits are always read as zeroes.

Table 11-12. Timer B Count LSB Register

Timer B Count LSB Register

(TBCLR)

(Address = 0xBF)

Bit(s)

Value

Description

7:0

Read

The current value of the eight LSBs of the Timer B counter are reported.

Chapter 11 Timers

159

11.2.1 Using Timer B

Normally the prescaler is set to divide perclk/2 by a number that provides a counting rate
appropriate to the problem. For example, if the clock is 22.1184 MHz, then perclk/2 is
11.0592 MHz. A Timer B clock rate of 11.0592 MHz will cause a complete cycle of the
10-bit clock in 92.6 µs.

Normally an interrupt will occur when either of the comparators in Timer B generates a
pulse. The interrupt routine must detect which comparator is responsible for the interrupt
and dispatch the interrupt to a service routine. The service routine sets up the next match
value, which will become the match value after the next interrupt. If the clocked parallel
ports are being used, then a value will normally be loaded into some bits of the parallel
port register. These bits will become the output bits on the next match pulse. (It is neces-
sary to keep a shadow register for the parallel port unless the bit-addressable feature of
Ports D and E is used.)

If you wish to read the time from the Timer B counter, either during an interrupt caused by
the match pulse or in some other interrupt routine asynchronous to the match pulse, you
will have to use a special procedure to read the counter because the upper 2 bits are in a
different register than the lower 8 bits. The following method is suggested.

1. Read the lower 8 bits (read TBCLR register).

2. Read the upper 2 bits (read TBCMR register)

3. Read the lower 8 bits again (read TBCLR register)

4. If bit 7 changed from 1 to 0 between the first and second read of the lower 8 bits, there

has been a carry to the upper 2 bits. In this case, read the upper 2 bits again and decre-
ment those 2 bits to get the correct upper 2 bits. Use the first read of the lower 8 bits.

This procedure assumes that the time between reads can be guaranteed to be less than 256
counts. This can be guaranteed in most systems by disabling the priority 1 interrupts,
which will normally be disabled in any case in an interrupt routine.

It is inadvisable to disable the high-priority interrupts (levels 2 and 3) as that defeats their
purpose.

If speed is critical, the three reads of the registers can be performed without testing for the
carry. The three register values can be saved and the carry test can be performed by a
lower priority analysis routine. Since the upper 2 bits are in the TBCMR register at
address 0x0BE, and the lower 8 bits are in TBCLR at address 0x0BF, both registers can be
read with a single 16-bit I/O instruction. The following sequence illustrates how the regis-
ters could be captured.

; enter from external interrupt on pulse input transition

; 19 clocks latency plus 10 clocks interrupt execution

push af ; 7

push hl

ioi ld a,(TBCLR) ; 11 get lower 8 bits of counter

ioi ld hl,(TBCMR) ; 13 get l=upper, h=lower

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161

12. R

ABBIT

ERIAL

ORTS

The Rabbit 3000 has 6 on-chip serial ports designated A, B, C, D, E, and F. All the ports can per-
form asynchronous serial communications at high baud rates. Ports A-D can operate as clocked
ports. Ports A and B can be switched to alternate pins. Ports E and F support SDLC/HDLC syn-
chronous communications in addition to standard asynchronous communications. Port A has the
special capability of being used to remote boot the microprocessor via asynchronous, synchro-
nous, or IrDA (asynchronous serial).

Table 12-1 lists the synchronous serial port signals.

Table 12-1. Serial Port Signals

Serial Port

Signal Name

Function

Serial Port A

TXA

Serial Transmit Out

RXA

Serial Transmit In

CLKA

Clock for clocked mode (bidirectional)

ATXA

Alternate serial transmit out

ARXA

Alternate serial receive in

Serial Port B

TXB

Serial Transmit Out

RXB

Serial Transmit In

CLKB

Clock for clocked mode (bidirectional)

ATXB

Alternate serial transmit out

ARXB

Alternate serial receive in

Serial Port C

TXC

Serial Transmit Out

RXC

Serial Transmit In

CLKC

Clock for clocked mode (bidirectional)

Serial Port D

TXD

Serial Transmit Out

RXD

Serial Transmit In

CLKD

Clock for clocked mode (bidirectional)

Serial Port E

TXE

Serial Transmit Out

RXE

Serial Transmit In

TCLKE

Optional external transmit clock

RCLKE

Optional external receive clock

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Figure 12-1 shows a block diagram of the serial ports.

Figure 12-1. Block Diagram of Rabbit Serial Ports

Serial Port F

TXF

Serial Transmit Out

RXF

Serial Transmit In

TCLKF

Optional external transmit clock

RCLKF

Optional external receive clock

Table 12-1. Serial Port Signals (continued)

Serial Port

Signal Name

Function

Serial Port A

Timer A4

Serial Port B

Timer A5

TXA

RXA

TXB

RXB

CLKA

CLKB

Input to timers

perclk

/2 or

prescaled (Timer A1)

ATXA

ATXB

Serial Port C

Timer A6

TXC

RXC

CLKC

Serial Port D

Timer A7

TXD

RXD

CLKD

Serial Port E

Timer A2

TXE

RXE

RCLKE

TCLKE

Serial Port F

Timer A3

TXF

RXF

RCLKF

TCLKF

ARXB

ARXA

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12.1 Serial Port Register Layout

Figure 12-2 shows a functional block diagram of a serial port. Each serial port has a data
register, a control register and a status register. Writing to the data register starts transmis-
sion. The least significant bit (LSB) is always transmitted first. This is true for both asyn-
chronous and synchronous communication. If the write is performed to an alternate data
register address, the extra address bit or 9th bit (8th bit if 7 data bits) is sent. When data
bits have been received, they are read from the data register (LSB first). The control regis-
ter is used to set the transmit and receive parameters. The status register may be tested to
check on the operation of the serial port.

Figure 12-2. Functional Block Diagram of a Serial Port

Bit 0 1 2 3 4 5 6 7 stop

Rx serial data in

Tx serial data out

Read Data

Write Data

Input Shift Reg

Data In Reg

Data Out Reg

Start Bit

0 1 1 0 1 0 1 1

Transmitting 0x0D6

Stop Bit

Start Bit

Bit 0 1 2 3 4 5 6 7 A stop

0 1 1 0 1 0 1 1

Transmitting 0x0D6

Stop Bit

9th bit

with 9th bit zero

Signals Shown at Microprocessor Tx Pin

fifo ports E, F only

(4 bytes deep)

fifo ports E, F only

(4 bytes deep)

Output Shift Reg

9th bit
zero

9th bit
one

alternate data out
registers

address register

long stop register

LSB First

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12.2 Serial Port Registers

Each serial port has 6 registers shown in the tables below. The status, control and extended
registers may have somewhat different formats for different serial ports.

Table 12-2. Serial Port A Registers

Register Name

Mnemonic

I/O Address

R/W

Reset

Serial Port A Data Register

SADR

0xC0

R/W

xxxxxxxx

Serial Port A Address Register

SAAR

0xC1

xxxxxxxx

Serial Port A Long Stop Register

SALR

0xC2

xxxxxxxx

Serial Port A Status Register

SASR

0xC3

0xx00000

Serial Port A Control Register

SACR

0xC4

xx000000

Serial Port A Extended Register

SAER

0xC5

00000000

Table 12-3. Serial Port B Registers

Register Name

Mnemonic

I/O Address

R/W

Reset

Serial Port B Data Register

SBDR

0xD0

R/W

xxxxxxxx

Serial Port B Address Register

SBAR

0xD1

xxxxxxxx

Serial Port B Long Stop Register

SBLR

0xD2

xxxxxxxx

Serial Port B Status Register

SBSR

0xD3

0xx00000

Serial Port B Control Register

SBCR

0xD4

xx000000

Serial Port B Extended Register

SBER

0xD5

00000000

Table 12-4. Serial Port C Registers

Register Name

Mnemonic

I/O Address

R/W

Reset

Serial Port C Data Register

SCDR

0xE0

R/W

xxxxxxxx

Serial Port C Address Register

SCAR

0xE1

xxxxxxxx

Serial Port C Long Stop Register

SCLR

0xE2

xxxxxxxx

Serial Port C Status Register

SCSR

0xE3

0xx00000

Serial Port C Control Register

SCCR

0xE4

xx000000

Serial Port C Extended Register

SCER

0xE5

00000000

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Table 12-5. Serial Port D Registers

Register Name

Mnemonic

I/O Address

R/W

Reset

Serial Port D Data Register

SDDR

0xF0

R/W

xxxxxxxx

Serial Port D Address Register

SDAR

0xF1

xxxxxxxx

Serial Port D Long Stop Register

SDLR

0xF2

xxxxxxxx

Serial Port D Status Register

SDSR

0xF3

0xx00000

Serial Port D Control Register

SDCR

0xF4

xx000000

Serial Port D Extended Register

SDER

0xF5

00000000

Table 12-6. Serial Port E Registers

Register Name

Mnemonic

I/O Address

R/W

Reset

Serial Port E Data Register

SEDR

0xC8

R/W

xxxxxxxx

Serial Port E Address Register

SEAR

0xC9

xxxxxxxx

Serial Port E Long Stop Register

SELR

0xCA

xxxxxxxx

Serial Port E Status Register

SESR

0xCB

0xx00000

Serial Port E Control Register

SECR

0xCC

xx000000

Serial Port E Extended Register

SEER

0xCD

000x000x

Table 12-7. Serial Port F Registers

Register Name

Mnemonic

I/O Address

R/W

Reset

Serial Port F Data Register

SFDR

0xD8

R/W

xxxxxxxx

Serial Port F Address Register

SFAR

0xD9

xxxxxxxx

Serial Port F Long Stop Register

SFLR

0xDA

xxxxxxxx

Serial Port F Status Register

SFSR

0xDB

0xx00000

Serial Port F Control Register

SFCR

0xDC

xx000000

Serial Port F Extended Register

SFER

0xDD

000x000x

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Table 12-8. Data Register All Ports

Serial Port x Data Register

(SADR)

(Address = 0xC0)

(SBDR)

(Address = 0xD0)

(SCDR)

(Address = 0xE0)

(SDDR)

(Address = 0xF0)

(SEDR)

(Address = 0xC8)

(SFDR)

(Address = 0xD8)

Bit(s)

Value

Description

7:0

Read

Returns the contents of the receive buffer.

Write

Loads the transmit buffer with a data byte for transmission.

Table 12-9. Address Register All Ports

Serial Port x Address Register

(SAAR)

(Address = 0xC1)

(SBAR)

(Address = 0xD1)

(SCAR)

(Address = 0xE1)

(SDAR)

(Address = 0xF1)

(SEAR)

(Address = 0xC9)

(SFAR)

(Address = 0xD9)

Bit(s)

Value

Description

7:0

Read

Returns the contents of the receive buffer. In Clocked Serial mode reading the
data from this register automatically causes the receiver to start a byte receive
operation (the current contents of the receive buffer are read first), eliminating
the need for software to issue the Start Receive command.

Write

Loads the transmit buffer with an address byte, marked with a “zero” address bit,
for transmission. In HDLC mode, the last byte of a frame must be written to this
register to enable subsequent CRC and closing Flag transmission. In Clocked
Serial mode writing the data to this register causes the transmitter to start a byte
transmit operation, eliminating the need for the software to issue the Start
Transmit command.

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Table 12-11. Status Register Asynchronous Mode Only (All Ports)

Serial Port x Status Register

(SASR)

(Address = 0xC3)

(SBSR)

(Address = 0xD3)

(SCSR)

(Address = 0xE3)

(SDSR)

(Address = 0xF3)

(SESR)

(Address = 0xCB)

(SFSR)

(Address = 0xDB)

Bit(s)

Value

Description (Async mode only)

The receive data register is empty—no input character is ready.

There is a byte in the receive buffer. The transition from “0” to “1” sets the
receiver interrupt request flip-flop. The interrupt FF is cleared when the character
is read from the data buffer. The interrupt FF will be immediately set again if
there are more characters available in the FIFO or shift register to be transferred
into the data buffer.

The byte in the receive buffer is data, received with a valid Stop bit.

Address bit or 9th (8th) bit received. This bit is set if the character in the receiver
data register has a 9th (8th) bit. This bit is cleared and should be checked before
reading a data register since a new data value with a new address bit may be
loaded immediately when the data register is read.

The byte in the receive buffer is an address, or a byte with a framing error. If an
address bit is not expected. If the data in the buffer is all zeros, this may be a
Break.

The receive buffer was not overrun.

This bit is set if the receiver is overrun. This happens if the shift register and the data
register are full and a start bit is detected. This bit is cleared when the receiver data
register is read.

This bit is always zero in async mode.

The transmit buffer is empty.

ransmitter data buffer full. This bit is set when the transmit data register is full,

that is, a byte is written to the serial port data register. It is cleared when a byte is
transferred to the transmitter shift register or FIFO, or a write operation is
performed to the serial port status register. This bit will request an interrupt on
the transition from 1 to 0 if interrupts are enabled. Transmit interrupts are cleared
when the transmit buffer is written, or any value (which will be ignored) is
written to this register.

The transmitter is idle.

Transmitter busy bit. This bit is set if the transmitter shift register is busy sending
data. It is set on the falling edge of the start bit, which is also the clock edge that
transfers data from the transmitter data register to the transmitter shift register.
The transmitter busy bit is cleared at the end of the stop bit of the character sent.
This bit will cause an interrupt to be latched when it goes from busy to not busy
status after the last character has been sent (there are no more data in the
transmitter data register).

1:0

These bits are always zero in async mode.

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171

Table 12-12. Status Register Clocked Serial (Ports A-D only)

Serial Port x Status Register

(SASR)

(Address = 0xC3)

(SBSR)

(Address = 0xD3)

(SCSR)

(Address = 0xE3)

(SDSR)

(Address = 0xF3)

Bit(s)

Value

Description (Clocked serial mode only)

The receive data register is empty

There is a byte in the receive buffer. The serial port will request an interrupt
while this bit is set. The interrupt is cleared when the receive buffer is empty.

This bit is always zero in clocked serial mode.

The receive buffer was not overrun.

The receive buffer was overrun. This bit is cleared by reading the receive buffer.

This bit is always zero in clocked serial mode.

The transmit buffer is empty.

The transmit buffer is not empty. The serial port will request an interrupt when
the transmitter takes a byte from the transmit buffer. Transmit interrupts are
cleared when the transmit buffer is written, or any value (which will be ignored)
is written to this register.

The transmitter is idle.

The transmitter is sending a byte. An interrupt is generated when the transmitter
clears this bit, which occurs only if the transmitter is ready to start sending
another byte but the transmit buffer is empty.

1:0

These bits are always zero in clocked serial mode.

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Table 12-13. Status Register HDLC Mode (Ports E and F only)

Serial Port x Status Register

(SESR)

(Address = 0xCB)

(SFSR)

(Address = 0xD3)

Bit(s)

Value

Description (HDLC mode only)

The receive data register is empty

There is a byte in the receive buffer. The serial port will request an interrupt
while this bit is set. The interrupt is cleared when the receive buffer is empty.

6,4

The byte in the receive buffer is data.

The byte in the receive buffer was followed by an Abort.

The byte in the receive buffer is the last in the frame, with valid CRC.

The byte in the receive buffer is the last in the frame, with a CRC error.

The receive buffer was not overrun.

The receive buffer was overrun. This bit is cleared by reading the receive buffer.

The transmit buffer is empty.

The transmit buffer is not empty. The serial port will request an interrupt when
the transmitter takes a byte from the transmit buffer, unless the byte is marked as
the last in the frame. Transmit interrupts are cleared when the transmit buffer is
written, or any value (which will be ignored) is written to this register.

2:1

Transmit interrupt due to buffer empty condition.

Transmitter finished sending CRC. An interrupt is generated at the end of CRC
transmission. Data written in response to this interrupt will cause only one Flag
to be transmitted between frames, and no interrupt will be generated by this Flag.

Transmitter finished sending an Abort. An interrupt is generated at the end of an
Abort transmission.

The transmitter finished sending a closing Flag. Data written in response to this
interrupt will cause at least two Flags to be transmitted between frames.

The byte in the receiver buffer is 8 bits.

The byte in the receiver buffer is less than 8 bits.

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173

Table 12-14. Serial Port Control Register Ports A and B

Serial Port x Control Register

(SACR)

(Address = 0xC4)

(SBCR)

(Address = 0xD4)

Bit(s)

Value

Description

7:6

No operation. These bits are ignored in the Async mode.

In clocked serial mode, start a byte receive operation.

In clocked serial mode, start a byte transmit operation.

In clocked serial mode, start a byte transmit operation and a byte receive
operation simultaneously.

5:4

Parallel Port C is used for input.

Parallel Port D is used for input.

Disable the receiver input.

3:2

Async mode with 8 bits per character.

Async mode with 7 bits per character. In this mode the most significant bit of a
byte is ignored for transmit, and is always zero in receive data.

Clocked serial mode with external clock.

Serial Port A clock is on Parallel Port PB1

Serial Port B clock is on Parallel Port PB0

Clocked serial mode with internal clock.

Serial Port A clock is on Parallel Port PB1

Serial Port B clock is on Parallel Port PB0

1:0

The Serial Port interrupt is disabled.

The Serial Port uses Interrupt Priority 1.

The Serial Port uses Interrupt Priority 2.

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Table 12-15. Serial Port Control Register Ports C and D

Serial Port x Control Register

(SCCR)

(Address = 0xE4)

(SDCR)

(Address = 0xF4)

Bit(s)

Value

Description

7:6

No operation. These bits are ignored in the async mode.

In clocked serial mode, start a byte receive operation.

In clocked serial mode, start a byte transmit operation.

In clocked serial mode, start a byte transmit operation and a byte receive
operation simultaneously.

Enable the receiver input.

Disable the receiver input.

This bit is ignored.

3:2

Async mode with 8 bits per character.

Async mode with 7 bits per character. In this mode the most significant bit of a
byte is ignored for transmit, and is always zero in receive data.

Clocked serial mode with external clock.

Serial Port C clock is on Parallel Port PF1

Serial Port D clock is on Parallel Port PF0

Clocked serial mode with internal clock.

Serial Port C clock is on Parallel Port PF1

Serial Port D clock is on Parallel Port PF0

1:0

The serial port interrupt is disabled.

The serial port uses Interrupt Priority 1.

The serial port uses Interrupt Priority 2.

The serial port uses Interrupt Priority 3.

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Table 12-16. Serial Port Control Register Ports E and F

Serial Port x Control Register

(SECR)

(Address = 0xCC)

(SFCR)

(Address = 0xDC)

Bit(s)

Value

Description

7:6

No operation. These bits are ignored in the Async mode.

In HDLC mode, force receiver in Flag Search mode.

No operation.

In HDLC mode, transmit an Abort pattern.

Enable the receiver input.

Disable the receiver input.

This bit is ignored.

3:2

Async mode with 8 bits per character.

Async mode with 7 bits per character. In this mode the most significant bit of a
byte is ignored for transmit, and is always zero in receive data.

HDLC mode with external clock. The external clocks are supplied as follows:

•

Transmit clock (Serial Port F)—pins PG0 and PG1on Parallel Port G.

•

Receive clock (Serial Port E)—pins PG4 and PG5 on Parallel Port G.

HDLC mode with internal clock. The clock is 16× the data rate, and the DPLL is
used to recover the receive clock. If necessary, the clocks are supplied as follows:

•

Transmit clock (Serial Port F)—pins PG0 and PG1on Parallel Port G.

•

Receive clock (Serial Port E)—pins PG4 and PG5 on Parallel Port G.

1:0

The serial port interrupt is disabled.

The serial port uses Interrupt Priority 1.

The serial port uses Interrupt Priority 2.

The serial port uses Interrupt Priority 3.

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Table 12-17. Extended Register Asynchronous Mode All Ports

Serial Port x Extended Register

(SAER)

(Address = 0xC5)

(SBER)

(Address = 0xD5)

(SCER)

(Address = 0xE5)

(SDER)

(Address = 0xF5)

(SEER)

(Address = 0xCD)

(SFER)

(Address = 0xDD)

Bit(s)

Value

Description (Async mode only)

7:5

xxx

These bits are ignored in async mode.

Normal async data encoding.

Enable RZI coding (3/16ths bit cell IrDA-compliant).

Normal Break operation. This option should be selected when address bits are
expected.

Fast Break termination. At the end of Break a dummy character is written to the
buffer, and the receiver can start character assembly after one bit time.

Async clock is 16X data rate.

Async clock is 8X data rate.

1:0

These bits are ignored in async mode.

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Table 12-18. Extended Register Clocked Serial Mode (Ports A-D only)

Serial Port x Extended Register

(SAER)

(Address = 0xC5)

(SBER)

(Address = 0xD5)

(SCER)

(Address = 0xE5)

(SDER)

(Address = 0xF5)

Bit(s)

Value

Description (Clocked serial mode only)

Normal clocked serial operation.

Timer synchronized clocked serial operation.

Timer-synchronized clocked serial uses Timer B1.

Timer-synchronized clocked serial uses Timer B2.

5:4

Normal clocked serial clock polarity, inactive High. Internal or external clock.

Normal clocked serial clock polarity, inactive Low. Internal clock only.

Inverted clocked serial clock polarity, inactive Low. Internal or external clock.

Inverted clocked serial clock polarity, inactive High. Internal clock only.

3:2

These bits are ignored in clocked serial mode.

No effect on transmitter.

Terminate current clocked serial transmission. No effect on buffer.

No effect on receiver.

Terminate current clocked serial reception.

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Table 12-19. Extended Register HDLC Mode (Ports E and F only)

Serial Port x Extended Register

(SEER)

(Address = 0xCD)

(SFER)

(Address = 0xDD)

Bit(s)

Value

Description (HDLC mode only)

7:5

000

NRZ data encoding for HDLC receiver and transmitter.

010

NRZI data encoding for HDLC receiver and transmitter.

100

Biphase-Level (Manchester) data encoding for HDLC receiver and transmitter.

110

Biphase-Space data encoding for HDLC receiver and transmitter.

111

Biphase-Mark data encoding for HDLC receiver and transmitter.

Normal HDLC data encoding.

Enable RZI coding (1/4th bit cell IRDA-compliant). This mode can only be used
with internal clock and NRZ data encoding.

Idle line condition is Flags.

Idle line condition is all ones.

Transmit Flag on underrun.

Transmit Abort on underrun.

1:0

These bits are ignored in HDLC mode.

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12.3 Serial Port Interrupt

A common interrupt vector is used for the receive and transmit interrupts. There is a sepa-
rate interrupt request flip-flop for the receiver and transmitter. If either of these flip-flops
is set, a serial port interrupt is requested. The flip-flops are set by a rising edge only. The
flip-flops are cleared by a pulse generated by an I/O read or write operation as shown in
Figure 12-3. When an interrupt is requested, it will take place immediately when priorities
allow and an instruction execution is complete. The interrupt is lost if the request flip-flop
is cleared before the interrupt takes place. If the flip-flop is not cleared in the interrupt,
another interrupt will take place when priorities are lowered.

Figure 12-3. Generation of Serial Port Interrupts

The receive interrupt request flip-flop is set after the stop bit is sampled on receive, nomi-
nally one half of the way through the stop bit. Data bits are transferred on this same clock
from the receive shift register to the receive data register.

The transmit interrupt request flip-flop is set on the leading edge of the start bit for data
register empty and at the trailing edge of the stop bit for shift register empty (transmitter
idle). Unless the data register is empty on this trailing edge of the stop bit, the transmitter
does not become idle. The transmitter becomes idle only if the data register is empty at the
trailing edge of the stop bit.

The serial port interrupt vectors are shown in Table 6-1.

Transmitter IRQ

Request Interrupt

Receiver IRQ

Transmitter Data
Buffer Empty or Trans-
mitter not Busy

Receiver Data
Buffer Full

Read Receiver
Data Register

Write Transmitter Data
Register or
Write Status Register

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12.5 Receive Serial Data Timing

When the receiver is ready to receive data, a falling edge indicates that a start bit must be
detected. The falling edge is detected as a different Rx input between two different clocks,
the clock being 8x or 16x the baud rate. Once the start bit has been detected, data bits are
sampled at the middle of each data bit and are shifted into the receive shift register. After
7 or 8 data bits have been received, the next bit will be either a 9th (8th) address bit, or a
stop bit will be sampled. If the Rx line is low, it is an address bit and the address bit
received bit in the status register will be enabled. If an address bit is detected, the receiver
will attempt to sample the stop bit. If the line is high when sampled, it is a stop bit and a
new scan for a new start bit will begin after the sample point. At the same time, the data
bits are transferred into the receive data register and an interrupt, if enabled, is requested.

On receive, an interrupt is requested when the receiver data register has data. This hap-
pens when data bits are transferred from the receive shift register to the data register. This
also sets bit 7 of the status register. The interrupt request and bit 7 are cleared when the
data register is read.

An interrupt is requested if bit 7 is high. The interrupt is requested on the edge of the
transmitter data register becoming empty or the transmitter shift register becoming empty.
The transmitter interrupt is cleared by writing to the status register or to the data register.

On receive, the scan for the next start bit starts immediately after the stop bit is detected.
The stop bit is normally detected at a sample clock that nominally occurs in the center of
the stop bit. If there is a 9th (8th) address bit, the stop bit follows that bit.

The serial clock can be configured to be either 16× the data rate or 8× the data rate.

Figure 12-4. Serial Port Synchronization

Start Bit

8 clocks

Stop Bit

Receiver Data

Ready Bit

Sampling
Point

Serial Port
Input Clock

Asynchronous Receive

Asynchronous Transmit

Transmitter Data Reg Full

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12.6 Clocked Serial Ports

Ports A–D can operate in clocked mode. The data line and clock line are driven as shown in
Figure 12-4. The data and clock are provided as 8-bit bursts with the LSB shifted out and/or
received first. By default the transmit shift register advances on the falling edge of the clock
and the receiver samples the data on the rising edge of the clock. The serial port can generate
the clock or the clock can be provided externally.

The clock polarity is programmable in clocked serial mode according to Figure . The clocked
serial transfer may also be synchronized to the output of either of the match conditions in
Timer B to give precisely timed transfers.

To enable the clocked serial mode, a code must be in bits (3,2) of the control register, enabling
the clocked serial mode with either an internal clock or an external clock. The transition
between the external and the internal clock should be performed with care. Normally a pullup
resistor is needed on the clock line to prevent spurious clocks while neither party is driving the
clock.

Figure 12-5. Clock Polarities Supported in Clocked Serial Mode

In clocked serial mode the shift register and the data register work in the same fashion as for
asynchronous communications. However, to initiate basic sending or receiving, a command
must be issued by writing to bits (7,6) of the control register for each byte sent or received.
One command is for sending a byte, a different command is for receiving a byte, and yet
another command can initiate a transmit and receive at the same time for full duplex commu-
nication. Alternatively, a read or write to the Serial Ports A-D Address registers (SxAR) elim-
inates the need to issue separate receive and transmit commands. In clocked serial mode,
reading the data from the corresponding SxAR register automatically causes the receiver to
start a byte receive operation, eliminating the need for software to issue the Start Receive
command. Any data contained in the receive buffer will be read first before being replaced

CLK (Mode 00)

CLK (Mode 10)

CLK (Mode 01)

CLK (Mode 11)

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with new incoming data. Similarly, writing the data to the SxAR register causes the trans-
mitter to start a byte transmit operation, eliminating the need for the software to issue the
Start Transmit command. The effect of these codes is different, depending on whether the
mode is internal clock or external clock.

To transmit in internal clock mode, the user must first load the data register (which must
be empty) and then store the send code. When the shift register finishes sending the cur-
rent character, if any, the data register will be loaded into the shift register and transmitted
by an 8-clock burst. One character can be in the process of transmitting while another
character is waiting in the data register tagged with the send code. The send code is effec-
tively double-buffered.

To receive a character in internal clock mode, the receive shift register should be idle. The
user then stores the receive code in the control register. A burst of 8 clocks will be gener-
ated and the sender must detect the clocks and shift output data to the data line on the fall-
ing edge of each clock. The receiver will sample the data on the rising edge of each clock
for clock modes 00 and 01 or the falling edge for clock modes 10 and 11. The receive
mode cannot double-buffer characters when using the internal clock. The shift register
must be idle before another character receive can be initiated. However, the interrupt
request and character ready takes place on the rising edge of the last clock pulse. If the
next receive code is stored before the natural location of the next falling edge, another
receive will be initiated without pausing the clock. To do this, the interrupt has to be ser-
viced within 1/2 clock.

To transmit each byte in external clock mode, the user must load the data register and then
store the send code. When the shift register is idle and the receiver provides a clock burst,
the data bits are transferred to the shift register and are shifted out. Once the transfer is
made to the shift register, a new byte can be loaded into the transmit register and a new
send code can be stored.

To receive a byte in external clock mode, the user must set the receive code for the first
byte and then store the receive code for the next byte after each byte is removed from the
data register. Since the receive code must be stored before the transmitter sends the next
byte, the receiver must service the interrupt within 1/2 baud clock to maintain full-speed
transmission. This is usually not practical unless a flow control arrangement is made or
the transmitter inserts gaps between the clock bursts.

In order to carry on high-speed communication, the best arrangement will usually be for
the receiver to provide the clock. When the receiver provides the clock, the transmitter
should always be able to keep up because it is double-buffered and has a full character
time to answer the transmitter data register empty interrupt. The receiver will answer
interrupts that are generated on the last clock rising edge. If the interrupt can be serviced
within 1/2 clock, there will be no pause in the data rate. If it takes the receiver longer to
answer, then there will be a gap between bytes, the length of which depends on the inter-
rupt latency. For example, if the baud rate is 400,000 bps, then up to 50,000 bytes per sec-
ond could be transmitted, or a byte every 20 µs. No data will be lost if the transmitter can

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12.7 Clocked Serial Timing

12.7.1 Clocked Serial Timing With Internal Clock

For synchronous serial communication, the serial clock can be generated either by the
Rabbit or by an external device. The timing diagram in Figure 12-6 below can be applied
to both full-duplex and half-duplex clocked serial communication where the serial clock is
generated internally by the Rabbit. Other SPI-compatible clock modes supported by the
Rabbit 3000 are shown in Figure 12-5. With an internal clock, the maximum serial clock
rate is

perclk

/2.

Figure 12-6. Full-Duplex Clocked Serial Timing Diagram with Internal Clock (Mode 00)

12.7.2 Clocked Serial Timing with External Clock

In a system where the Rabbit serial clock is generated by an external device, the clock sig-
nal has to be synchronized with the internal peripheral clock (

perclk

) before data can be

transmitted or received by the Rabbit. Depending on when the external serial clock is gen-
erated, in relation to

perclk

, it may take anywhere from 2 to 3 clock cycles for the exter-

nal clock to be synchronized with the internal clock before any data can be transferred.
Figure 12-7 shows the timing relationship among

perclk

, the external serial clock, and

data transmit.

Figure 12-7. Synchronous Serial Data Transmit Timing with External Clock (Mode 00)

LSB

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

MSB

LSB

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

MSB

CYCLE

CLKA

TxA

RxA

Rx Capture Strobe

perclk

CLKA

TxA

(ext.)

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12.8 Synchronous Communications on Ports E and F

Serial Port E and F are a dual-function serial ports that can be used in either asynchronous
or HDLC mode. Four bytes of buffering are available for both receiver and transmitter to
reduce interrupt overhead. An interrupt is generated whenever at least one byte is avail-
able in the receiver buffer and every time a byte is removed from the transmitter buffer.

Serial Port E is clocked by the output of Timer A2 and Serial Port F by A3. In asynchro-
nous mode this clock can be either sixteen (the default) or eight times the data rate. In
HDLC mode this clock is sixteen times the data rate. Note that the fastest output from
Timer A2 or A3 is the same frequency as the peripheral clock. Thus the maximum data
rate is the peripheral clock frequency divided by eight in async mode and divided by six-
teen in HDLC mode.

The HDLC receiver employs a Digital Phase-Locked-Loop (DPLL) to generate a synchro-
nized receive clock for the incoming data stream. HDLC mode also allows for an external
1x (same speed as the data rate) clock for both the receiver and the transmitter. HDLC
receive and transmit clocks can be input or output, as appropriate, via the specified pins.
When using an external clock, the maximum data rate is one-sixth of the peripheral clock
rate.

In asynchronous mode the port can send and receive seven or eight bits and has the option
of appending and recognizing an additional address bit. On transmit, the address bit is
automatically appended to the data when this data is written to the address register or long
stop register. Writing to the address register appends an “zero” address bit to the data,
while writing to the long stop register appends an “one” address bit to the data. The
address bit is followed by a normal stop bit. Normal data is written to the data register to
be transmitted. On receive, a status bit distinguishes normal data from “address” data. This
status bit is set to one if a “zero” address bit is received. In non-address bit applications,
this indicates a framing error. This status bit can also indicate a received break, if the
accompanying data is all zeros (this is the definition of break). Asynchronous mode oper-
ates full-duplex. Either the receive data available, transmit buffer empty or transmit idle
conditions can be programmed to generate an interrupt.

The HDLC mode allows full-duplex synchronous communication. Either an internal or
external clock may be selected for both the receiver and the transmitter. HDLC mode
encapsulates data within opening and closing Flags, and sixteen bits of CRC precedes the
closing Flag. All information between the opening and closing Flag is “zero-stuffed”. That
is, if five consecutive ones occur, independent of byte boundaries, a zero is automatically
inserted by the transmitter and automatically deleted by the receiver. This allows a Flag
byte (0x07E) to be unique within the serial bit stream. The standard CRC-CCITT polyno-

mial (x

+ x

+ 1) is implemented, with the generator and checker preset to all ones.

Both receive and transmit operation are essentially automatic. In the receiver, each byte is
marked with status to indicate end-of-frame, short frame and CRC error. The receiver
automatically synchronizes on Flag bytes and presets the CRC checker appropriately. If

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the current receive frame is not needed (because it is addressed to a different station, for
example) a Flag Search command is available. This command forces the receiver to ignore
the incoming data stream until another Flag is received. In the transmitter, the CRC gener-
ator is preset and the opening Flag is transmitted automatically after the first byte is writ-
ten to the transmitter buffer, and CRC and the closing flag are transmitted after the byte
that is written to the buffer through the Address Register. If no CRC is required, writing
the last byte of the frame to the Long Stop Register automatically appends a closing flag
after the last byte. If the transmitter underflows, either an Abort or a Flag will be transmit-
ted, under program control. A command is available to send the Abort pattern (seven con-
secutive ones) if a transmit frame needs to be aborted prematurely. The Abort command
takes effect on the next byte boundary, and causes the transmission of an 0xFE (a zero fol-
lowed by seven ones), after which the transmitter will send the idle line condition. The
Abort command also purges the transmit FIFO. The idle line condition may be either
Flags or all ones.

Both the receiver and transmitter contain four bytes of buffering for the data. Status bits
are buffered along with the data in both receiver and transmitter. The receiver automati-
cally generates an interrupt at the end of a received frame, and the transmitter generates an
interrupt at the end of CRC transmission, at the end of the transmission of an Abort
sequence, and at the end of the transmission of a closing Flag.

The transmitter is not capable of sending an arbitrary number of bits, but only a multiple
of bytes. However, the receiver can receive frames of any bit length. If the last “byte” in
the frame is not eight bits, the receiver sets a status flag that is buffered along with this last
byte. Software can then use the table below to determine the number of valid data bits in
this last “byte.” Note that the receiver transfers all bits between the opening and closing
Flags, except for the inserted zeros, to the receiver data buffer.

Several types of data encoding are available in the HDLC mode. In addition to the normal
NRZ, they are NRZI, Biphase-Level (Manchester), Biphase-Space (FM0) and Biphase-
Mark (FM1). Examples of these encodings are shown in the Figure below. Note that in
NRZI, Biphase-Space and Biphase-Mark the signal level does not convey information.
Rather it is the placement of the transitions that determine the data. In Biphase-Level it is
the polarity of the transition that determines the data.

Last Byte Bit Pattern

Valid Data Hits

bbbbbbb0

bbbbbb01

bbbbb011

bbbb0111

bbb01111

bb011111

b0111111

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189

In HDLC mode the internal clock comes from the output of Timer A2. This timer output is
divided by sixteen to form the transmit clock, and is fed to the Digital Phase-Locked Loop
(DPLL) to form the receive clock. The DPLL is basically just a divide-by-16 counter that
uses the timing of the transitions on the receive data stream to adjust its count. The DPLL
adjust the count so that the output of the DPLL will be properly placed in the bit cells to
sample the receive data. To work properly, then, transitions are required in the receive data
stream. NRZ data encoding does not guarantee transitions in all cases (a long string of
zeros for example), but the other data encodings do. NRZI guarantees transitions because
of the inserted zeros, and the Biphase encodings all have at least one transition per bit cell.

The DPLL counter normally counts by sixteen, but if a transition occurs earlier or later
than expected the count will be modified during the next count cycle. If the transition
occurs earlier than expected, it means that the bit cell boundaries are early with respect to
the DPLL-tracked bit cell boundaries, so the count is shortened, either by one or two
counts. If the transition occurs later than expected, it means that the bit cell boundaries are
late with respect to the DPLL-tracked bit cell boundaries, so the count is lengthened,
either by one or two counts. The decision to adjust by one or by two depends on how far
off the DPLL-tracked bit cell boundaries are. This tracking allows for minor differences in
the transmit and receive clock frequencies.

With NRZ and NRZI data encoding, the DPLL counter runs continuously, and adjusts
after every receive data transition. Since NRZ encoding does not guarantee a minimum
density of transitions, the difference between the sending data rate and the DPLL output

Serial Clock

Biphase-Space

Biphase-Mark

NRZ Data

NRZI

Biphase-Level

NRZI

Biphase-Space

Biphase-Mark

data

"1"

"0"

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Rabbit 3000 Microprocessor User’s Manual

clock rate must be very small, and depends on the longest possible run of zeros in the
received frame. NRZI encoding guarantees at least one transition every six bits (with the
inserted zeros). Since the DPLL can adjust by two counts every bit cell, the maximum dif-
ference between the sending data rate and the DPLL output clock rate is 1/48 (~2%).

With Biphase data encoding (either -Level, -Mark or -Space), the DPLL runs only as long
as transitions are present in the receive data stream. Two consecutive missed transitions
causes the DPLL to halt operation and wait for the next available transition. This mode of
operation is necessary because it is possible for the DPLL to lock onto the optional transi-
tions in the receive data stream. Since they are optional, they will eventually not be
present and the DPLL can attempt to lock onto the required transitions. Since the DPLL
can adjust by one count every bit cell, the maximum difference between the sending data
rate and the DPLL output clock rate is 1/16 (~6%).

With Biphase data encoding the DPLL is designed to work in multiple-access conditions
where there may not be Flags on an idle line. The DPLL will properly generate an output
clock based on the first transition in the leading zero of an opening Flag. Similarly, only the
completion of the closing Flag is necessary for the DPLL to provide the extra two clocks to
the receiver to properly assemble the data. In Biphase-Level mode, this means the transi-
tion that defines the last zero of the closing Flag. In Biphase-Mark and Biphase-Space
modes this means the transition that defines the end of the last zero of the closing Flag.

The figure below shows the adjustment ranges and output clock for the different modes of
operation of the DPLL. Each mode of operation will be described in turn.

Bit cell

Bi-S adj

Bi-M adj

NRZI adj

NRZI Clock

Bi-L Clock

Bi-L adj

Bi-S Clock

Bi-M Clock

none

add one

add two

subtract two

subtract one

none

add one

ignore transitions

subtract one

none

add one

ignore transitions

subtract one

none

add one

ignore transitions

subtract one

ignore transitions

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191

With NRZ and NRZI encoding all transitions occur on bit-cell boundaries and the data
should be sampled in the middle of the bit cell. If a transition occurs after the expected bit-
cell boundary (but before the midpoint) the DPLL needs to lengthen the count to line up
the bit-cell boundaries. This corresponds to the “add one” and “add two” regions shown. If
a transition occurs before the bit cell boundary (but after the midpoint) the DPLL needs to
shorten the count to line up the bit-cell boundaries. This corresponds to the “subtract one”
and “subtract two” regions shown. The DPLL makes no adjustment if the bit-cell bound-
aries are lined up within one count of the divide-by-sixteen counter. The regions that
adjust the count by two allow the DPLL to synchronize faster to the data stream when
starting up.

With Biphase-Level encoding there is a guaranteed “clock” transition at the center of
every bit cell and optional “data” transitions at the bit cell boundaries. The DPLL only
uses the clock transitions to track the bit cell boundaries, by ignoring all transitions occur-
ring outside a window around the center of the bit cell. This window is half a bit-cell wide.
Additionally, because the clock transitions are guaranteed, the DPLL requires that they
always be present. If no transition is found in the window around the center of the bit cell
for two successive bit cells the DPLL is not in lock and immediately enters the search
mode. Search mode assumes that the next transition seen is a clock transition and immedi-
ately synchronizes to this transition. No clock output is provided to the receiver during the
search operation. Decoding Biphase-Level data requires that the data be sampled at either
the quarter or three-quarter point in the bit cell. The DPLL here uses the quarter point to
sample the data.

Biphase-Mark and Biphase space encoding are identical as far as the DPLL is concerned,
and are similar to Biphase-Level. The primary difference is the placement of the clock and
data transitions. With these encodings the clock transitions are at the bit-cell boundary and
the data transitions are at the center of the bit cell, and the DPLL operation is adjusted
accordingly. Decoding Biphase-Mark or Biphase-Space encoding requires that the data be
sampled by both edges of the recovered receive clock.

An optional IRDA (Infrared Data Association) -compliant encode and decode function is
available in both asynchronous mode and HDLC mode. The encoder sends an active-High
pulse for a zero and no pulse for a one. In the asynchronous 16x mode this pulse is 3/16ths
of a bit cell wide, while in the asynchronous 8x mode it is 1/8th of a bit cell wide. In
HDLC mode the pulse is 1/4th of a bit cell wide. In all modes the decoder watches for
active-Low pulses, which are stretched to one bit time wide to recreate the normal asyn-
chronous waveform for the receiver. Enabling the IRDA-compliant encode/decode modi-
fies the transmitter in HDLC mode so that there are always two opening Flags transmitted.

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12.9 Serial Port Software Suggestions

The receiver and transmitter share the same interrupt vector, but it is possible to make the
receive and transmit interrupt service routines (ISRs) separate by dispatching the interrupt
to either of two different routines. This is desirable to make the ISR less complex and to
reduce the interrupt off time. No interrupts will be lost since distinct interrupt flip-flops
exist for receive and transmit. The dispatcher can test the receiver data register full bit to
dispatch. If this bit is on, the interrupt is dispatched for receive, otherwise for transmit.
The receiver receives first consideration because it must be serviced attentively or data
could be lost.

The dispatcher might look as follows.

interrupt:

PUSH AF

; 10

IOI LD A,(SCSR) ; 7 get status register serial port C

JP m,receive

; 7 go service the receive interrupt

; else service transmit interrupt

The individual interrupts would assume that register AF has been saved and the status reg-
ister has been loaded into Register A.

The interrupt service routines can, as a matter of good practice and obtaining optimum
performance, remove the cause of the interrupt and re-enable the interrupts as soon as pos-
sible. This keeps the interrupt latency down and allows the fastest transmission speed on
all serial ports.

All the serial ports will normally generate priority level 1 interrupts. In exceptional circum-
stances, one or more serial ports can be configured to use a higher priority interrupt.
There is an exception to be aware of when a serial port has to operate at an extremely high
speed. At 115,200 bps, the highest speed of a PC serial port, the interrupts must be serviced
in 10 baud times, or 86 µs, in order not to lose the received characters. If all six serial ports
were operating at this receive speed, it would be necessary to service the interrupt in less
than 21.5 µs to assure no lost characters. In addition, the time taken by other interrupts of
equal or higher priority would have to be considered. A receiver service routine might
appear as follows below. The byte at

bufptr

is used to address the buffer where data bits

are stored. It is necessary to save and increment this byte because characters could be han-
dled out of order if two receiver interrupts take place in quick succession.

receive:

PUSH HL ; 10 save HL

PUSH DE ; 10 save DE

LD HL,struct ; 6

LD A,(HL) ; 5 get in-pointer

LD E,A ; 2 save in pointer in E

INC HL ; 2 point to out-pointer

CMP A,(HL) ; 5 see if in-pointer=out-pointer (buffer full)

JR Z,roverrun ; 5 go fix up receiver over run

INC A ; 2 incement the in pointer

AND A,mask ; 4 mask such as 11110000 if 16 buffer locs

DEC HL ; 2

Chapter 12 Rabbit Serial Ports

193

LD (HL),A

; 6 update the in pointer

IOI LD A,(SCDR) ; 11 get data register port C, clears interrupt request

IPRES ; 4 restore the interrupt priority

; 68 clocks to here

; to level before interrupt took place

; more interrupts could now take place,

; but receiver data is in registers

; now handle the rest of the receiver interrupt routine

LD HL,bufbase ; 6

LD D,0 ; 6

ADD HL,DE ; 2 location to store data

LD (HL),A ; 6 put away the data byte

POP DE ; 7

POP HL ; 7

POP AF ; 7

RET ; 8 from interrupt

; 117 clocks to here

This routine gets the interrupts turned on in about 68 clocks or 3.5 µs at a clock speed of
20 MHz. Although two characters may be handled out of order, this will be invisible to a
higher level routine checking the status of the input buffer because all the interrupts will
be completed before the higher level routine can perform a check on the buffer status.

A typical way to organize the buffers is to have an in-pointer and an out-pointer that incre-
ment through the addresses in the data buffer in a circular manner. The interrupt routine
manipulates the in-pointer and the higher level routine manipulates the out-pointer. If the
in-pointer equals the out-pointer, the buffer is considered full. If the out-pointer plus 1
equals the in-pointer, the buffer is empty. All increments are done in a circular fashion,
most easily accomplished by making the buffer a power of two in length, then anding a
mask after the increment. The actual memory address is the pointer plus a buffer base
address.

12.9.1 Controlling an RS-485 Driver and Receiver

RS-485 uses a half-duplex method of communication. One station enables its driver and
sends a message. After the message is complete, the station disables the driver and listens
to the line for a reply. The driver must be enabled before the start bit is sent and not dis-
abled until the stop bit has been sent. The transmitter idle interrupt is normally used to dis-
able the RS-485 driver and possibly enable the receiver.

12.9.2 Transmitting Dummy Characters

It may be desired to operate the serial transmitter without actually sending any data. “Dummy”
characters are transmitted to pass time or to measure time.

The output of the transmitter may be disconnected from the transmitter output pin by manip-
ulating the control registers for Parallel Port C or D, which are used as output pins. For
example, if Serial Port B is to be temporarily disconnected from its output pin, which is bit
4 of Parallel Port C, this can be done as follows.

1. Store a "1" in bit 4 of the parallel port data output register to provide the quiescent state

of the drive line.

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Rabbit 3000 Microprocessor User’s Manual

2. Clear bit 4 of the Parallel Port C function register so that the output no longer comes

from the serial port. Of course, this should not be done until the transmitter is idle.

A similar procedure can be used if the serial port is set up to use alternate output pins on
port D. Only Serial Ports A and B can use alternate outputs on Parallel Port D.

If an RS-485 driver is being used, dummy characters can be transmitted by disabling the
driver after the stop bit has been sent. This is an alternative to the above procedure.

12.9.3 Transmitting and Detecting a Break

A break is created when the output of the transmitter is driven low for an extended period.
If a break is received, it will appear as a series of characters filled with zeros and with the
9th bit detected low. This could only be confused with a legitimate message if a protocol
using the 9th bit was in effect. Break is not usually used as a message in such protocols.

A break can be transmitted by transmitting a byte of zeros at a very slow baud rate.
Another and probably better method is to disconnect the transmitter from the output pin,
and use the parallel port bit to set the line low while sending dummy characters to time out
the break.

The use of break as a signaling device should be avoided because it is slow, erratically sup-
ported by different types of hardware, and usually creates more problems than it solves.

12.9.4 Using A Serial Port to Generate a Periodic Interrupt

A serial port may be used to generate a periodic interrupt by continuously transmitting
characters. Since the Tx output via Parallel Port C or D can be disabled, the transmitted
characters are transmitted to nowhere. Because the character output path is double-buff-
ered, there will be no gaps in the character transmission, and the interrupts will be exactly
periodic. The interrupts can happen every 9, 10 or 11 baud times, depending on whether 7
or 8 bits are transmitted and on whether the 9th (8th) bit is sent.

12.9.5 Extra Stop Bits, Sending Parity, 9th Bit Communication Schemes

Some systems may require two stop bits. In some cases, it may be necessary to send a par-
ity bit. Certain systems, such as some 8051-based multidrop communications systems,
use a 9th data bit to mark the start of a message frame. The Rabbit 3000 can receive parity
or message formats that contain a 9th bit without problem. Transmitting messages with
parity or messages that always contain a 9th bit is also possible. It is quite easy to do so for
byte formats that use only 7 data bits, in which case the 9th bit or parity bit is actually an
8th bit. Sending a 9th low bit is supported by hardware. Sending a 9th bit as a high value
requires a write to the Serial Port A-F Long Stop Register (SxLR) which is the same as
two stop bits.

Chapter 12 Rabbit Serial Ports

195

Figure 12-9 illustrates the standard asynchronous serial output patterns.

Figure 12-9. Asynchronous Serial Output Patterns

12.9.6 Parity, Extra Stop Bits with 7-Data-Bit Characters

If only 7 data bits are being sent, sending an additional parity or signal bit is easily solved
by sending 8 bits and always setting bit 7 (the eighth bit) of the byte to “1” or “0” depend-
ing on what is desired. No special precautions are needed if two stop bits are to be
received. If parity is received with 7 data bits, receive the data as 8 bits, and the parity will
be in the high bit of the byte.

12.9.7 Parity, Extra Stop Bits with 8-Data-Bit Characters

In order to receive parity with 8 data bits, a check is made on each character for a 9th bit
low. The 9th bit, or parity bit, is low if bit 6 of the serial port status register (SxSR) is set to
a “1” after the character is received. If the 9th bit is not a zero, then the serial port treats it
as an extra stop bit. So if the 9th bit low flag is not set, it should be assumed that the parity
bit is a “1.”

Setting the 9th bit high or low can easily be done in the Rabbit 3000. The 9th bit can be
set low by a write to the Serial Port A-F Address Register (SxAR) and the 9th bit can be
set high by a write to the Serial Port A-F Long Stop Register (SxLR).

Start Bit

Data Bits

9th bit low

Stop Bit

Character with 9th bit low

Character w/o 9th bit low

Start Bit

Signal shown at output pin on processor. A “1” is high.

Start Bit

Stop Bit

9th bit high

Character w. 9th bit high

Generated by a Write to SxLR

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12.9.8 Supporting 9th Bit Communication Protocols

This section describes how 9th bit communication protocols work. 9th bit communication
protocols are supported by processors such as the 8051 and the Z180, and by companies
such as Cimentrics Technology. The data bytes have an extra 9th bit appended where a
parity bit would normally be placed. Requests from the network master to one of its slaves
consist of a frame of bytes—the first byte has the 9th bit set to "1" (as the signal is
observed at the Tx pin of the processor) and the following bytes have the 9th bit set to "0."
The first byte is identified as the address byte, which specifies the slave unit where the
message is directed. This enables a slave to find the start of a message, which is the byte
with the 9th bit set, and to determine if the message is directed to it. If the message is
directed to a particular slave, the slave will then read the characters in the rest of the mes-
sage; otherwise the slave will continue to scan for a start of message character containing
its address.

Normally the 9th bit is set to "1" only on the first byte of a request transmitted by the net-
work master. The subsequent bytes and the slave replies have the 9th bit set to zero. Since
the majority of the traffic has a 9th bit set low, it is only necessary to stretch the stop bit for
the first bytes or address bytes. This can be done without sacrificing performance by send-
ing a dummy character (transmitter disconnected) after the address byte.

Some microprocessor serial ports have a “wake up” mode of operation. In this mode, char-
acters without the 9th bit set to "1" are ignored, and no interrupt is generated. When the
start of a frame is detected, an interrupt takes place on that byte. If the byte contains the
address of the slave, then the “wake up” mode is turned off so that the remaining charac-
ters in the frame can be read. This scheme reduces the overhead associated with messages
directed to other slaves, but it does not really help with the worst-case load. In most cases,
the worst-case compute load is the governing factor for embedded systems. In addition, it
is quite easy for the interrupt driver to dismiss characters not directed to the system. For
these reasons, the “wake up” mode was not implemented for the Rabbit.

The 9th bit protocols suffer from a major problem that the IBM-PC uarts can support the
9th bit only by using special drivers.

12.9.9 Rabbit-Only Master/Slave Protocol

If only Rabbit microprocessors are connected, the 9th bit low can be set on the address
byte, and the remaining bytes can be transmitted in the normal 8-bit mode. This is more
efficient than other 9th bit protocols because only the first byte requires 11 baud times; the
remaining bytes are transmitted in 10 baud times.

12.9.10 Data Framing/Modbus

Some protocols, for example, Modbus, depend on a gap in the data frame to detect the
beginning of the next frame. The 9th bit protocol is another way to detect the start of a
data frame.

The Modbus protocol requires that data frames begin with a minimum 3.5-character quiet
time. The receiver uses this 3.5-character gap to detect the start of a frame. In order for

Chapter 13 Rabbit Slave Port

199

13. R

ABBIT

LAVE

ORT

When a Rabbit microprocessor is configured as a slave, Parallel Port A and certain other
data lines are used as communication lines between the

slave

and the

master

. The slave

unit is a Rabbit configured as a slave. The master can be another Rabbit or any other type
of processor. Rabbits configured as slaves can themselves have slaves.

The master and slave communicate with each other via the slave port. The slave port is a
physical device that includes data registers, a data bus and various handshaking lines. The
slave port is a part of the slave Rabbit, but logically it is an independent device that is used
to communicate between the two processors. Figure 13-1 shows a diagram of the slave port.

Figure 13-1. Rabbit Slave Port

CPU

SPD2R

SPD1R

SPD0R

SPSR

8188

/SLAVEATTN

100

SD0SD7
SA1
SA0
/SRD
/SWR
/SCS

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Rabbit 3000 Microprocessor User’s Manual

The slave port lines are shown in Figure 13-1. The function of these lines is described
below.

•

SD0–SD7—These are bidirectional data lines, and are generally connected to the data
bus of the master processor. Multiple slaves can be connected to the data bus. The slave
drives the data lines only when /SCS and /SRD are both pulled low.

•

SA1, SA0—These are address lines used to select one of the four data registers of the
slave interface. Normally these lines are connected to the low-order address lines of the
master. The master always drives these lines which are always inputs to the slave.

•

/SCS—Input. Slave chip select. The slave ignores read or write requests unless the chip
select is low. If a Rabbit is used as a master, this line can be connected to one of the
master’s programmable chip select lines /I0–/I7.

•

/SRD—Input. If /SCS is also low, this line pulled low causes the contents of the register
selected by the address lines to be driven on the data bus. If a Rabbit is used as a master,
this line is normally connected to the global I/O read strobe /IORD.

•

/SWR—Input. If /SCS is also low, this line causes the data bits on the data bus to be
clocked into the register selected by the address lines on the rising edge of /SWR or
/SCS, whichever rises first. If a Rabbit is used as a master, this line is normally con-
nected to the global I/O write strobe /IOWR.

•

/SLAVEATTN—This line is set low (asserted) if the slave writes to the SPD0R register.
This line is set high if the master writes anything to the slave status register. This line is
usually connected to cause the master to be interrupted when it goes low.

The data lines of the slave port are shared with Parallel Port A that uses the same package
pins. The slave port can be enabled, and Parallel Port A be disabled, by storing an appro-
priate code in the slave port control register (SCR). After the processor is reset, all the pins
belonging to the slave interface are configured as parallel-port inputs unless (SMODE1,
SMODE0) are set to (0,1), in which case the slave port is enabled after reset and the slave
starts the cold-boot sequence using the slave port.

The slave port has three data registers for each direction of communication. Three regis-
ters, named SPD0R, SPD1R, and SPD2R, can be written by the master and read by the
slave. Three different registers, also named SPD0R, SPD1R, and SPD2R, can be written
by the slave and read by the master. The same names are used for different registers since
it is usually clear from the context which register is meant. If it is necessary to distinguish
between registers, we will refer to the registers as “SPD0R writable by the slave” or
“SPD0R writable by the master.”

A status register can be read by either the slave or the master. The status register has full/
empty bits for each of the six registers. A data register is considered

full

when it is written

to by whichever side is capable of writing to it. If the same register is then read by either
side it is considered to be

empty

. The flag for that register is thus set to a "1" when the reg-

ister is written to, and the flag is set to a "0" when the register is read.

Chapter 13 Rabbit Slave Port

201

The registers appear to be internal I/O registers to the slave. To the master, at least for a
Rabbit master, the registers appear to be external I/O registers. The figure below shows the
sequence of events when the master reads/writes the slave port registers.

Figure 13-2. Slave Port R/W Sequencing

/SCS

SD[7:0]

/SRD

Slave Port Read Cycle

Slave Port Write Cycle

/SWR

SA1, SA0

Tsu(SCS)

Tsu(SA)

Th(SA)

Th(SCS)

Tw(SRD)

Ten(SRD)

Tdis(SRD)

Ta(SRD)

Tsu(SWR – SRD)

/SCS

SD[7:0]

/SRD

/SWR

SA1, SA0

Tsu(SCS)

Tsu(SA)

Th(SA)

Th(SCS)

Tw(SWR)

Th(SD)

Tsu(SD)

Tsu(SRD – SWR)

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The following table explains the parameters used in Figure 13-2.

The two SPD0R registers have special functionality not shared by the other data registers.
If the master writes to SPD0R, an inbound interrupt flip-flop is set. If slave port interrupts
are enabled, the slave processor will take a slave port interrupt. If the slave writes to the
other SPD0R register, the slave attention line (/SLAVEATTN, pin 100) is asserted (driven
low) by the slave processor. This line can be used to create an interrupt in the master.
Either side that is interrupted can clear the signal that is causing an interrupt request by writ-
ing to the slave port status register. The data bits are ignored, but the flip-flop that is the
source of the interrupt request is cleared. Figure 13-3 shows a logical schematic of this func-
tionality.

Symbol

Parameter

Minimum

(ns)

Maximum

(ns)

Tsu(SCS)

/SCS Setup Time

—

Th(SCS)

/SCS Hold Time

—

Tsu(SA)

SA Setup Time

—

Th(SA)

SA Hold Time

—

Tw(SRD)

/SRD Low Pulse Width

—

Ten(SRD)

/SRD to SD Enable Time

—

Ta(SRD)

/SRD to SD Access Time

—

Tdis(SRD)

/SRD to SD Disable Time

—

Tsu(SRW – SRD) /SWR High to /SRD Low Setup Time

—

Tw(SWR)

/SWR Low Pulse Width

—

Tsu(SD)

SD Setup Time

—

Th(SD)

SD Hold Time

—

Tsu(SRD – SWR) /SRD High to /SWR Low Setup Time

—

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Rabbit 3000 Microprocessor User’s Manual

Figure 13-4 shows a sample connection of two slave Rabbits to a master Rabbit. The master
drives the slave reset line for both slaves and provides the main processor clock from its
own clock. There is no requirement that the master and slave share a clock, but doing so
makes it unnecessary to connect a crystal to the slaves. Each Rabbit in Figure 13-4 has to
have RAM memory. The master must also have flash memory. However, the slaves do not
need nonvolatile memory since the master can cold boot them over the slave port and
download their program. In order for this to happen, the SMODE0 and SMODE1 pins
must be properly configured as shown in Figure 13-4 to begin a cold boot process at the
end of the slave reset.

Figure 13-4. Typical Connection Slave Rabbit to Master Rabbit

13.1 Hardware Design of Slave Port Interconnection

The designer has the option of cold-booting the slave and downloading the program to
RAM on each cold start. Another option is to configure the slave with both RAM and flash
memory. In this case, the slave will only have the program downloaded for maintenance or
upgrades. Usually, the flash would not be written to on every startup because of the lim-
ited number of lifetime writes to flash memory. The slaves’ reset in Figure 13-4 is under
the program control of the master. If the master is reset, the slave will also be reset because
the master’s drive of the reset line will be lost on reset and the pulldown resistor will pull
the slaves’ resets low. This may be undesirable because it forces the slave to crash if the
master crashes and has a watchdog timeout.

Master Rabbit

First Slave Rabbit

D0–D7

SD0–SD7

Second Slave Rabbit

/IORD

/IOWR

A0
A1

/SRD
/SWR
SA0
SA1

/SLAVEATTN

INT0A

/RESET

/SCS

/I7

/XTALB1

CLK

/I6

/SCS

/SLAVEATTN

INT1A

portout

SMODE0

SMODE1

SMODE0
SMODE1

Reset
Pulldown

Chapter 13 Rabbit Slave Port

205

13.2 Slave Port Registers

The slave port registers are listed in Table 13-1. These registers, each of which is actually
two separate registers, one for read and one for write, are accessible to the slave at the I/O
addresses shown in the table and they are accessible to the master at the external address
shown which specifies the value of the slave address (SA0, SA1) input to the slave when
the master reads or writes the registers. The register that can be written by the slave can
only be read by the master and vice versa. If one side were to attempt to read a register at
the same time that the other side attempted to write the register the result of the read could
be scrambled. However, the protocols and handshaking bits used in communication are
normally such that this never happens.

If the user for some reason wants to depart from the suggested protocols and poll a register
while waiting for the other side to write something to the register, the user should be aware
that all the bits might not change at the exact same time when the result changes, and a
transitional value could be read from the register where some bits have changed to the new
value and others have not. To avoid being confused by a transitional value, the user can
read the register twice and make sure both values are the same before accepting the value,
or the user can test only one bit for a change. The transitional value can only exist for one
read of the register, and each bit will have its old value change to the new value at some
point without wavering back and forth. The existence of a transitional value could be very
rare and has the potential to create a bug that happens often enough to be serious, but so
infrequently as to be difficult to diagnose. Thus, the user is cautioned to avoid this situa-
tion.

Table 13-1. Slave Port Registers

Register

Mnemonic

Internal

Address

External

Address

Slave Port Data 0 Register

SPD0R

0x20

Slave Port Data 1 Register

SPD1R

0x21

Slave Port Data 2 Register

SPD2R

0x22

Slave Port Status Register

SPSR

0x23

Slave Port Control Register

SPCR

0x24

N.A.

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Rabbit 3000 Microprocessor User’s Manual

Table 13-2 describes the slave port control register.

The functionality of the bits is as follows:

Bit 7—If set to "0," the cold-boot feature will be enabled. Normally this bit is set to a "1"

after the cold boot is complete. The cold boot for the slave port is enabled automatically if

(SMODE1, SMODE0) lines are set to (0,1) after the reset ends. This features disables the

normal operation of the processor and causes commands to be accepted via the slave port

the master that is managing the cold boot has finished setting up memory and I/O space,

the (SMODE1, SMODE0) pins are changed to code (0,0), which causes execution to start

at address zero. Typically this will start execution of a secondary boot program. At some

point, bit 7 will be set to a "1" so that the SMODEx pins can be used as normal input pins.

Bits 6,5—May be used to read the input pins SMODE, SMODE0.

Bits 3,2—A “10” written to bits 3,2 enables the slave port disabling Parallel Port A and vari-

ous other port lines. Bits 3,2 are automatically set to a "10" if a cold boot is done via the

slave port. If bit 3 is "0," then bit 2 controls whether Parallel Port A is an input (bit 2 = 0)

or an output (bit 2 = 1). A “11” written to bits 3,2 enables the Auxilliary I/O bus.

Bits 1,0—This 2-bit field sets the priority of the slave port interrupt. The interrupt is disabled

by (0,0).

Table 13-2. Slave Port Control Register (SPCR) (adr = 0x024)

Bit 7

(Write Only)

Bits 6,5

(Read Only)

Bit 4

Bit 3,2

(Write Only)

Bits 1,0

(Write Only)

0—obey SMODE
pins

1—ignore SMODE
pins

Reads SMODE
pins
smode1,smode0

00—disable slave port, port A
is a byte wide input port

01—disable slave port, port A
is a byte wide output port

10—enable the slave port

11—Enable the auxilliary I/O
bus. Parallel Port A is used
for the data bus and Parallel
Port B[7:2] is used for the
address bus.

00—no slave
interrupt

pp—enable slave
port interrupt

01 priority 1

10 priority 2

11 priority 3

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Rabbit 3000 Microprocessor User’s Manual

13.3 Applications and Communications Protocols for Slaves

The communications protocol used with the slave port depends on the application. A slave
processor may be used for various reasons. Some possible applications are listed below.

Keep in mind that the Rabbit can also be operated as a slave processor via a serial port and
some of the protocols will work well via a serial communications connection. If a serial
connection is used, the protocol becomes more complicated if errors in transmission need
to be taken into account. If the physical link can be controlled so that transmission errors
do not occur, a realistic possibility if the interconnection environment is controlled, the
serial protocol is simpler and faster than if error correction needs to be taken into account.

13.3.1 Slave Applications

•

Motion Controller—Many types of motion control require fast action, may be com-
pute-intensive or both. Traditional servo system solutions may be overly expensive or
not work very well because of system nonlinearities. The basic communications model
for a motion controller is for the master to send short messages—positioning com-
mands—to the slave. The slave acknowledges execution of the commands and reports
exception conditions.

•

Communications Protocol Processor—Communications protocols may be very com-
plex, may require fast responses, or may be compute-intensive.

•

Graphics Controller—The Rabbit can be used to perform operations such as drawing
geometric figures and generating characters.

•

Digital Signal Processing—Although the Rabbit is not a speciality digital signal pro-
cessor, it has enough compute speed to handle some types of jobs that might otherwise
require a speciality processor. The slave processor can process data to perform pattern
recognition or to extract a specific parameter from a data stream.

13.3.2 Master-Slave Messaging Protocol

In this protocol the master sends messages to the slave and receives an acknowledgement
message. The protocol can be polled or interrupt driven. Generally, the master sends a
message that has a message type code, perhaps a byte count, and the text of the message.
The slave responds with a similar message as an acknowledgement. Nothing happens
unless the master sends a message. The slave is not allowed to initiate a message, but the
slave could signal the master by using a parallel port line other than /SLAVEATN or by
placing data in one of the registers the master can read without interfering with the mes-
sage protocol.

The master sends a message byte by storing it in SPD0R. The slave notices that SPD0R is
full and reads the byte. When the master notices that SPD0R is empty because the slave
read it, the master stores the next byte in SPD0R. Either side can tell if any register is
empty or full by reading the status register. When the slave acknowledges the message
with a reply message, the process is reversed. To perform the protocol with interrupts, a
slave interrupt can be generated each time the slave receives a character. The slave can
acknowledge the master by reading SPD0R if the master is polling for the slave response

Chapter 13 Rabbit Slave Port

209

to each character. If the master is to be interrupted to acknowledge each character, the
slave can create an interrupt in the master by storing a dummy character in SPD0R to cre-
ate a master interrupt, assuming that the /SLAVEATTN line is wired to interrupt the mas-
ter. The acknowledgement message works in a similar manner, except that the master
writes a dummy character to interrupt the slave to say that it has the character.

Several problems can arise if there are dual interrupts for each character transmitted. One
problem is that the message transmission rate will free run at a speed limited by the inter-
rupt latency and compute speed of each processor. This could consume a high percentage
of the compute resources of one or both processors, starving other processes and espe-
cially interrupt routines, for compute time. If this is a problem, then a timed interrupt can
be used to drive the process on one side, thus limiting the data transmission rate.

Another solution, which may be better than limiting the transmission rate, is to use inter-
rupts only for the first byte of the message on the slave side, and then lower the interrupt
priority and conduct the rest of the transaction as a polled transaction. On the master side
the entire transaction can be a polled transaction. In this case, the entire transaction takes
place in the interrupt routine on the slave, but other interrupts are not inhibited since the
priority has been lowered.

A typical slave system consists of a Rabbit microprocessor and a RAM memory con-
nected to it. The clock can be provided either by connecting a crystal, or crystals to the
slave or by providing an external clock, which could be the master’s clock. The reset line
of the slave would normally be driven by the master. At system startup time the master
resets the slave and cold boots it via the slave port. (The SMODE pins must be configured
for this.) Once the software is loaded into the slave, the slave can begin to perform its
function.

As a simple example, suppose that the slave is to be used as a four-port UART. It has the
capability to send or receive characters on any of its four serial ports. Leaving aside the ques-
tion of setting up parameters such as the baud rate, we could define a protocol as follows.

•

SPD0R readable by master is a status register with bits indicating which of the four
receivers and four transmitters is ready, that is, has a character received or is ready to
send a character.

•

SPD0R writable by the master is a control register used to send commands to the slave.

•

SPD1R is used to send or receive data characters or control bytes.

•

The line /SLAVEATTN is wired to the external interrupt request of the master so that
the master is interrupted when the slave writes to SPD0R. Typically the slave will write
to SPD0R when there is a change of status on one of the serial ports.

The slave can interrupt the master at any time by storing to SPD0R. It will do this every
time an enabled transmitter is ready to accept a character or every time an enabled receiver
receives a character. When it stores to SPD0R, it will store a code indicating the reason for
the interrupt, that is, receive or transmit and channel number. If the cause is receive, the
received character will also be placed in SPD1R writable by the slave. When the master is

Chapter 14 Rabbit 3000 Clocks

211

14. R

ABBIT

3000 C

LOCKS

The Rabbit 3000 normally uses two clocks, the main clock and the 32.768 kHz clock. The
32.768 kHz clock is needed for the battery-backable clock, the watchdog timer, and the
cold-boot function. The main oscillator provides the run-time clock for the microproces-
sor. Figure 14-1 shows the main oscillator circuit. TN235,

External 32.768 kHz Oscillator

Circuits

, provides further information on the 32.768 kHz oscillator circuit and selecting

the values of components to use in the oscillator circuit.

Figure 14-1. Rabbit 3000 Main Oscillator Circuit

NOTE:

You may have to adjust resistors and capacitors for various frequencies and

crystal load capacitances.

The 32.768 kHz oscillator is slow to start oscillating after power-on. For this reason, a
wait loop in the BIOS waits until this oscillator is oscillating regularly before continuing
the startup procedure. If the clock is battery-backed, there will be no startup delay since
the oscillator is already oscillating. The startup delay may be as much as 5 seconds. Crys-
tals with low series resistance (R < 35 k

Ω

) will start faster.

XTALB2

XTALB1

1 M

2 k

33 pF

11.0592 MHz

Main Oscillator Circuit

Chapter 15 EMI Control

213

15. EMI C

ONTROL

EMI or electromagnetic interference from unintentional radiation is of concern to the
microprocessor system designer.

One concern is passing the tests sometimes required by the U.S. Federal Communications
Commission (FCC) or by the European EMC Directive. For example, in the U.S. the FCC
requires that computing devices intended for use in the home or in office environments
(but not industrial or medical environments) not have unintentional electromagnetic radia-
tion above certain limits of field strength that depend on frequency and whether the device
is intended for home or office use. This is verified by measuring radiation from the device
at a test site. The device under test (DUT) is operated in a typical fashion with a typical
mechanical and electrical configuration while the electromagnetic radiation is measured
by a calibrated antenna located either 3 or 10 m from the device. The output of the antenna
is connected to a spectrum analyzer. For the purposes of the test, the spectral power is
measured by using a filter with a bandwidth of 120 kHz. The peak power is measured by
using a “quasi peak” detector in the spectrum analyzer. The quasi peak detector has a
charge time constant of 1 ms and a discharge time constant of 550 ms. In this manner the
peak radiated signal strength is measured. The tests required by the FCC and the EC are
practically identical.

The Rabbit 3000 has important features that aid in the control if EMI.

•

The power supply for the processor core is on separate pins from the power supply for
the I/O buffers associated with the processor and various peripheral devices.

•

A spectrum spreader in the clock circuit can be enabled to spread the spectrum of the
clock by varying the clock frequency in a regular pattern.

•

The built in clock doubler allows the external oscillator circuitry to operate at 1/2 the
ultimate clock frequency.

•

In most cases it is not necessary to route the system clock outside the package, although
a pin is provided for this purpose in the unusual circumstances where it might be neces-
sary. The high speed clock on PC board traces is a major cause of EMI.

If all the EMI suppression features of the Rabbit 3000 are properly utilized and low EMI
design techniques are used on the printed circuit board, system EMI will likely be reduced
to a very low level, probably much lower than is necessary to pass government tests.

214

Rabbit 3000 Microprocessor User’s Manual

15.1 Power Supply Connections and Board Layout

Refer to Technical Note TN221,

PC Board Layout Suggestions for the Rabbit 3000

Microprocessor

, for recommendations on laying out a PC board to minmize EMI emsis-

sions.

15.2 Using the Clock Spectrum Spreader

The spectrum spreader is very powerful for reducing EMI because it will reduce all sources
of EMI above 100 MHz that are related to the clock by about 15 dB. This is a very large
reduction since it is common to struggle to reduce EMI by 5 dB in order to pass government
tests.

Figure 15-1. Peak Spectral Amplitude Reduction from Spectrum Spreader

The spectrum spreader modulates the clock so as to spread out the spectrum of the clock
and its harmonics. Since the government tests use a 120 kHz bandwidth to measure EMI,
spreading the energy of a given harmonic over a wider bandwidth will decrease the
amount of EMI measured for a given harmonic. The spectrum spreader not only reduces
the EMI measured in government tests, but it will also often reduce the interference cre-
ated for radio and television reception.

The spectrum spreader has three settings under software control (see Table 15-1 and
Table 15-2): off, standard spreading and strong spreading.

Two registers control the clock spectrum spreader. These registers must be loaded in a spe-
cific manner with proper time delays. GCM0R is only read by the spectrum spreader at the
moment when the spectrum spreader is enabled by storing 0x080 in GCM1R. If GCM1R
is cleared (when disabling the spectrum spreader), there is up to a 500-clock delay before
the spectrum spreader is actually disabled. The proper procedure is to clear GCM1R, wait
for 500 clocks, set GCM0R, and then enable the spreader by storing 0x080 in GCM1R.

100

200

150

250

350

300

Normal Spreading

Strong Spreading

MHz

Chapter 15 EMI Control

215

When the spectrum spreader is engaged, the frequency is modulated, and individual clock
cycles may be shortened or lengthened by an amount that depends on whether the clock
doubler is engaged and whether the spectrum spreader is set to the normal or strong set-
ting. The frequency modulation amplitude and the change in clock cycle length is greater
at lower voltages or higher temperatures since it is sensitive to process parameters. The
spectrum spreader also introduces a time offset in the system clock edge and an equal off-
set in edges generated relative to the system clock. A feedback system limits the worst
case time error of any signal edge derived from the system clock to plus or minus 20 ns for
the normal setting and plus or minus 40 ns for the strong setting at 3.3 V. The maximum
time offset is inversely proportional to operating voltage. The time error will not usually
interfere with communications channels, except perhaps at the extreme upper data rates.
More details on dealing with the clock variation introduced are available elsewhere (see
Chapter 16, “AC Timing Specifications”).

If the input oscillator frequency is 4 MHz or less the spectrum spreader modulation of fre-
quency will enter the audio range of 20 kHz or less and may generate an audible whistle in
FM stations. For this reason it may be desirable to disable the spreader for low speed oscil-
lators (where it is probably unnecessary anyway). However, in practical cases the whistle
may not be audible due to the very low level of the interference from a system with low
oscillator frequency and the spectrum spreader engaged. Each halving of clock frequency
reduces the amplitude of the harmonics at a given frequency by 6 dB or more.

The effect of pure harmonic noise on an FM station is to either completely block out a sta-
tion near the harmonic frequency or to disturb reception of that station. If the spectrum
spreader is engaged then interference will be spread across the band but will generally be

Table 15-1. Spread Spectrum Enable/Disable Register

Global Clock Modulator 0 Register

(GCM0R)

(Address = 0x0A)

Bit(s)

Value

Description

Enable normal spectrum spreading.

Enable strong spectrum spreading.

6:0

These bits are reserved.

Table 15-2. Spread Spectrum Mode Select

Global Clock Modulator 1 Register

(GCM1R)

(Address = 0x0B)

Bit(s)

Value

Description

Disable the spectrum spreader.

Enable the spectrum spreader.

6:0

These bits are reserved.

Chapter 16 AC Timing Specifications

217

16. AC T

IMING

PECIFICATIONS

The Rabbit 3000 processor may be operated at voltages between 1.8 V and 3.6 V, and at
temperatures from –40°C to +85°C with use possible use over the extended range -55°C to
+105°C. For long life it is desirable not to exceed a die temperature of 125°C. Most users
will operate the Rabbit at 3.3 V.

16.1 Memory Access Time

Required memory address and output enable access time for some important typical cases
are given in the table below. It is assumed that the clock doubler is used, that the clock
spreader is enabled in the normal mode, that the memory early output enable is on, and
that the address bus has 60 pF load.

All important signals on the Rabbit 3000 are output synchronized with the internal clock.
The internal clock is closely synchronized with the external clock (CLK) that may be
optionally output from pin 2 of the TQFP package. The delay in signal output depends on
the capacitive load on the output lines. In the case of the address lines, which are critically
important for establishing memory access time requirements, the capacitive loading is
usually in the range of 25–100 pF, and the load is due to the input capacitance of the mem-
ory devices and PC trace capacitance. Delays are expressed from the waveform midpoint
in keeping with the convention used by memory manufacturers.

Table 16-1. Memory Requirements at 3.3 V, -40°C to +85°C, Adr Bus 60 pF

Clock

Frequency

(MHz)

Period

(ns)

Clock Doubler

Nominal Delay

(ns)

Memory Address

Access

(ns)

Memory Output

Enable Access

(ns)

18.43

22.11

24.00

25.80

29.49

44.24

22.5

33.5

218

Rabbit 3000 Microprocessor User’s Manual

Figure 16-1 illustrates the parameters used to describe memory access time.

Figure 16-1. Parameters Used to Describe Memory Access Time

Table 16-2 lists the delays in gross memory access time for several values of V

When the spectrum spreader is enabled with the clock doubler, every other clock cycle is
shortened (sometimes lengthened) by a maximum amount given in the table above. The
shortening takes place by shortening the high part of the clock. If the doubler is not
enabled, then every clock is shortened during the low part of the clock period. The maxi-
mum shortening for a pair of clocks combined is shown in the table.

Table 16-2. Data and Clock Delays V

±10%, Temp, -40°C–+85°C (maximum)

VDD

Clock to Address Output Delay

(ns)

Data Setup

Time Delay

(ns)

Spectrum Spreader Delay

(ns)

30 pF

60 pF

90 pF

Normal

no dbl/dbl

Strong

no dbl/dbl

3.3

3/4.5

4.5/9

2.7

1.5

3.5/5.5

5.5/11

2.5

1.5

4/6

6/12

1.8

8/12

11/22

delay

capacitive
loading

setup time data to clock

Chapter 16 AC Timing Specifications

219

Figure 16-2 and Figure 16-3 illustrate the memory read and write cycles. The Rabbit 3000
operates at 2 clocks per bus cycle plus any wait states that might be specified.

Figure 16-2. Memory Read and Write Cycles

Tadr

Memory Read (no wait states)

CLK

A[19:0]

Memory Write (no extra wait states)

CLK

A[19:0]

valid

TOEx

D[7:0]

valid

Thold

Tsetup

/CSx

/OEx

TCSx

valid

D[7:0]

TDHZV

TDVHZ

/CSx

/WEx

TCSx

TWEx

220

Rabbit 3000 Microprocessor User’s Manual

The following memory read time delays were measured.

The measurements were taken at the 50% points under the following conditions.

•

T = -40°C to 85°C, V = 3.3 V

•

Internal clock to nonloaded CLK pin delay

≤

1 ns @ 85°C/3.0 V

The following memory write time delays were measured.

The measurements were taken at the 50% points under the same conditions that the mem-
ory read delays were measured.

See Table 16-2 for delays at other voltages.

Table 16-3. Memory Read Time Delays

Time Delay

Output Capacitance

30 pF

60 pF

90 pF

Max. clock to address delay (T

adr

)

6 ns

8 ns

11 ns

Max. clock to memory chip select delay (T

CSx

)

6 ns

8 ns

11 ns

Max. clock to memory read strobe delay (T

OEx

)

6 ns

8 ns

11 ns

Min. data setup time (T

setup

)

1 ns

Min. data hold time (T

hold

)

0 ns

Table 16-4. Memory Write Time Delays

Time Delay

Output Capacitance

30 pF

60 pF

90 pF

Max. clock to address delay (T

adr

)

6 ns

8 ns

11 ns

Max. clock to memory chip select delay (T

CSx

)

6 ns

8 ns

11 ns

Max. clock to memory write strobe delay (T

WEx

)

6 ns

8 ns

11 ns

Max. high Z to data valid rel. to clock (T

DHZV

)

10 ns

12 ns

15 ns

Max. data valid to high Z rel. to clock (T

DVHZ

)

10 ns

12 ns

15 ns

Chapter 16 AC Timing Specifications

221

Figure 16-3. Memory Read and Write Cycles—Early

Output Enable and Write Enable Timing

Tadr

Memory Read (no wait states)

CLK

A[19:0]

Memory Write (no extra wait states)

CLK

A[19:0]

valid

TOEx

D[7:0]

valid

Thold

Tsetup

/CSx

/OEx

TCSx

valid

D[7:0]

TDHZV

TDVHZ

/CSx

/WEx

TCSx

TWEx

222

Rabbit 3000 Microprocessor User’s Manual

Figure 16-4 illustrates the sources that create memory access time delays.

Figure 16-4. Sources of Memory Access Time Delays

The gross memory access time is 2T, where T is the clock period. To calculate the actual
memory access time, subtract the clock to address output time, the data in setup time, and
the clock period shortening due to the clock spectrum spreader from 2T.

Example

•

clock = 29.49 MHz,

•

T = 34 ns,

•

operating voltage is 3.3 V,

•

bus loading is 60 pF,

•

address to output time = 8 ns (see Table 16-2),

•

data setup time = 1 ns,

•

the spectrum spreader is on in normal mode, resulting in a loss of 3 ns.

The access time is given by

access time = 2T - (clock to address) - (data setup) - (spreader delay)

= 68 ns - 8 ns - 1 ns - 3 ns
= 56 ns

data out

address

memory access

time

clock period shortening

output enable

memory output enable
time

Clock

data in setup time

clock to

(early)

output

address

due to spectrum spreader

Chapter 16 AC Timing Specifications

223

The required memory output enable access time is more complicated since it is affected by
the clock doubler delays. The clock doubler setup register creates a nominal delay time
ranging from 6 to 20 ns, resulting in a nominal clock low time ranging from 6 to 20 ns.
The clock low time depends on internal delays, and is subject to variation arising from
process variation, operating voltage and temperature. Minimum and maximum clock low
times for various doubler settings are given in the formulas and in the graph below.

Max. delay @ 3.3 V = 6.1 + 1.21(

- 6) [

is the nominal delay, 6–20 ns)

Min. delay @ 3.3 V = 3.7 + 0.75(

- 6)

Max. delay @ 2.5 V = 7.6 + 1.67(

- 6)

Min. delay @ 2.5 V = 4.7 + 1.03(

- 6)

Max. delay @ 1.8 V = 12.2 + 2.7(

- 6)

Min. delay @ 1.8 V = 6.6 + 1.44(

- 6)

Figure 16-5. Clock Doubler Max-Min Clock Low Times

0.0

10.0

20.0

30.0

40.0

50.0

60.0

Nominal Delay (ns)

lay (ns)

3.3 V

2.5 V

1.8 V

224

Rabbit 3000 Microprocessor User’s Manual

The following factors have to be taken into account when calculating the output enable
access time required.

•

The gross output enable access time is T + minimum clock low time (it is assumed that
the early output enable option is enabled) This is reduced by the spectrum spreader
loss, the time from clock to output for the output enable signal, the data setup time, and
a correction for the asymmetry of the original oscillator clock.

Example

•

Clock = 29.49 MHz,

•

T = 34 ns,

•

operating voltage is 3.3 V,

•

the clock doubler has a nominal delay of 16 ns, resulting in a minimum clock low time
of 12.8 ns,

•

the spectrum spreader is on in normal mode, resulting in a loss of 3 ns,

•

clock to output enable is 5 ns (assuming 20 pF load),

•

the clock asymmetry is 52-48, resulting in a loss of 4% of the clock period, or 1.4 ns.

The output enable access time is given by

access time

= T + (min. clock low) - (clock to output enable) - (spreader delay) - (asymmetry delay)

- (data setup time)

= 34 ns + 12.8 ns - 5 ns - 3 ns - 1.36 ns - 1 ns
= 36.5 ns

Chapter 16 AC Timing Specifications

225

16.2 I/O Access Time

Figure 16-6 illustrates the I/O read and write cycles.

Figure 16-6. I/O Read and Write Cycles—No Extra Wait States

NOTE:

/IOCSx

can be programmed to be active low (default) or active high.

Tadr

External I/O Read (one programmed wait state)

CLK

A[15:0]

External I/O Write (one programmed wait state)

CLK

A[15:0]

/IORD

valid

/BUFEN

/IOCSx

/IOWR

/BUFEN

D[7:0]

valid

Tsetup

Thold

/CSx

/IOCSx

TCSx

TIOCSx

TIORD

TBUFEN

TCSx

TIOCSx

TIORD

TBUFEN

valid

D[7:0]

/CSx

TCSx

TIOCSx

TIOWR

TCSx

TIOCSx

TIOWR

TBUFEN

TDHZV

TDVHZ

226

Rabbit 3000 Microprocessor User’s Manual

The following I/O read time delays were measured.

The measurements were taken at the 50% points under the following conditions.

•

T = -40°C to 85°C, V = 3.3 V

•

Internal clock to nonloaded CLK pin delay

≤

1 ns @ 85°C/3.0 V

The following I/O write time delays were measured.

The measurements were taken at the 50% points under the same conditions that the I/O
read delays were measured.

I/O bus cycles have an automatic wait state and thus require 3 clocks plus any extra wait
states specified.

See Table 16-2 for delays at other voltages.

Table 16-5. I/O Read Time Delays

Time Delay

Output Capacitance

30 pF

60 pF

90 pF

Max. clock to address delay (T

adr

)

6 ns

8 ns

11 ns

Max. clock to memory chip select delay (T

CSx

)

6 ns

8 ns

11 ns

Max. clock to I/O chip select delay (T

IOCSx

)

6 ns

8 ns

11 ns

Max. clock to I/O read strobe delay (T

IORD

)

6 ns

8 ns

11 ns

Max. clock to I/O buffer enable delay (T

BUFEN

)

6 ns

8 ns

11 ns

Min. data setup time (T

setup

)

1 ns

Min. data hold time (T

hold

)

0 ns

Table 16-6. I/O Write Time Delays

Time Delay

Output Capacitance

30 pF

60 pF

90 pF

Max. clock to address delay (T

adr

)

6 ns

8 ns

11 ns

Max. clock to memory chip select delay (T

CSx

)

6 ns

8 ns

11 ns

Max. clock to I/O chip select delay (T

IOCSx

)

6 ns

8 ns

11 ns

Max. clock to I/O write strobe delay (T

IOWR

)

6 ns

8 ns

11 ns

Max. clock to I/O buffer enable delay (T

BUFEN

)

6 ns

8 ns

11 ns

Max. high Z to data valid rel. to clock (T

DHZV

)

10 ns

12 ns

15 ns

Max. data valid to high Z rel. to clock (T

DVHZ

)

10 ns

12 ns

15 ns

Chapter 16 AC Timing Specifications

227

16.3 Further Discussion of Bus and Clock Timing

The clock doubler is normally used, except in situations where low-frequency systems are
specifically being used. The clock doubler works by oring the clock with a delayed ver-
sion of itself. The nominal delay varies from 6 to 20 ns, and is settable under program con-
trol. Any asymmetry in the oscillator waveform before it is doubled will result in alternate
clocks having slightly different periods. Using the suggested oscillator circuit, the asym-
metry is no worse than 52%–48%. This results in a given clock being shortened by the
ratio 50/52, or 4%. Memory access time is not affected because memory bus cycle is 2
clocks long and includes both a long and a short clock, resulting in no net change due to
asymmetry. However, if an odd number of wait states is used, then the memory access
time will be affected slightly.

When the clock spectrum spreader is enabled, clock periods are shortened by a small
amount depending on whether the “normal” or the “strong” spreader setting is used, and
depending on the operating voltage. If the clock doubler is used, the spectrum spreader
affects every other cycle and reduces the clock high time. If the doubler is not used, then
the spreader affects every clock cycle, and the clock low time is reduced. Of course, the
spectrum spreader also lengthens clock cycles, but only the worst case shortening is rele-
vant for calculating worst case access times. The numbers given for clock shortening with
the doubler disabled are the combined shortening for 2 consecutive clock cycles, worst
case.

In computing memory requirements, the important considerations are address access time,
output enable access time, and minimum write pulse required. Increasing the clock dou-
bler delay increases the output enable time, but decreases memory write pulse width. The
early write pulse option can be used to ensure a long-enough write pulse, but then it must
be ensured that the write pulse does not begin before the address lines have stabilized.

Chapter 16 AC Timing Specifications

229

16.4 Maximum Clock Speeds

The Rabbit 3000 is rated for a minimum clock period of 17 ns (commercial specifications)
and 18 ns (industrial specifications). The commercial rating calls for a ±5% voltage varia-
tion from 3.3 V and a temperature range from -40 to + 70°C. The industrial ratings stretch
the voltage variation to ±10% and a temperature range from -40 to + 85°C. This corre-
sponds to maximum clock frequencies of 58.8 MHz (commercial) and 55.5 MHz (indus-
trial). If the clock doubler or spectrum spreader is used, these maximum ratings must be
reduced as shown in the following table. When the doubler is used, the duty cycle of the
clock becomes a critical parameter. The duty cycle should be measured at the separate
clock output pin (pin 2). The minimum period must be increased by any amount that the
clock high time is greater or less than specified in the duty-cycle requirement.

Table 16-7. Maximum Clock Speeds at 3.3 V [Preliminary]

Conditions

Commercial Ratings

Industrial Ratings

Duty Cycle

Requirements

(ns)

Minimum

Period

(ns)

Maximum

Frequency

(MHz)

Minimum

Period

(ns)

Maximum

Frequency

(MHz)

No doubler or
spreader

58.8

55.5

Spreader only
normal

50.0

47.6

Spreader only
strong

47.6

45.4

Doubler only
(8 ns delay)

52.6

50.0

1 > (clock low -
clock high) > 0

Doubler only
(internal 50%
clock)

47.6

1 > (clock low -
clock high) > -1

Spreader
normal with
doubler
(8 ns delay)

47.6

45.4

4 > (clock low -
clock high) > 2

Spreader
normal with
doubler (8 ns
delay), internal
50% clock

41.6

40.0

1 > (clock low -
clock high) > -1

Spreader only
strong

21.5

46.5

22.5

45.0

Spreader strong
with doubler
(8 ns delay)

43.5

41.6

8 > (clock low -
clock high) > 6

Chapter 16 AC Timing Specifications

231

16.5 Power and Current Consumption

With the Rabbit 3000 it is possible to design systems that perform their task with very low
power consumption. Unlike competitive processors, the Rabbit 3000 has short chip select
features designed to minimize power consumption by external memories, which can easily
become the dominant power consumers at low clock frequencies if not well handled.

The preferred configuration for a Rabbit-based system is to use an external crystal or reso-
nator that has a frequency ½ of the maximum internal clock frequency. The oscillator fre-
quency can be doubled or divided by 2, 4, 6, or 8, giving a variety of operating speeds
from the same crystal frequency. In addition, the 32.768 kHz oscillator the drives the bat-
tery-backable clock can be used as the main processor clock and, to save the substantial
power consumed by the fast oscillator, the fast oscillator can be turned off. This scenario
is called the

sleepy mode

with a clock speed in the range of 2 kHz to 32 kHz, and with an

operating system current consumption in the range of 10 to 120 µA depending on fre-
quency and voltage.

Up to an operating speed of 29.5 MHz, a SST39LF512020 256K × 8, 45 ns access time
flash memory combined with any of several 55 ns low-power SRAMs is assumed for cal-
culating the current consumption estimates below.

A crystal frequency of 3.6864 MHz is a good choice for a low-power system consuming
between 2 and 18 mA at 3.3 V as the clock frequency is throttled between 0.46 MHz and
7.37 MHz. The required memory access time is about 250 ns, however, a faster memory
may result in less power since a short chip select cycle can then be used.

A crystal frequency of 11.0592 MHz is a good choice for a medium-power system con-
suming between 5 and 50 mA at 3.3 V as the clock frequency is throttled between 1.4 MHz
and 22 MHz. The required memory access time is 70 ns.

A crystal frequency of 14.7456 MHz is a good choice for a faster medium-power system
consuming between 6 and 65 mA at 3.3 V as the clock frequency is throttled between 1.8
and 29.5 MHz. The required memory access time is 55 ns.

A maximum-speed system that will require fast RAM for program and data can be con-
structed using a 25.8048 MHz crystal. This system will consume between 12 and 112 mA
at 3.3V as the clock speed is throttled between 3 and 51.6 MHz. The required memory
access time is about 20 ns.

Typical system current consumptions are shown in the graphs below. These are for the
processor and oscillator only, and do not include current consumed by memory and other
devices. It is assumed that approximately 30 pF is connected to each address line, particu-
larly A0 and A1, which account for three quarters of the charging current due to the
address lines.

232

Rabbit 3000 Microprocessor User’s Manual

Figure 16-9. Rabbit 3000 System Current vs. Frequency at 3.3 V

Figure 16-10. Rabbit 3000 System Current vs. Frequency at 3.3 V

(enlarged view over 0–16 MHz range)

100

120

Clock Frequency (MHz)

I (mA

)

xtal=25.80

xtal=14.74

xtal=11.05

xtal=3.68

Clock Frequency (MHz)

I (mA

)

xtal=25.80

xtal=14.74

xtal=11.05

xtal=3.68

Chapter 16 AC Timing Specifications

233

Lowering the operating voltage will greatly reduce current consumption and power. Drop-
ping to 2.7 V from 3.3 V will result in 70% current consumption and 60% of the power.
Further dropping to 1.8 V will reduce current to 40% and power to 20% compared to 3.3 V.
Naturally this complicates the selection of memories, especially at 1.8 V.

It is important to know that the lowest speed crystal will not always give the lowest power
consumption because when the crystal is divided internally the short chip select option can
be used to reduce the chip select duty cycle of the flash memory or fast RAM, greatly
reducing the static current consumption associated with some memories.

In sleepy mode, power consumption consists of the processor core, the external recom-
mended external tiny logic 32 kHz oscillator, and the memory. The oscillator consumes
17 µA at 3.3 V, and this drops rapidly to about 2 µA at 1.8 V. The processor core con-
sumes between 3 and 50 µA at 3.3 V as the frequency is throttled from 2 kHz to 32 kHz,
and about 40% as much at 1.8 V. If the flash memory specified above is used for memory
and a self-timed 106 ns chip select is used, then the memory will consume 22 µA at
32 MHz and 1.4 µA at 2 kHz.

In addition to these items, a low-power reset controller may consume about 8 µA and
CMOS leakage may consume several µA, increasing with higher temperatures. The graph
below shows current consumption including the tiny logic core, but not including memory
or the reset controller.

Figure 16-11. Sleepy Mode Current Consumption

2.048

4.096

8.192

16.384

32.768

Clock Frequency (kHz)

I (µ

)

1.8V

2.2V

2.7V

3.0V

3.3V

234

Rabbit 3000 Microprocessor User’s Manual

16.6 Current Consumption Mechanisms

The following mechanisms contribute to the current consumption of the Rabbit 3000
while it is operating.

1. A current proportional to voltage and clock frequency that results from the charging of

internal and external capacitances. At 3.3 V (see (2) below) approximately 57% of the
current is due to charging and 43% is due to crossover current.

2. A crossover current that is proportional to clock frequency and to the overdrive voltage

= V × [(V/2) – 0.7], where V is the operating voltage of the Rabbit 3000. The cross-

over current results from a brief short circuit when both the P and N transistors of a
CMOS buffer are turned on at the same time. This component drops as the voltage
drops, and becomes negligible at 1.4 V.

3. The current consumed by the built-in main oscillator when turned on. This current is

also proportional to V

, and is equal to 1 mA at 3.3 V.

4. The current drawn by the logic that is driven at the oscillator (crystal frequency). This is

considered distinct because it varies with the crystal frequency, but is not reduced when
the clock frequency is divided. This current becomes zero when the main oscillator is
turned off, and is 2.5 mA at 3.3 V when the crystal frequency is 14.7 MHz. This current
is divided between capacitive and crossover components in the same manner as the cur-
rents in (1) and (2) above.

All of the above currents can be combined according to the following formula:

total

(mA) = 0.32 × V × f + 0.23 × Vc × f + 0.30 × Vc + 0.029 × V × fc + 0.025 × Vc × fc

where V = the operating voltage of the Rabbit 3000, V

= V × [(V/2) – 0.7], f

= frequency

of crystal oscillator in MHz, and f = clock frequency in MHz.

236

Rabbit 3000 Microprocessor User’s Manual

16.8 Memory Current Consumption

Since there are many different memories available, let’s look at an example using one of
the recommended flash and SRAM memories.

Flash memory

—SST part SST39LF512020, 256K × 8, 45 ns access time. Standby

current: nil.

•

Static Current (chip select low): 3.5 mA @ 3.3 V

•

Dynamic Current: 7 mA at 14.7 MHz bus speed and 3.3 V

The total current is 10 mA at a clock speed of 29.49 MHz or a bus speed of 5 MHz.

The static part of the current is computed using

3.5 × (chip select duty cycle).

The dynamic part is computed using

0.5 × f in mA,

where f is the bus speed in MHz.

At 0.46 MHz (3.68 MHz/8), and using a short chip select, the duty cycle is about 10%,
giving a static current of about 0.35 mA. The dynamic current is 0.25 mA, for a total cur-
rent of 0.6 mA. Added to the approximately 2.5 mA operating current gives a total current
of 3.1 mA at 0.46 MHz.

In sleepy mode with a self-timed chip select of 106 ns and a clock speed of 32 kHz, the
duty cycle will be 0.106/66 = 1/600, and the static current will be 3.5/600= 6 µA. If the
clock is divided down by a factor of 2, then the static current is reduced to 3 µA. The
dynamic current will be 16 µA at 32 kHz (1000×0.5×f) and 8 µA at 16 kHz.

Chapter 16 AC Timing Specifications

237

16.9 Battery-Backed Clock Current Consumption

When using the suggested tiny logic oscillator, the oscillator and clock consume current as
shown in Figure 16-12 below. Normally a resistor is placed in the battery circuit to limit
the current to about 3 µA, which results in a voltage setpoint of about 1.7 V. When operat-
ing at 3.3 V in sleepy mode, the current of the oscillator and the real-time clock—about
12 µA—must be added.

Using the suggested tiny logic oscillator circuit, the external 32.768 kHz oscillator con-
sumes the following current in µA, where V is the operating voltage.

osc

(µA) = 0.35 × V

+ 0.31 × V

Generally the oscillator will not start unless the voltage is about 1.4 V. However, the oscil-
lator will continue to run until the voltage drops to about 0.8 V. If the oscillator stops, the
current draw is very much lower than when it is running. Below about 1.4 V most of the
current draw is used to charge and discharge the capacitive load.

The current consumed by the battery-backed portion of the Rabbit 3000, which is driven
by the 32.768 kHz oscillator, is given by

rab

(µA) = 0.91 × V

- 1.04 × V (V > 1.14 V)

The current is negligible for V < 1.14 V.

Figure 16-12. Current Consumption—Real-Time Clock and 32 kHz Oscillator Circuit

0.00

2.00

4.00

6.00

8.00

10.00

12.00

1.2

1.4

1.6

1.8

2.2

2.4

Battery-Backup Voltage (V)

Curre

nt (µ

Total Battery Backed

Rabbit 3000 Real-Time Clock

Tiny Logic 32 kHz Osc

238

Rabbit 3000 Microprocessor User’s Manual

16.10 Reduced-Power External Main Oscillator

The circuit in Figure 16-13 can be used to generate the main clock using less power than
with the built-in oscillator buffer. The power consumption is less because of the current-
limiting resistors that cannot be used with the built-in buffer. The 2.2 k

Ω

series resistor

must be reduced as the clock frequency increases, as must be the current-limiting resistors.

Figure 16-13. Reduced-Power External Main Oscillator

Table 16-8 lists results for the reduced-power external oscillator with no current-limiting
resistors.

Design Recommendations

•

Add current-limiting resistors to reduce current without inhibiting oscillator start-up

•

Increase the 1 M

Ω

resistor to improve gain

•

Minimize loop area to reduce EMI

Table 16-8. Current Draw Using Reduced-Power External Oscillator

Ω

current-limiting resistors)

Voltage

(V)

Current (incl built-in buffer)

(mA)

3.3

0.635

2.5

0.380

1.8

0.252

1 M

2.2 k

33 pF

3.68 MHz

= 20 pF)

To Rabbit 3000

XTALA1

+3.3 V

Optional current-reducing

resistors

SN74HCT1G04DBVR

Chapter 17 Rabbit BIOS and Virtual Driver

239

17. R

ABBIT

BIOS

AND

IRTUAL

RIVER

When a program is compiled by Dynamic C for a Rabbit target, the Virtual Driver is auto-
matically incorporated into the program. Virtual Driver is the name given to some initial-
ization routines and a group of services performed by the periodic interrupt. The Rabbit
BIOS, software that handles startup, shutdown and various basic features of the Rabbit, is
compiled to the target along with the application program.

Rabbit Semiconductor provides the full source code for the BIOS and Virtual Driver so
the user can modify them and examine details of the operation that are not apparent from
the documentation.

More details on the BIOS and Virtual Driver software can be found in the

Dynamic C

User’s Manual

, the

Rabbit 3000 Designer’s Handbook

, and the source code in the

Dynamic C libraries.

17.1 The BIOS

The BIOS provided with Dynamic C will work with all Rabbit board products.

The BIOS is compiled separately from the user’s application. It occupies space at the bot-
tom of the root code segment. When execution of the user’s program starts at address zero
on power-up or reset, it starts in the BIOS. When Dynamic C cold-boots the target and
downloads the binary image of the BIOS, the BIOS symbol table is retained to make its
entry points and global data available to the user application. Board specific drivers are
compiled with the user’s program after the BIOS is compiled.

17.1.1 BIOS Services

The BIOS includes support for the following services.

•

System startup: including setup of memory, wait states and clock speed.

•

Writing to flash. Writes to the primary code memory require turning off interrupts for
up to 20 ms or so. To protect the System Identification Block (see the

Rabbit 3000

Designer’s Handbook

for more information on the System ID Block), the flash driver

will not write to that block. A routine that can actually write this block is not included
in the BIOS to make it hard to accidently corrupt this block.

•

Run-time exception handling and logging to handle fatal errors and watchdog time-outs
(error logging not implemented in older versions).

•

Debugging and PC-target communication

240

Rabbit 3000 Microprocessor User’s Manual

17.1.2 BIOS Assumptions

The BIOS makes certain assumptions concerning the physical configuration of the proces-
sor. Processors are expected to have RAM connected to /CS1, /WE1, and /OE1. Flash is
expected to be connected to /CS0, /WE0, and /OE0. (See the

Rabbit 3000 Designer’s

Handbook

Memory Planning chapter if you want to design a board with RAM only.) The

crystal frequency is expected to be n*1.8432 MHz.

The

Rabbit 3000 Designer’s Handbook

has a chapter on the Rabbit BIOS with more

details.

17.2 Virtual Driver

The Virtual Driver is compiled with the user’s application. It includes support for the fol-
lowing services.

•

Hitting the hardware watchdog timer.

•

Decrementing software watchdog timers.

•

Synchronizing the system timer variables with the real-time clock and keeping them
updated.

•

Driving uC/OS-II multi-tasking.

•

Driving slice statement multi-tasking.

17.2.1 Periodic Interrupt

The periodic interrupt that drives the Virtual Driver occurs every 16 clocks or every 488
µs. If the 32.768 kHz oscillator is absent, it is possible to substitute a different periodic
interrupt. This alternative is not supported by Rabbit Semiconductor since the cost of con-
necting a crystal is very small. The periodic interrupt keeps the interrupts turned off (that
is, the processor priority is raised to 1 from zero) for about 75 clocks, so it contributes lit-
tle to interrupt latency.

The periodic interrupt is turned on by default before

main()

is called. It can be disabled if

needed. The

Dynamic C Users’s Manual

chapter on the Virtual Driver provides more

details on the periodic interrupt.

The Rabbit 3000 microprocessor requires the 32 kHz oscillator in order to boot via
Dynamic C, unless a custom loader and BIOS are used.

17.2.2 Watchdog Timer Support

A microprocessor system can crash for a variety of reasons. A software bug or an electri-
cal upset are common reasons. When the system crashes the program will typically settle
into an endless loop because parameters that govern looping behavior have been cor-
rupted. Typically, the stack becomes corrupted and returns are made to random addresses.

The usual corrective action taken in response to a crash is to reset the microprocessor and
reboot the system. The crash can be detected either because an anomaly is detected by pro-

Chapter 18 Other Rabbit Software

243

18. O

THER

ABBIT

OFTWARE

18.1 Power Management Support

The power consumption and speed of operation can be throttled up and down with rough
synchronism. This is done by changing the clock speed or the clock doubler. The range of
control is quite wide: the speed can vary by a factor of 16 when the main clock is driving
the processor. In addition, the main clock can be switched to the 32.768 kHz clock. In this
case, the slowdown is very dramatic, a factor of perhaps 500. In this ultra slow mode, each
clock takes about 30 µs, and a typical instruction takes 150 µs to execute. At this speed,
the periodic interrupt cannot operate because the interrupt routine would execute too
slowly to keep up with an interrupt every 16 clocks. Only about 3 instructions could be
executed between ticks.

A different set of rules applies in the ultra slow or “sleepy” mode. The Rabbit 3000 auto-
matically disables periodic interrupts when the clock mode is switched to 32 kHz or one of
the multiples of 32 kHz. This means that the periodic-interrupt hardware does not function
when running at any of these 32 kHz clock speeds simply because there are not enough
clock cycles available to service the interrupt. Hence virtual watchdogs (which depend on
the periodic interrupt)

cannot

be used in the sleepy mode. The user must set up an endless

loop to determine when to exit sleepy mode. A routine,

updateTimers()

, is provided to

update the system timer variables by directly reading the real-time clock and to hit the
watchdog while in sleepy mode. If the user’s routine cannot get around the loop in the
maximum watchdog timer time-out time, the user should put several calls to

updateTimers()

in the loop. The user should avoid indiscriminate direct access to the

watchdog timer and real-time clock. The least significant bits of the real-time clock cannot
be read in ultra slow mode because they count fast compared to the instruction execution
time. To reduce bus activity and thus power consumption, it is useful to multiply zero by
zero. This requires 12 clocks for one memory cycle and reduces power consumption. Typ-
ically a number of

mul

instructions can be executed between each test of the condition

being waited for.

Dynamic C libraries also provide functions to change clock speeds to enter and exit sleepy
mode. See the

Rabbit 3000 Designer’s Handbook

chapter

Low Power Design and Sup-

port

for more details.

244

Rabbit 3000 Microprocessor User’s Manual

18.2 Reading and Writing I/O Registers

The Rabbit has two I/O spaces: internal I/O registers and external I/O registers.

18.2.1 Using Assembly Language

The fastest way to read and write I/O registers in Dynamic C is to use a short segment of
assembly language inserted in the C program. Access is the same as for accessing data
memory except that the instruction is preceded by a prefix (

IOI

IOE

) to indicate the

internal or external I/O space. For example:

// compute value and write to Port A Data Register

value=x+y

#asm

ld a,(value) ; value to write

ioi ld (PADR),a ; write value to PADR

#endasm

In the example above the

IOI

prefix changes a store to memory to a store to an internal

I/O port. The prefix

ioe

is used for writes to external I/O ports.

18.2.2 Using Library Functions

Dynamic C functions are available to read and write I/O registers. These functions are pro-
vided for convenience. For speed, assembly code is recommended. For a complete
description of the functions noted in this section, refer to the

Dynamic C User’s Manual

or from the

Help

menu in Dynamic C, access the

HTML Function Reference

Function

Lookup

options.

To read internal I/O registers, there are two functions.

int RdPortI(int PORT) ; // returns PORT, high byte zero

int BitRdPortI(int PORT, int bitcode); // bit code 0-7

To write internal I/O registers, there are two functions.

void WrPortI(int PORT, char *PORTShadow, int value);

void BitWrPortI(int PORT, char *PORTShadow, int value, int bitcode);

The external registers are also accessible with Dynamic C functions.

int RdPortE(int PORT) ; // returns PORT, high byte zero

int BitRdPortE(int PORT, int bitcode); // bit code 0-7

int WrPortE(int PORT, char *PORTShadow, int value);

int BitWrPortE(int PORT, char *PORTShadow, int value, int bitcode);

In order to read a port the following code could be used:

k=RdPortI(PADR); // returns Port A Data Register

Chapter 18 Other Rabbit Software

245

18.3 Shadow Registers

Many of the registers of the Rabbit’s internal I/O devices are write-only. This saves gates
on the chip, making possible greater capability at lower cost. Write-only registers are eas-
ier to use if a memory location, called a shadow register, is associated with each write-
only register. To make shadow register names easy to remember, the word shadow is
appended to the register name. For example the register GOCR (Global Output Control
register) has the shadow

GOCRShadow

. Some shadow registers are defined in the BIOS

source code as shown below.

char GCSRShadow; // Global Control Status Register

char GOCRShadow; // Global Output Control Registe

char GCDRShadow; // Global Clock Doubler Register

If the port is a write-only port, the shadow register can be used to find out the port’s con-
tents. For example GCSR has a number of write-only bits. These can be read by consult-
ing the shadow, provided that the shadow register is always updated when writing to the
register.

k=GCSRShadow;

18.3.1 Updating Shadow Registers

If the address of a shadow register is passed as an argument to one of the functions that
write to the internal or external I/O registers, then the shadow register will be updated as
well as the specified I/O register.

NULL

pointer may replace the pointer to a shadow register as an argument to

WrPortI()

and

WrPortE()

; the shadow register associated with the port will not be updated. A pointer

to the shadow register is mandatory for

BitWrPortI()

and

BitWrPortE()

18.3.2 Interrupt While Updating Registers

When manipulating I/O registers and shadow registers, the programmer must keep in
mind that an interrupt can take place in the middle of the sequence of operations, and then
the interrupt routine may manipulate the same registers. If this possibility exists, then a
solution must be crafted for the particular situation. Usually it is not necessary to disable
the interrupts while manipulating registers and their associated shadow registers.

18.3.2.1 Atomic Instruction

As an example, consider the Parallel Port D data direction register (PDDDR). This register
is write only, and it contains 8 bits corresponding to the 8 I/O pins of Parallel Port D. If a
bit in this register is a “1,” the corresponding port pin is an output, otherwise it is an input.
It is easy to imagine a situation where different parts of the application, such as an inter-
rupt routine and a background routine, need to be in charge of different bits in the PDDDR
register. The following code sets a bit in the shadow and then sets the I/O register. If an
interrupt takes place between the

set

and the

LDD

, and changes the shadow register and

PDDDR, the correct value will still be set in PDDDR.

246

Rabbit 3000 Microprocessor User’s Manual

ld hl,PDDDRShadow ; point to shadow register

ld de,PDDDR ; set de to point to I/O reg

set 5,(hl) ; set bit 5 of shadow register

; use ldd instruction for atomic transfer

ioi ldd ; (io de)<-(hl) side effect: hl--, de--

In this case, the

ldd

instruction when used with an I/O prefix provides a convenient data

move from a memory location to an I/O location. Importantly, the

ldd

instruction is an

atomic operation so there is no danger that an interrupt routine could change the shadow
register during the move to the PDDDR register.

18.3.2.2 Non-atomic Instructions

If the following two instructions were used instead of the

ldd

instruction,

ld a,(hl)

ld (PDDDR),a ; output to PDDDR

then an interrupt could take place after the first instruction, change the shadow register and
the PDDDR register, and then after a return from the interrupt, the second instruction
would execute and store an obsolete copy of the shadow register in the PDDDR, setting it
to a wrong value.

18.3.3 Write-only Registers Without Shadow Registers

Shadow register are not needed for many of the registers that can be written to. In some
cases, writing to registers is used as a handy way of changing a peripheral’s state, and the
data bits written are ignored. For example, a write to the status register in the Rabbit serial
ports is used to clear the transmitter interrupt request, but the data bits are ignored, and the
status register is actually a read-only register except for the special functionality attached
to the act of writing the register. An illustration of a write-only register for which a shadow
is unnecessary is the transmitter data register in the Rabbit serial port. The transmitter data
register is a write-only register, but there is little reason to have a shadow register since
any data bits stored are transmitted promptly on the serial port.

18.4 Timer and Clock Usage

The battery-backable real-time clock is a 48 bit counter that counts at 32768 counts per
second. The counting frequency comes from the 32.768 kHz oscillator which is separate
from the main oscillator. Two other important devices are also powered from the 32.768
kHz oscillator: the periodic interrupt and the watchdog timer. It is assumed that all mea-
surements of time will derive from the real-time clock and not the main processor clock
which operates at a much higher frequency (e.g. 22.1184 MHz). This allows the main pro-
cessor oscillator to use less expensive ceramic resonators rather than quartz crystals.
Ceramic resonators typically have an error of 5 parts in 1000, while crystals are much
more accurate, to a few seconds per day.

Chapter 18 Other Rabbit Software

247

Two library functions are provided to read and write the real-time clock:

unsigned long int read_rtc(void) ; // read bits 15-46 rtc

void write_rtc(unsigned long int time) ; // write bits 15-46

// note: bits 0-14 and bit 47 are zeroed

However, it is not intended that the real-time clock be read and written frequently. The
procedure to read it is lengthy and has an uncertain execution time. The procedure for
writing the clock is even more complicated. Instead, Dynamic C software maintains a long
variable

SEC_TIMER

in memory.

SEC_TIMER

is synchronized with the real-time clock

when the Virtual Driver starts, and updated every second by the periodic interrupt. It may
be read or written directly by the user’s programs. Since

SEC_TIMER

is driven by the

same oscillator as the real-time clock there is no relative gain or loss of time between the
two. A millisecond timer variable,

MS_TIMER

, is also maintained by the Virtual Driver.

Two utility routines are provided that can be used to convert times between the traditional
format (10-Jan-2000 17:34:12) and the seconds since 1-Jan-1980 format.

// converts time structure to seconds

unsigned long mktime(struct tm *timeptr);

// seconds to structure

unsigned int mktm(struct tm *timeptr, unsigned long time);

The format of the structure used is the following

struct tm {

char tm_sec; // seconds 0-59

char tm_min; // 0-59

char tm_hour; // 0-59

char tm_mday; // 1-31

char tm_mon; // 1-12

char tm_year; // 00-150 (1900-2050)

char tm_wday; // 0-6 0==sunday

};

The day of the week is not used to compute the long seconds, but it is generated when
computing from long seconds to the structure. A utility program,

setclock.c

, is avail-

able to set the date and time in the real-time clock from the Dynamic C

STDIO

console.

250

Rabbit 3000 Microprocessor User’s Manual

Spreadsheet Conventions

ALTD (“A” Column) Symbol Key

IOI and IOE (“I” Column) Symbol Key

Flag Register Key

Flag

Description

ALTD selects alternate flags

ALTD selects alternate flags and register

ALTD selects alternate register

ALTD operation is a special case

Flag

Description

IOI and IOE affect source and destination

IOI and IOE affect destination

IOI and IOE affect source

Z L/V

* The L/V (logical/overflow) flag serves a dual purpose—

L/V is set to 1 for logical operations if any of the four
most significant bits of the result are 1, and L/V is reset to
0 if all four of the most significant bits of the result are 0.

Description

Sign flag affected

Sign flag not affected

Zero flag affected

Zero flag not affected

LV flag contains logical check result

LV flag contains arithmetic overflow result

LV flag is cleared

LV flag is affected

Carry flag is affected

Carry flag is not affected

Carry flag is cleared

Carry flag is set

Chapter 19 Rabbit Instructions

251

Symbols

Rabbit

Z180

Meaning

b b

Bit select:
000 = bit 0, 001 = bit 1,
010 = bit 2, 011 = bit 3,
100 = bit 4, 101 = bit 5,
110 = bit 6, 111 = bit 7

cc cc

Condition code select:
00 = NZ, 01 = Z,
10 = NC, 11 = C

d d

7-bit (signed) displacement. Expressed in two’s complement.

dd ww

Word register select destination: 00 = BC, 01 = DE, 10 = HL, 11 = SP

dd’

Word register select alternate: 00 = BC’, 01 = DE’, 10 = HL’

e j

8-bit (signed) displacement added to PC.

f f

Condition code select:
000 = NZ (non zero),001 = Z (zero),
010 = NC (non carry), 011 = C (carry),

100 = LZ

(logical zero), 101 = LO

†

(logical one),

110 = P (sign plus), 111 = M (sign minus)

* Logical zero if all four of the most significant bits of the result are 0.
† Logical one if any of the four most significant bits of the result are 1.

m m

MSB of a 16-bit constant.

mn mn

16-bit constant.

n n

8-bit constant or LSB of a 16-bit constant.

r, g

g, g’

Byte register select:
000 = B, 001 = C,
010 = D, 011 = E,
100 = H, 101 = L,
111 = A

Word register select (source): 00 = BC, 01 = DE, 10 = HL, 11 = SP

v v

Restart address select:
010 = 0x0020, 011 = 0x0030,
100 = 0x0040, 101 = 0x0050,
111 = 0x0070

xx xx

Word register select: 00 = BC, 01 = DE, 10 = IX, 11 = SP

yy yy

Word register select: 00 = BC, 01 = DE, 10 = IY, 11 = SP

zz zz

Word register select: 00 = BC, 01 = DE, 10 = HL, 11 = AF

252

Rabbit 3000 Microprocessor User’s Manual

19.1 Load Immediate Data

Instruction clk A I S Z V C Operation

LD IX,mn 8 - - - - IX = mn

LD IY,mn 8 - - - - IY = mn

LD dd,mn 6 r - - - - dd = mn

LD r,n 4 r - - - - r = n

19.2 Load & Store to Immediate Address

Instruction clk A I S Z V C Operation

LD (mn),A 10 d - - - - (mn) = A

LD A,(mn) 9 r s - - - - A = (mn)

LD (mn),HL 13 d - - - - (mn) = L; (mn+1) = H

LD (mn),IX 15 d - - - - (mn) = IXL; (mn+1) = IXH

LD (mn),IY 15 d - - - - (mn) = IYL; (mn+1) = IYH

LD (mn),ss 15 d - - - - (mn) = ssl; (mn+1) = ssh

LD HL,(mn) 11 r s - - - - L = (mn); H = (mn+1)

LD IX,(mn) 13 s - - - - IXL = (mn); IXH = (mn+1)

LD IY,(mn) 13 s - - - - IYL = (mn); IYH = (mn+1)

LD dd,(mn) 13 r s - - - - ddl = (mn); ddh = (mn+1)

19.3 8-bit Indexed Load and Store

Instruction clk A I S Z V C Operation

LD A,(BC) 6 r s - - - - A = (BC)

LD A,(DE) 6 r s - - - - A = (DE)

LD (BC),A 7 d - - - - (BC) = A

LD (DE),A 7 d - - - - (DE) = A

LD (HL),n 7 d - - - - (HL) = n

LD (HL),r 6 d - - - - (HL) = r = B, C, D, E, H, L, A

LD r,(HL) 5 r s - - - - r = (HL)

LD (IX+d),n 11 d - - - - (IX+d) = n

LD (IX+d),r 10 d - - - - (IX+d) = r

LD r,(IX+d) 9 r s - - - - r = (IX+d)

LD (IY+d),n 11 d - - - - (IY+d) = n

LD (IY+d),r 10 d - - - - (Iy+d) = r

LD r,(IY+d) 9 r s - - - - r = (IY+d)

19.4 16-bit Indexed Loads and Stores

Instruction clk A I S Z V C Operation

LD (HL+d),HL 13 d - - - - (HL+d) = L; (HL+d+1) = H

LD HL,(HL+d) 11 r s - - - - L = (HL+d); H = (HL+d+1)

LD (SP+n),HL 11 - - - - (SP+n) = L; (SP+n+1) = H

LD (SP+n),IX 13 - - - - (SP+n) = IXL; (SP+n+1) = IXH

LD (SP+n),IY 13 - - - - (SP+n) = IYL; (SP+n+1) = IYH

LD HL,(SP+n) 9 r - - - - L = (SP+n); H = (SP+n+1)

LD IX,(SP+n) 11 - - - - IXL = (SP+n); IXH = (SP+n+1)

LD IY,(SP+n) 11 - - - - IYL = (SP+n); IYH = (SP+n+1)

LD (IX+d),HL 11 d - - - - (IX+d) = L; (IX+d+1) = H

LD HL,(IX+d) 9 r s - - - - L = (IX+d); H = (IX+d+1)

LD (IY+d),HL 13 d - - - - (IY+d) = L; (IY+d+1) = H

LD HL,(IY+d) 11 r s - - - - L = (IY+d); H = (IY+d+1)

Chapter 19 Rabbit Instructions

253

19.5 16-bit Load and Store 20-bit Address

Instruction clk A I S Z V C Operation

LDP (HL),HL 12 - - - - (HL) = L; (HL+1) = H.

(Adr[19:16] = A[3:0])

LDP (IX),HL 12 - - - - (IX) = L; (IX+1) = H.

(Adr[19:16] = A[3:0])

LDP (IY),HL 12 - - - - (IY) = L; (IY+1) = H.

(Adr[19:16] = A[3:0])

LDP HL,(HL) 10 - - - - L = (HL); H = (HL+1).

(Adr[19:16] = A[3:0])

LDP HL,(IX) 10 - - - - L = (IX); H = (IX+1).

(Adr[19:16] = A[3:0])

LDP HL,(IY) 10 - - - - L = (IY); H = (IY+1).

(Adr[19:16] = A[3:0])

LDP (mn),HL 15 - - - - (mn) = L; (mn+1) = H.

(Adr[19:16] = A[3:0])

LDP (mn),IX 15 - - - - (mn) = IXL; (mn+1) = IXH.

(Adr[19:16] = A[3:0])

LDP (mn),IY 15 - - - - (mn) = IYL; (mn+1) = IYH.

(Adr[19:16] = A[3:0])

LDP HL,(mn) 13 - - - - L = (mn); H = (mn+1).

(Adr[19:16] = A[3:0])

LDP IX,(mn) 13 - - - - IXL = (mn); IXH = (mn+1).

(Adr[19:16] = A[3:0])

LDP IY,(mn) 13 - - - - IYL = (mn); IYH = (mn+1).

(Adr[19:16] = A[3:0])

Note that the

LDP

instructions wrap around on a 64K page boundary. Since the

LDP

instruc-

tion operates on two-byte values, the second byte will wrap around and be written at the
start of the page if you try to read or write across a page boundary. Thus, if you fetch or
store at address 0xn,0xFFFF, you will get the bytes located at 0xn,0xFFFF and
0xn,0x0000 instead of 0xn,0xFFFFand 0x(n+1),0x0000 as you might expect. Therefore,
do

not

use

LDP

at any physical address ending in 0xFFFF.

19.6 Register to Register Moves

Instruction clk A I S Z V C Operation

LD r,g 2 r - - - - r = g, r, g any of B, C, D, E, H, L, A

LD A,EIR 4 fr * * - - A = EIR

LD A,IIR 4 fr * * - - A = IIR

LD A,XPC 4 r - - - - A = MMU

LD EIR,A 4 - - - - EIR = A

LD IIR,A 4 - - - - IIR = A

LD XPC,A 4 - - - - XPC = A

LD HL,IX 4 r - - - - HL = IX

LD HL,IY 4 r - - - - HL = IY

LD IX,HL 4 - - - - IX = HL

LD IY,HL 4 - - - - IY = HL

LD SP,HL 2 - - - - SP = HL

LD SP,IX 4 - - - - SP = IX

LD SP,IY 4 - - - - SP = IY

LD dd’,BC 4 - - - - dd’ = BC (dd’: 00-BC’, 01-DE’, 10-HL’)

LD dd’,DE 4 - - - - dd’ = DE (dd’: 00-BC’, 01-DE’, 10-HL’)

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19.7 Exchange Instructions

Instruction clk A I S Z V C Operation

EX (SP),HL 15 r - - - - H <-> (SP+1); L <-> (SP)

EX (SP),IX 15 - - - - IXH <-> (SP+1); IXL <-> (SP)

EX (SP),IY 15 - - - - IYH <-> (SP+1); IYL <-> (SP)

EX AF,AF’ 2 - - - - AF <-> AF’

EX DE’,HL 2 s - - - - if (!ALTD) then DE’ <-> HL

else DE’ <-> HL’

EX DE’,HL’ 4 s - - - - DE’ <-> HL’

EX DE,HL 2 s - - - - if (!ALTD) then DE <-> HL

else DE <-> HL’

EX DE,HL’ 4 s - - - - DE <-> HL’

EXX 2 - - - - BC <-> BC’; DE <-> DE’;

HL <-> HL’

19.8 Stack Manipulation Instructions

Instruction clk A I S Z V C Operation

ADD SP,d 4 f - - - * SP = SP + d -- d=0 to 255

POP IP 7 - - - - IP = (SP); SP = SP+1

POP IX 9 - - - - IXL = (SP); IXH = (SP+1);

SP = SP+2

POP IY 9 - - - - IYL = (SP); IYH = (SP+1);

SP = SP+2

POP zz 7 r - - - - zzl = (SP); zzh = (SP+1);

SP=SP+2 -- zz= BC,DE,HL,AF

PUSH IP 9 - - - - (SP-1) = IP; SP = SP-1

PUSH IX 12 - - - - (SP-1) = IXH; (SP-2) = IXL;

SP = SP-2

PUSH IY 12 - - - - (SP-1) = IYH; (SP-2) = IYL;

SP = SP-2

PUSH zz 10 - - - - (SP-1) = zzh; (SP-2) = zzl;

SP=SP-2 --zz= BC,DE,HL,AF

19.9 16-bit Arithmetic and Logical Ops

Instruction clk A I S Z V C Operation

ADC HL,ss 4 fr * * V * HL = HL + ss + CF -- ss=BC,

DE, HL, SP

ADD HL,ss 2 fr - - - * HL = HL + ss

ADD IX,xx 4 f - - - * IX = IX + xx -- xx=BC,

DE, IX, SP

A’

F’

H’

D’

L’

E’

B’

C’

EX AF,AF’

EX DE’,HL

EX DE,HL’

EX DE’,HL’

EX DE,HL

EXX - exchange HL,HL’,DE,DE’,BC,BC’

Chapter 19 Rabbit Instructions

255

ADD IY,yy 4 f - - - * IY = IY + yy -- yy=BC,

DE, IY, SP

ADD SP,d 4 f - - - * SP = SP + d -- d=0 to 255

AND HL,DE 2 fr * * L 0 HL = HL & DE

AND IX,DE 4 f * * L 0 IX = IX & DE

AND IY,DE 4 f * * L 0 IY = IY & DE

BOOL HL 2 fr * * 0 0 if (HL != 0) HL = 1,

set flags to match HL

BOOL IX 4 f * * 0 0 if (IX != 0) IX = 1

BOOL IY 4 f * * 0 0 if (IY != 0) IY = 1

DEC IX 4 - - - - IX = IX - 1

DEC IY 4 - - - - IY = IY - 1

DEC ss 2 r - - - - ss = ss - 1 -- ss= BC,

DE, HL, SP

INC IX 4 - - - - IX = IX + 1

INC IY 4 - - - - IY = IY + 1

INC ss 2 r - - - - ss = ss + 1 -- ss= BC,

DE, HL, SP

MUL 12 - - - - HL:BC = BC * DE, signed

32 bit result. DE unchanged

OR HL,DE 2 fr * * L 0 HL = HL | DE -- bitwise or

OR IX,DE 4 f * * L 0 IX = IX | DE

OR IY,DE 4 f * * L 0 IY = IY | DE

RL DE 2 fr * * L * {CY,DE} = {DE,CY} --

left shift with CF

RR DE 2 fr * * L * {DE,CY} = {CY,DE}

RR HL 2 fr * * L * {HL,CY} = {CY,HL}

RR IX 4 f * * L * {IX,CY} = {CY,IX}

RR IY 4 f * * L * {IY,CY} = {CY,IY}

SBC HL,ss 4 fr * * V * HL=HL-ss-CY

(cout if (ss-CY)>hl)

19.10 8-bit Arithmetic and Logical Ops

Instruction clk A I S Z V C Operation

ADC A,(HL) 5 fr s * * V * A = A + (HL) + CF

ADC A,(IX+d) 9 fr s * * V * A = A + (IX+d) + CF

ADC A,(IY+d) 9 fr s * * V * A = A + (IY+d) + CF

ADC A,n 4 fr * * V * A = A + n + CF

ADC A,r 2 fr * * V * A = A + r + CF

ADD A,(HL) 5 fr s * * V * A = A + (HL)

ADD A,(IX+d) 9 fr s * * V * A = A + (IX+d)

ADD A,(IY+d) 9 fr s * * V * A = A + (IY+d)

ADD A,n 4 fr * * V * A = A + n

ADD A,r 2 fr * * V * A = A + r

AND (HL) 5 fr s * * L 0 A = A & (HL)

AND (IX+d) 9 fr s * * L 0 A = A & (IX+d)

AND (IY+d) 9 fr s * * L 0 A = A & (IY+d)

AND n 4 fr * * L 0 A = A & n

AND r 2 fr * * L 0 A = A & r

CP* (HL) 5 f s * * V * A - (HL)

CP* (IX+d) 9 f s * * V * A - (IX+d)

CP* (IY+d) 9 f s * * V * A - (IY+d)

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Rabbit 3000 Microprocessor User’s Manual

CP* n 4 f * * V * A - n

CP* r 2 f * * V * A - r

OR (HL) 5 fr s * * L 0 A = A | (HL)

OR (IX+d) 9 fr s * * L 0 A = A | (IX+d)

OR (IY+d) 9 fr s * * L 0 A = A | (IY+d)

OR n 4 fr * * L 0 A = A | n

OR r 2 fr * * L 0 A = A | r

SBC* (IX+d) 9 fr s * * V * A = A - (IX+d) - CY

SBC* (IY+d) 9 fr s * * V * A = A - (IY+d) - CY

SBC* A,(HL) 5 fr s * * V * A = A - (HL) - CY

SBC* A,n 4 fr * * V * A = A-n-CY (cout if (r-CY)>A)

SBC* A,r 2 fr * * V * A = A-r-CY (cout if (r-CY)>A)

SUB (HL) 5 fr s * * V * A = A - (HL)

SUB (IX+d) 9 fr s * * V * A = A - (IX+d)

SUB (IY+d) 9 fr s * * V * A = A - (IY+d)

SUB n 4 fr * * V * A = A - n

SUB r 2 fr * * V * A = A - r

XOR (HL) 5 fr s * * L 0 A = [A & ~(HL)] | [~A & (HL)]

XOR (IX+d) 9 fr s * * L 0 A = [A & ~(IX+d)] | [~A & (IX+d)]

XOR (IY+d) 9 fr s * * L 0 A = [A & ~(IY+d)] | [~A & (IY+d)]

XOR n 4 fr * * L 0 A = [A & ~n] | [~A & n]

XOR r 2 fr * * L 0 A = [A & ~r] | [~A & r]

* SBC and CP instruction output inverted carry. C is set if A<B if the oper-

ation or virtual operation is (A-B). Carry is cleared if A>=B. SUB outputs

carry in opposite sense from SBC and CP.

19.11 8-bit Bit Set, Reset and Test

Instruction clk A I S Z V C Operation

BIT b,(HL) 7 f s - * - - (HL) & bit

BIT b,(IX+d)) 10 f s - * - - (IX+d) & bit

BIT b,(IY+d)) 10 f s - * - - (IY+d) & bit

BIT b,r 4 f - * - - r & bit

RES b,(HL) 10 d - - - - (HL) = (HL) & ~bit

RES b,(IX+d) 13 d - - - - (IX+d) = (IX+d) & ~bit

RES b,(IY+d) 13 d - - - - (IY+d) = (IY+d) & ~bit

RES b,r 4 r - - - - r = r & ~bit

SET b,(HL) 10 b - - - - (HL) = (HL) | bit

SET b,(IX+d) 13 b - - - - (IX+d) = (IX+d) | bit

SET b,(IY+d) 13 b - - - - (IY+d) = (IY+d) | bit

SET b,r 4 r - - - - r = r | bit

19.12 8-bit Increment and Decrement

Instruction clk A I S Z V C Operation

DEC (HL) 8 f b * * V - (HL) = (HL) - 1

DEC (IX+d) 12 f b * * V - (IX+d) = (IX+d) -1

DEC (IY+d) 12 f b * * V - (IY+d) = (IY+d) -1

DEC r 2 fr * * V - r = r - 1

INC (HL) 8 f b * * V - (HL) = (HL) + 1

INC (IX+d) 12 f b * * V - (IX+d) = (IX+d) + 1

INC (IY+d) 12 f b * * V - (IY+d) = (IY+d) + 1

INC r 2 fr * * V - r = r + 1

Chapter 19 Rabbit Instructions

257

19.13 8-bit Fast A Register Operations

Instruction clk A I S Z V C Operation

CPL 2 r - - - - A = ~A

NEG 4 fr * * V * A = 0 - A

RLA 2 fr - - - * {CY,A} = {A,CY}

RLCA 2 fr - - - * A = {A[6,0],A[7]}; CY = A[7]

RRA 2 fr - - - * {A,CY} = {CY,A}

RRCA 2 fr - - - * A = {A[0],A[7,1]}; CY = A[0]

19.14 8-bit Shifts and Rotates

Instruction clk A I S Z V C Operation

RL (HL) 10 f b * * L * {CY,(HL)} = {(HL),CY}

RL (IX+d) 13 f b * * L * {CY,(IX+d)} = {(IX+d),CY}

RL (IY+d) 13 f b * * L * {CY,(IY+d)} = {(IY+d),CY}

RL r 4 fr * * L * {CY,r} = {r,CY}

RLC (HL) 10 f b * * L * (HL) = {(HL)[6,0],(HL)[7]};

CY = (HL)[7]

RLC (IX+d) 13 f b * * L * (IX+d) = {(IX+d)[6,0],

(IX+d)[7]}; CY = (IX+d)[7]

RLC (IY+d) 13 f b * * L * (IY+d) = {(IY+d)[6,0],

(IY+d)[7]}; CY = (IY+d)[7]

RLC r 4 fr * * L * r = {r[6,0],r[7]}; CY = r[7]

RR (HL) 10 f b * * L * {(HL),CY} = {CY,(HL)}

RR (IX+d) 13 f b * * L * {(IX+d),CY} = {CY,(IX+d)}

RR (IY+d) 13 f b * * L * {(IY+d),CY} = {CY,(IY+d)}

RR r 4 fr * * L * {r,CY} = {CY,r}

RRC (HL) 10 f b * * L * (HL) = {(HL)[0],(HL)[7,1]};

CY = (HL)[0]

RRC (IX+d) 13 f b * * L * (IX+d) = {(IX+d)[0],

(IX+d)[7,1]}; CY = (IX+d)[0]

RRC (IY+d) 13 f b * * L * (IY+d) = {(IY+d)[0],(

IY+d)[7,1]}; CY = (IY+d)[0]

RRC r 4 fr * * L * r = {r[0],r[7,1]}; CY = r[0]

SLA (HL) 10 f b * * L * (HL) = {(HL)[6,0],0}; CY =

(HL)[7]

SLA (IX+d) 13 f b * * L * (IX+d) = {(IX+d)[6,0],0};

CY = (IX+d)[7]

SLA (IY+d) 13 f b * * L * (IY+d) = {(IY+d)[6,0],0};

CY = (IY+d)[7]

RL, RLA

RLC, RLCA

RR, RRA

RRC, RRCA

SLA

SRA

SRL

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Rabbit 3000 Microprocessor User’s Manual

SLA r 4 fr * * L * r = {r[6,0],0}; CY = r[7]

SRA (HL) 10 f b * * L * (HL) = {(HL)[7],(HL)[7,1]};

CY = (HL)[0]

SRA (IX+d) 13 f b * * L * (IX+d) = {(IX+d)[7],

(IX+d)[7,1]}; CY = (IX+d)[0]

SRA (IY+d) 13 f b * * L * (IY+d) = {(IY+d)[7],

(IY+d)[7,1]}; CY = (IY+d)[0]

SRA r 4 fr * * L * r = {r[7],r[7,1]}; CY = r[0]

SRL (HL) 10 f b * * L * (HL) = {0,(HL)[7,1]};

CY = (HL)[0]

SRL (IX+d) 13 f b * * L * (IX+d) = {0,(IX+d)[7,1]};

CY = (IX+d)[0]

SRL (IY+d) 13 f b * * L * (IY+d) = {0,(IY+d)[7,1]};

CY = (IY+d)[0]

SRL r 4 fr * * L * r = {0,r[7,1]};

CY = r[0]

19.15 Instruction Prefixes

Instruction clk A I S Z V C Operation

ALTD 2 - - - - alternate register destinatIn

for next Instruction

IOE 2 - - - - I/O external prefix

IOI 2 - - - - I/O internal prefix

19.16 Block Move Instructions

Instruction clk A I S Z V C Operation

LDD 10 d - - * - (DE) = (HL); BC = BC-1;

DE = DE-1; HL = HL-1

LDDR 6+7i d - - * - if {BC != 0} repeat:

LDI 10 d - - * - (DE) = (HL); BC = BC-1;

DE = DE+1; HL = HL+1

LDIR 6+7i d - - * - if {BC != 0} repeat:

If any of the block move instructions are prefixed by an I/O prefix, the destination will be
in the specified I/O space. Add 1 clock for each iteration for the prefix if the prefix is IOI
(internal I/O). If the prefix is IOE, add 2 clocks plus the number of I/O wait states enabled.
The V flag is set when BC transitions from 1 to 0. If the V flag is not set another step is
performed for the repeating versions of the instructions. Interrupts can occur between dif-
ferent repeats, but not within an iteration equivalent to LDD or LDI. Return from the inter-
rupt is to the first byte of the instruction which is the I/O prefix byte if there is one.

A new

LDIR/LDDR

bug was discovered in September, 2002. The problem has to do with

wait states and the block move operations. With this problem, the first iteration of

LDIR/LDDR

uses the correct number of wait states for both the read and the write. How-

ever, all subsequent iterations use the number of waits programmed for the memory
located at the write address for both the read and the write cycles. This becomes a problem
when moving a block of data from a slow memory device requiring wait states to a fast
memory device requiring no wait states. With respect to external I/O operations, the

LDIR

LDDR

performs reads with zero wait states independent of the waits programmed for the

I/O for all but the first iteration. The first iteration is correct. This bug is automatically cor-
rected by Dynamic C, and will be fixed in future generations of the chip.

Chapter 19 Rabbit Instructions

259

19.17 Control Instructions - Jumps and Calls

Instruction clk A I S Z V C Operation

CALL mn 12 - - - - (SP-1) = PCH; (SP-2) = PCL;

PC = mn; SP = SP-2

DJNZ j 5 r - - - - B = B-1; if {B != 0} PC = PC + j

JP (HL) 4 - - - - PC = HL

JP (IX) 6 - - - - PC = IX

JP (IY) 6 - - - - PC = IY

JP f,mn 7 - - - - if {f} PC = mn

JP mn 7 - - - - PC = mn

JR cc,e 5 - - - - if {cc} PC = PC + e

JR e 5 - - - - PC = PC + e (if e==0 next

seq inst is executed)

LCALL xpc,mn 19 - - - - (SP-1) = XPC; (SP-2) = PCH;

(SP-3) = PCL; XPC=xpc;

PC = mn; SP = (SP-3)

LJP xpc,mn 10 - - - - XPC=xpc; PC = mn

LRET 13 - - - - PCL = (SP); PCH = (SP+1);

XPC = (SP+2); SP = SP+3

RET 8 - - - - PCL = (SP); PCH = (SP+1);

SP = SP+2

RET f 8/2 - - - - if {f} PCL = (SP); PCH =

(SP+1); SP = SP+2

RETI 12 - - - - IP = (SP); PCL = (SP+1);

PCH = (SP+2); SP = SP+3

RST v 10 - - - - (SP-1) = PCH; (SP-2) = PCL;

SP = SP - 2; PC = {R,v)

v=10,18,20,28,38 only

19.18 Miscellaneous Instructions

Instruction clk A I S Z V C Operation

CCF 2 f - - - * CF = ~CF

IPSET 0 4 - - - - IP = {IP[5:0], 00}

IPSET 1 4 - - - - IP = {IP[5:0], 01}

IPSET 2 4 - - - - IP = {IP[5:0], 10}

IPSET 3 4 - - - - IP = {IP[5:0], 11}

IPRES 4 - - - - IP = {IP[1:0], IP[7:2]}

LD A,EIR 4 fr * * - - A = EIR

LD A,IIR 4 fr * * - - A = IIR

LD A,XPC 4 r - - - - A = MMU

LD EIR,A 4 - - - - EIR = A

LD IIR,A 4 - - - - IIR = A

LD XPC,A 4 - - - - XPC = A

NOP 2 - - - - No Operation

POP IP 7 - - - - IP = (SP); SP = SP+1

PUSH IP 9 - - - - (SP-1) = IP; SP = SP-1

SCF 2 f - - - 1 CF = 1

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19.19 Privileged Instructions

The privileged instructions are described in this section. Privilege means that an interrupt
cannot take place between the privileged instruction and the following instruction.

The three instructions below are privileged.

LD SP,HL ; load the stack pointer

LD SP,IY

LD SP,IX

The instructions to load the stack are privileged so that they can be followed by an instruc-
tion to load the stack segment (SSEG) register without the danger of an interrupt taking
place with and incorrect association between the stack pointer and the stack segment reg-
ister. For example,

LD SP,HL

IOI LD (STACKSEG),A

The following instructions are privileged.

IPSET 0 ; shift IP left and set priority 00 in bits 1,0

IPSET 1

IPSET 2

IPSET 3

IPRES ; rotate IP right 2 bits, restoring previous priority

POP IP ; pop IP register from stack

The instructions to modify the IP register are privileged so that they can be followed by a
return instructions that is guaranteed to execute before another interrupt takes place. This
avoids the possibility of an ever-growing stack.

RETI ; pops IP from stack and then pops return address

The instruction

reti

can be used to set both the return address and the IP in a single

instruction. If preceded by a

XPC

, a complete jump or call to a computed address can

be done with no possible interrupt.

LD A,XPC ; get and set the XPC

LD XPC,A

The instruction

XPC,A

is privileged so that it can be followed by other code setting

interrupt priority or program counter without an intervening interrupt.

BIT B,(HL) ; test a bit in memory

The instruction bit

B,(HL)

is privileged to make it possible to implement a semaphore

without disabling interrupts. The following sequence is used. A bit is a semaphore, and the
first task to set the bit owns the semaphore and has a right to manipulate the resources
associated with the semaphore.

BIT B,(HL)

SET B,(HL)

JP z,ihaveit

; here I don’t have it

The

SET

instruction has no effect on the flags. Since no interrupt takes place after the

BIT

instruction, if the flag is zero that means that the semaphore was not set when tested by the
bit instruction and that the set instruction has set the semaphore. If an interrupt was
allowed between the

BIT

and set instructions, another routine could set the semaphore and

two routines could think that they both owned the semaphore.

Chapter 20 Differences Rabbit vs. Z80/Z180 Instructions

261

20. D

IFFERENCES

ABBIT

. Z80/Z180

NSTRUCTIONS

The Rabbit is highly code compatible with the Z80 and Z180, and it is easy to port non I/O
dependent code. The main areas of incompatibility are instructions that are concerned with
I/O or particular hardware implementations. The more important instructions that were
dropped from the Z80/Z180 are automatically simulated by an instruction sequence in the
Dynamic C assembler. A few fairly useless instructions have been dropped and cannot be
easily simulated. Code using these instructions should be rewritten.

The following Z80/Z180 instructions have been dropped and there are no exact substi-
tutes.

DAA

HALT

IM 0

IM 1

IM 2

OUT

OUT0

IN0

SLP

OUTI

IND

OUTD

INIR

OTIR

INDR

OTDR

TESTIO

MLT SP

RRD

RLD

CPI

CPIR

CPD

CPDR

Most of these op codes deal with I/O devices and thus do not represent transportable code.
The only opcodes that are not processor I/O related are

MLT

DAA

RRD

RLD

CPI

CPIR

CPD

, and

CPDR

MLT SP

is not a practical op code. The codes that are concerned

with decimal arithmetic,

DAA

RRD

, and

RLD

, could be simulated, but the simulation is very

inefficient. (The bit in the status register used for half carry is available and can be set and
cleared using the

PUSH AF

and

POP AF

instructions to gain access.) Usually code that

uses these instructions should be rewritten. The instructions

CPI

CPIR

CPD

, and

CPDR

are repeating compare instructions. These instructions are not very useful because the scan
stops when equal compare is detected. Unequal compare would be more useful. They are
difficult to simulate efficiently, so it is suggested that code using these instructions be
rewritten, which in most cases should be quite easy.

The following op codes are dropped.

RST 0

RST 8

RST 0x30

The remaining

RST

instructions are kept, but the interrupt vector is relocated to a variable

location the base of which is established by the IIR register.

RST

can be simulated by a call

instruction, but this is not done automatically by the assembler since most of these instruc-
tions are used for debugging by Dynamic C.

The following instruction has had its op code changed.

EX (SP),HL - old opcode 0x0E3, new opcode - 0x0ED-0x054

Chapter 21 Instructions in Alphabetical Order With Binary Encoding

263

21. I

NSTRUCTIONS

LPHABETICAL

RDER

ITH

INARY

NCODING

Spreadsheet Conventions

ALTD (“A” Column) Symbol Key

Flag

Description

ALTD selects alternate flags

ALTD selects alternate flags and register

ALTD selects alternate register

ALTD operation is a special case

IOI and IOE (“I” Column) Symbol Key

Flag

Description

IOI and IOE affect source and destination

IOI and IOE affect destination

IOI and IOE affect source

Flag Register Key

L/V

Description

Sign flag affected

Sign flag not affected

Zero flag affected

Zero flag not affected

L/V flag contains logical check result

L/V flag contains arithmetic overflow result

L/V flag is cleared

L/V flag is affected

Carry flag is affected

Carry flag is not affected

Carry flag is cleared

Carry flag is set

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Rabbit 3000 Microprocessor User’s Manual

Symbols

The L/V (logical/overflow) flag serves a dual purpose—L/V
is set to 1 for logical operations if any of the four most signif-
icant bits of the result are 1, and L/V is reset to 0 if all four of
the most significant bits of the result are 0.

Rabbit

Z180

Meaning

Bit select:
000 = bit 0,

001 = bit 1,

010 = bit 2,

011 = bit 3,

100 = bit 4,

101 = bit 5,

110 = bit 6,

111 = bit 7

Condition code select:
00 = NZ, 01 = Z,
10 = NC, 11 = C

7-bit (signed) displacement. Expressed in two’s complement.

Word register select destination: 00 = BC, 01 = DE, 10 = HL, 11 = SP

dd'

Word register select alternate: 00 = BC ', 01 = DE ', 10 = HL '

8-bit (signed) displacement added to PC.

Condition code select:
000 = NZ (non zero),

001 = Z (zero),

010 = NC (non carry),

011 = C (carry),

100 = LZ

(logical zero),

101 = LO

†

(logical one),

110 = P (sign plus),

111 = M (sign minus)

MSB of a 16-bit constant.

16-bit constant.

8-bit constant or LSB of a 16-bit constant.

r, g

g, g'

Byte register select:
000 = B,

001 = C,

010 = D,

011 = E,

100 = H,

101 = L,

111 = A

Word register select (source): 00 = BC, 01 = DE, 10 = HL, 11 = SP

Restart address select:
010 = 0x0020, 011 = 0x0030,
100 = 0x0040, 101 = 0x0050,
111 = 0x0070

Word register select: 00 = BC, 01 = DE, 10 = IX, 11 = SP

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Rabbit 3000 Microprocessor User’s Manual

Instruction Byte 1 Byte 2 Byte 3 Byte 4 clk A I S Z V C

ADC A,(HL) 10001110 5 fr s * * V *

ADC A,(IX+d) 11011101 10001110 ----d--- 9 fr s * * V *

ADC A,(IY+d) 11111101 10001110 ----d--- 9 fr s * * V *

ADC A,n 11001110 ----n--- 4 fr * * V *

ADC A,r 10001-r- 2 fr * * V *

ADC HL,ss 11101101 01ss1010 4 fr * * V *

ADD A,(HL) 10000110 5 fr s * * V *

ADD A,(IX+d) 11011101 10000110 ----d--- 9 fr s * * V *

ADD A,(IY+d) 11111101 10000110 ----d--- 9 fr s * * V *

ADD A,n 11000110 ----n--- 4 fr * * V *

ADD A,r 10000-r- 2 fr * * V *

ADD HL,ss 00ss1001 2 fr - - - *

ADD IX,xx 11011101 00xx1001 4 f - - - *

ADD IY,yy 11111101 00yy1001 4 f - - - *

ADD SP,d 00100111 ----d--- 4 f - - - *

ALTD 01110110 2 - - - -

AND (HL) 10100110 5 fr s * * L 0

AND (IX+d) 11011101 10100110 ----d--- 9 fr s * * L 0

AND (IY+d) 11111101 10100110 ----d--- 9 fr s * * L 0

AND HL,DE 11011100 2 fr * * L 0

AND IX,DE 11011101 11011100 4 f * * L 0

AND IY,DE 11111101 11011100 4 f * * L 0

AND n 11100110 ----n--- 4 fr * * L 0

AND r 10100-r- 2 fr * * L 0

BIT b,(HL) 11001011 01-b-110 7 f s - * - -

BIT b,(IX+d)) 11011101 11001011 ----d--- 01-b-110 10 f s - * - -

BIT b,(IY+d)) 11111101 11001011 ----d--- 01-b-110 10 f s - * - -

BIT b,r 11001011 01-b--r- 4 f - * - -

BOOL HL 11001100 2 fr * * 0 0

BOOL IX 11011101 11001100 4 f * * 0 0

BOOL IY 11111101 11001100 4 f * * 0 0

CALL mn 11001101 ----n--- ----m--- 12 - - - -

CCF 00111111 2 f - - - *

CP (HL) 10111110 5 f s * * V *

CP (IX+d) 11011101 10111110 ----d--- 9 f s * * V *

CP (IY+d) 11111101 10111110 ----d--- 9 f s * * V *

CP n 11111110 ----n--- 4 f * * V *

CP r 10111-r- 2 f * * V *

CPL 00101111 2 r - - - -

DEC (HL) 00110101 8 f b * * V -

DEC (IX+d) 11011101 00110101 ----d--- 12 f b * * V -

DEC (IY+d) 11111101 00110101 ----d--- 12 f b * * V -

DEC IX 11011101 00101011 4 - - - -

DEC IY 11111101 00101011 4 - - - -

DEC r 00-r-101 2 fr * * V -

DEC ss 00ss1011 2 r - - - -

ss= 00-BC, 01-DE, 10-HL, 11-SP

DJNZ j 00010000 --(j-2)- 5 r - - - -

EX (SP),HL 11101101 01010100 15 r - - - -

EX (SP),IX 11011101 11100011 15 - - - -

EX (SP),IY 11111101 11100011 15 - - - -

Chapter 21 Instructions in Alphabetical Order With Binary Encoding

267

EX AF,AF' 00001000 2 - - - -

EX DE,HL 11101011 2 s - - - -

EX DE',HL 11100011 2 s - - - -

EX DE,HL' 01110110 11100011 4 s - - - -

EX DE',HL' 01110110 11100011 4 s - - - -

EXX 11011001 2 - - - -

INC (HL) 00110100 8 f b * * V -

INC (IX+d) 11011101 00110100 ----d--- 12 f b * * V -

INC (IY+d) 11111101 00110100 ----d--- 12 f b * * V -

INC IX 11011101 00100011 4 - - - -

INC IY 11111101 00100011 4 - - - -

INC r 00-r-100 2 fr * * V -

INC ss 00ss0011 2 r - - - -

ss= 00-BC, 01-DE, 10-HL, 11-SP

IOE 11011011 2 - - - -

IOI 11010011 2 - - - -

IPSET 0 11101101 01000110 4 - - - -

IPSET 1 11101101 01010110 4 - - - -

IPSET 2 11101101 01001110 4 - - - -

IPSET 3 11101101 01011110 4 - - - -

IPRES 11101101 01011101 4 - - - -

JP (HL) 11101001 4 - - - -

JP (IX) 11011101 11101001 6 - - - -

JP (IY) 11111101 11101001 6 - - - -

JP f,mn 11-f-010 ----n--- ----m--- 7 - - - -

JP mn 11000011 ----n--- ----m--- 7 - - - -

JR cc,e 001cc000 --(e-2)- 5 - - - -

JR e 00011000 --(e-2)- 5 - - - -

Note: If byte following op code is zero, next sequential instruction

is executed. If byte is -2 (11111110) jr is to itself.

LCALL xpc,mn 11001111 ----n--- ----m--- --xpc--- 19 - - - -

LD (BC),A 00000010 7 d - - - -

LD (DE),A 00010010 7 d - - - -

LD (HL),n 00110110 ----n--- 7 d - - - -

LD (HL),r 01110-r- 6 d - - - -

LD (HL+d),HL 11011101 11110100 ----d--- 13 d - - - -

LD (IX+d),HL 11110100 ----d--- 11 d - - - -

LD (IX+d),n 11011101 00110110 ----d--- ----n--- 11 d - - - -

LD (IX+d),r 11011101 01110-r- ----d--- 10 d - - - -

LD (IY+d),HL 11111101 11110100 ----d--- 13 d - - - -

LD (IY+d),n 11111101 00110110 ----d--- ----n--- 11 d - - - -

LD (IY+d),r 11111101 01110-r- ----d--- 10 d - - - -

LD (mn),A 00110010 ----n--- ----m--- 10 d - - - -

LD (mn),HL 00100010 ----n--- ----m--- 13 d - - - -

LD (mn),IX 11011101 00100010 ----n--- ----m--- 15 d - - - -

LD (mn),IY 11111101 00100010 ----n--- ----m--- 15 d - - - -

LD (mn),ss 11101101 01ss0011 ----n--- ----m--- 15 d - - - -

LD (SP+n),HL 11010100 ----n--- 11 - - - -

LD (SP+n),IX 11011101 11010100 ----n--- 13 - - - -

LD (SP+n),IY 11111101 11010100 ----n--- 13 - - - -

Instruction Byte 1 Byte 2 Byte 3 Byte 4 clk A I S Z V C

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Rabbit 3000 Microprocessor User’s Manual

LD A,(BC) 00001010 6 r s - - - -

LD A,(DE) 00011010 6 r s - - - -

LD A,(mn) 00111010 ----n--- ----m--- 9 r s - - - -

LD A,EIR 11101101 01010111 4 fr * * - -

LD A,IIR 11101101 01011111 4 fr * * - -

LD A,XPC 11101101 01110111 4 r - - - -

LD dd,(mn) 11101101 01dd1011 ----n--- ----m--- 13 r s - - - -

LD dd',BC 11101101 01dd1001 4 - - - -

LD dd',DE 11101101 01dd0001 4 - - - -

LD dd,mn 00dd0001 ----n--- ----m--- 6 r - - - -

LD bc,mn 00000001 ...

LD de,mn 00010001 ...

LD hl,mn 00100001 ...

LD sp,mn 00110001 ...

LD EIR,A 11101101 01000111 4 - - - -

LD HL,(HL+d) 11011101 11100100 ----d--- 11 r s - - - -

LD HL,(IX+d) 11100100 ----d--- 9 r s - - - -

LD HL,(IY+d) 11111101 11100100 ----d--- 11 r s - - - -

LD HL,(mn) 00101010 ----n--- ----m--- 11 r s - - - -

LD HL,(SP+n) 11000100 ----n--- 9 r - - - -

LD HL,IX 11011101 01111100 4 r - - - -

LD HL,IY 11111101 01111100 4 r - - - -

LD IIR,A 11101101 01001111 4 - - - -

LD IX,(mn) 11011101 00101010 ----n--- ----m--- 13 s - - - -

LD IX,(SP+n) 11011101 11000100 ----n--- 11 - - - -

LD IX,HL 11011101 01111101 4 - - - -

LD IX,mn 11011101 00100001 ----n--- ----m--- 8 - - - -

LD IY,(mn) 11111101 00101010 ----n--- ----m--- 13 s - - - -

LD IY,(SP+n) 11111101 11000100 ----n--- 11 - - - -

LD IY,HL 11111101 01111101 4 - - - -

LD IY,mn 11111101 00100001 ----n--- ----m--- 8 - - - -

LD r,(HL) 01-r-110 5 r s - - - -

LD r,(IX+d) 11011101 01-r-110 ----d--- 9 r s - - - -

LD r,(IY+d) 11111101 01-r-110 ----d--- 9 r s - - - -

LD r,g 01-r---g 2 r - - - -

LD r,n 00-r-110 ----n--- 4 r - - - -

LD SP,HL 11111001 2 - - - -

LD SP,IX 11011101 11111001 4 - - - -

LD SP,IY 11111101 11111001 4 - - - -

LD XPC,A 11101101 01100111 4 - - - -

LDD 11101101 10101000 10 d - - * -

LDDR 11101101 10111000 6+7i d - - * -

LDI 11101101 10100000 10 d - - * -

LDIR 11101101 10110000 6+7i d - - * -

LDP (HL),HL 11101101 01100100 12 - - - -

LDP (IX),HL 11011101 01100100 12 - - - -

LDP (IY),HL 11111101 01100100 12 - - - -

LDP (mn),HL 11101101 01100101 ----n--- ----m--- 15 - - - -

LDP (mn),IX 11011101 01100101 ----n--- ----m--- 15 - - - -

LDP (mn),IY 11111101 01100101 ----n--- ----m--- 15 - - - -

Instruction Byte 1 Byte 2 Byte 3 Byte 4 clk A I S Z V C

Chapter 21 Instructions in Alphabetical Order With Binary Encoding

269

LDP HL,(HL) 11101101 01101100 10 - - - -

LDP HL,(IX) 11011101 01101100 10 - - - -

LDP HL,(IY) 11111101 01101100 10 - - - -

LDP HL,(mn) 11101101 01101101 ----n--- ----m--- 13 - - - -

LDP IX,(mn) 11011101 01101101 ----n--- ----m--- 13 - - - -

LDP IY,(mn) 11111101 01101101 ----n--- ----m--- 13 - - - -

LJP nbr,mn 11000111 ----n--- ----m--- --nbr--- 10 - - - -

LRET 11101101 01000101 13 - - - -

MUL 11110111 12 - - - -

NEG 11101101 01000100 4 fr * * V *

NOP 00000000 2 - - - -

OR (HL) 10110110 5 fr s * * L 0

OR (IX+d) 11011101 10110110 ----d--- 9 fr s * * L 0

OR (IY+d) 11111101 10110110 ----d--- 9 fr s * * L 0

OR HL,DE 11101100 2 fr * * L 0

OR IX,DE 11011101 11101100 4 f * * L 0

OR IY,DE 11111101 11101100 4 f * * L 0

OR n 11110110 ----n--- 4 fr * * L 0

OR r 10110-r- 2 fr * * L 0

POP IP 11101101 01111110 7 - - - -

POP IX 11011101 11100001 9 - - - -

POP IY 11111101 11100001 9 - - - -

POP zz 11zz0001 7 r - - - -

PUSH IP 11101101 01110110 9 - - - -

PUSH IX 11011101 11100101 12 - - - -

PUSH IY 11111101 11100101 12 - - - -

PUSH zz 11zz0101 10 - - - -

RES b,(HL) 11001011 10-b-110 10 d - - - -

RES b,(IX+d) 11011101 11001011 ----d--- 10-b-110 13 d - - - -

RES b,(IY+d) 11111101 11001011 ----d--- 10-b-110 13 d - - - -

RES b,r 11001011 10-b--r- 4 r - - - -

RET 11001001 8 - - - -

RET f 11-f-000 8/2 - - - -

RETI 11101101 01001101 12 - - - -

RL (HL) 11001011 00010110 10 f b * * L *

RL (IX+d) 11011101 11001011 ----d--- 00010110 13 f b * * L *

RL (IY+d) 11111101 11001011 ----d--- 00010110 13 f b * * L *

RL DE 11110011 2 fr * * L *

RL r 11001011 00010-r- 4 fr * * L *

RLA 00010111 2 fr - - - *

RLC (HL) 11001011 00000110 10 f b * * L *

RLC (IX+d) 11011101 11001011 ----d--- 00000110 13 f b * * L *

RLC (IY+d) 11111101 11001011 ----d--- 00000110 13 f b * * L *

RLC r 11001011 00000-r- 4 fr * * L *

RLCA 00000111 2 fr - - - *

RR (HL) 11001011 00011110 10 f b * * L *

RR (IX+d) 11011101 11001011 ----d--- 00011110 13 f b * * L *

RR (IY+d) 11111101 11001011 ----d--- 00011110 13 f b * * L *

RR DE 11111011 2 fr * * L *

RR HL 11111100 2 fr * * L *

RR IX 11011101 11111100 4 f * * L *

RR IY 11111101 11111100 4 f * * L *

Instruction Byte 1 Byte 2 Byte 3 Byte 4 clk A I S Z V C

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Rabbit 3000 Microprocessor User’s Manual

RR r 11001011 00011-r- 4 fr * * L *

RRA 00011111 2 fr - - - *

RRC (HL) 11001011 00001110 10 f b * * L *

RRC (IX+d) 11011101 11001011 ----d--- 00001110 13 f b * * L *

RRC (IY+d) 11111101 11001011 ----d--- 00001110 13 f b * * L *

RRC r 11001011 00001-r- 4 fr * * L *

RRCA 00001111 2 fr - - - *

RST v 11-v-111 [v=2,3,4,5,7 only] 8 - - - -

SBC (IX+d) 11011101 10011110 ----d--- 9 fr s * * V *

SBC (IY+d) 11111101 10011110 ----d--- 9 fr s * * V *

SBC A,(HL) 10011110 5 fr s * * V *

SBC A,n 11011110 ----n--- 4 fr * * V *

SBC A,r 10011-r- 2 fr * * V *

SBC HL,ss 11101101 01ss0010 4 fr * * V *

SCF 00110111 2 f - - - 1

SET b,(HL) 11001011 11-b-110 10 b - - - -

SET b,(IX+d) 11011101 11001011 ----d--- 11-b-110 13 b - - - -

SET b,(IY+d) 11111101 11001011 ----d--- 11-b-110 13 b - - - -

SET b,r 11001011 11-b--r- 4 r - - - -

SLA (HL) 11001011 00100110 10 f b * * L *

SLA (IX+d) 11011101 11001011 ----d--- 00100110 13 f b * * L *

SLA (IY+d) 11111101 11001011 ----d--- 00100110 13 f b * * L *

SLA r 11001011 00100-r- 4 fr * * L *

SRA (HL) 11001011 00101110 10 f b * * L *

SRA (IX+d) 11011101 11001011 ----d--- 00101110 13 f b * * L *

SRA (IY+d) 11111101 11001011 ----d--- 00101110 13 f b * * L *

SRA r 11001011 00101-r- 4 fr * * L *

SRL (HL) 11001011 00111110 10 f b * * L *

SRL (IX+d) 11011101 11001011 ----d--- 00111110 13 f b * * L *

SRL (IY+d) 11111101 11001011 ----d--- 00111110 13 f b * * L *

SRL r 11001011 00111-r- 4 fr * * L *

SUB (HL) 10010110 5 fr s * * V *

SUB (IX+d) 11011101 10010110 ----d--- 9 fr s * * V *

SUB (IY+d) 11111101 10010110 ----d--- 9 fr s * * V *

SUB n 11010110 ----n--- 4 fr * * V *

SUB r 10010-r- 2 fr * * V *

XOR (HL) 10101110 5 fr s * * L 0

XOR (IX+d) 11011101 10101110 ----d--- 9 fr s * * L 0

XOR (IY+d) 11111101 10101110 ----d--- 9 fr s * * L 0

XOR n 11101110 ----n--- 4 fr * * L 0

XOR r 10101-r- 2 fr * * L 0

ZINTACK (interrupt) 10 - - - -

Instruction Byte 1 Byte 2 Byte 3 Byte 4 clk A I S Z V C

Appendix A The Rabbit Programming Port

271

PPENDIX

ABBIT

ROGRAMMING

ORT

The programming port provides a standard physical and electrical interface between a
Rabbit-based system and the Dynamic C programming platform. A special interface cable
and converter—the

programming cable

— connects a PC serial port to the programming

port. The programming port is usually implemented with a standard 2 mm or 1.27 mm 10-
pin connector. With this setup the PC can communicate with the target, reset it, and reboot
it. The DTR line on the PC serial interface is used to drive the target reset line, which
should be drivable by an external CMOS driver. The STATUS pin is used to by the Rabbit-
based target to respond to Dynamic C before the pilot BIOS and the cold loader binary
files are first transmitted to the target system—Dynamic C will return the "No Rabbit
Processor Detected" error message when there is a problem with detecting the Rabbit
microprocessor. The SMODE pins are pulled up by the +5 V/+3.3 V supplied from the
target system through the programming cable. The SMODE pins should be pulled down to
ground on the board with ~ 5 k

Ω

resistors when the interface is not in use. The target

board provides the +5 V or +3.3 V to the programming cable to power the RS-232 driver
and receiver.

Figure A-1. Rabbit Programming Port

PROGRAMMING PORT PIN ASSIGNMENTS

(Rabbit LQFP pins are shown in parenthesis)

1. RXA (66)

2. GND

3. CKLKA (117)

4. +5 V/+3.3 V

5. /RESET

6. TXA (67)

7. n.c.

8. STATUS (output) (4)
9. SMODE0 (45)
10. SMODE1 (44)

~50 k

GND

~50 k

GND

~50 k

~10 k

Programming Port

Pin Numbers

272

Rabbit 3000 Microprocessor User’s Manual

A.1 Use of the Programming Port as a Diagnostic/Setup Port

The programming port, which is already in place, can serve as a convenient communica-
tions port for field setup, diagnosis or other occasional communication need (for example,
as a diagnostic port). There are several ways that the port can be automatically integrated
into the user’s software scheme. If the purpose of the port is simply to perform a setup
function, that is, write setup information to flash memory, then the controller can be reset
through the programming port, followed by a cold boot to start execution of a special pro-
gram dedicated to this functionality.

The standard programming cable connects the programming interface to a PC program-
ming port. The /RESET line can be asserted by manipulating DTR on the PC serial port
and the STATUS line can be read by the PC as DSR on the serial port. The PC can restart
the target by pulsing reset and then, after a short delay, sending a special character string at
2400 bps. To simply restart the BIOS, the string 0x80, 0x24, 0x80 can be sent. When the
BIOS is started, it can tell whether the

PROG

connector on the programming cable is con-

nected because the SMODE1, SMODE0 pins are sensed as high. This will cause the BIOS
to think that it should enter programming mode. The Dynamic C programming mode then
can have an escape message that will enable the diagnostic serial port function.

Another approach to enabling the diagnostic port is to poll the serial port periodically to
see if communication needs to begin or to enable the port and wait for interrupts. The
SMODE pins can be used for signaling and can be detected by a poll. However, recall that
the SMODE pins have a special function after reset and will inhibit normal reset behavior
if not held low. The pull-up resistors on RXA and CLKA prevent spurious data reception
that might take place if the pins floated.

If the clocked serial mode is used, the serial port can be driven by having two toggling
lines that can be driven and one line that can be sensed. This allows a conversation with a
device that does not have an asynchronous serial port but that has two output signal lines
and one input signal line.

The line TXA (also called PC6) is zero after reset if cold boot mode is not enabled. A pos-
sible way to detect the presence of a cable on the programming port is for the cable to con-
nect TXA to one of the SMODE pins and then test for the connection by raising PC6 and
reading the SMODE pin after the cold boot mode has been disabled.

A.2 Alternate Programming Port

The programming port uses Serial Port A. If the user needs to use Serial Port A in an
application, an alternate method of programming is possible using the same 10-pin pro-
gramming port. For his own application the user should use the alternate I/O pins for port
A that share pins with Parallel Port D. The TXA and RXA pins on the 10-pin program-
ming port are then a parallel port output and parallel port input using pins 6 and 7 on Par-
allel Port C. Using these two ports plus the STATUS pin as an output clock, the user can
create a synchronous clocked communication port using instructions to toggle the clock
and data. Another Rabbit-based board can be used to translate the clocked serial signal to

Appendix A The Rabbit Programming Port

273

an asynchronous signal suitable for the PC. Since the target controls the clock for both
send and receive, the data transmission proceeds at a rate controlled by the target board
under development.

This scheme does not allow for an interrupt, and it is not desirable to use up an external
interrupt for this purpose. The serial port may be used, if desired, During program load
because there is no conflict with the user’s program at compile load time. However, the
user’s program will conflict during debugging. The nature of the transmissions during
debugging is such that the user program starts at a break point or otherwise wants to get
the attention of the PC. The other type of message is when the PC wants to read or write
target memory while the target is running.

The target toggling the clock can simply send a clocked serial message to get the attention
of the PC. The intermediate communications board can accept these unsolicited messages
using its clocked serial port. To prevent overrunning the receiver, the target can wait for a
handshake signal on one of the SMODE lines or there can be suitable pre-arranged delays.

If the PC wants attention from the target it can set a line to request attention (SMODE).
The target will detect this line in the periodic interrupt routine and handle the complete
message in the periodic interrupt routine. This may slow down target execution, but the
interrupts will be enabled on the target while the message is read. The intermediate board
could split long messages into a series of shorter messages if this is a problem.

A.3 Suggested Rabbit Crystal Frequencies

Table A-1 provides a list of suggested Rabbit operating frequencies.

The numbers in

Table A-1

are based on the following assumptions:

•

spectrum spreader set to normal,

•

doubler in use (52/48 duty cycle), and

•

a combined 6 ns for clock to address and data setup times.

The crystal can be half the operating frequency if the clock doubler is used up to 27 MHz.
Beyond this operating clock speed, it is necessary to use an X1 crystal or an external oscil-
lator because asymmetry in the waveform generated by the oscillator becomes a variation
in the clock speed if the clock speed is doubled.

274

Rabbit 3000 Microprocessor User’s Manual

Table A-1. Preliminary Crystal Frequencies,

Memory Access Times, and Baud Rates

Crystal

Frequency

(MHz)

Doubled

Frequency

(MHz)

Doubled

Period

(ns)

Access Time

(ns)

Divisor for

115,200 baud

1.8432

3.6864

271

522

3.6864

7.3728

136

257

7.3728

14.7456

124

9.216

18.432

11.0592

22.1184

12.9024

25.8048

14.7456

29.4912

18.432

36.864

22.1184

44.2368

25.8048

51.6096

Non-Stock Crystals

20.2752

40.5504

21.1968

42.3936

23.04

46.08

23.9616

47.9232

24.8832

49.7664

26.7264

53.4528

Appendix B Rabbit 3000 Revisions

275

PPENDIX

B. R

ABBIT

3000 R

EVISIONS

Since its release, the Rabbit 3000 microprocessor has gone through one revision. The revi-
sion reflects bug fixes, improvements, and the introduction of new features. All Rabbit
3000 revisions are pin-compatible, and transparently replace previous versions of the chip.

The Rabbit 3000 has been supplied in the following versions.

Original Rabbit 3000

—Available in two packages and identified by

IL1T

for the

LQFP package and

IZ1T

for the TFBGA package. The LQFP package began shipping

in March 2002, and the TFBGA package began shipping in January 2003. There were
several bugs:

(a) Port A decode bug—This bug is documented in TN228,

Rabbit 3000 Parallel

Port F Bug

. The problem involves an incomplete address decode of the data

output register for Parallel Port A. If Parallel Port A is used as an output or is
used as the bidirectional bus for the slave port, then writing to any of the Paral-
lel Port F registers will cause a spurious write to the Parallel Port A register.

(b) LDIR/LDDR with wait states—This bug is documented in Section 19.16. The

nature of the problem is such that first iteration of LDIR/LDDR uses the cor-
rect number of wait states for both the read and the write. However, all subse-
quent iterations use the number of waits programmed for the memory located
at the write address for both the read and the write cycles. This becomes a
problem when moving a block of data from a slow memory device requiring
wait states to a fast memory device requiring no wait states.

Section 7.5. When the short chip select option is enabled, the interrupt
sequence will attempt to write the return address to the stack if an interrupt
takes place immediately after an internal or an external I/O instruction. The
chip select will be suppressed during the write cycle, and the correct return
address will not be stored on the stack. This happens only when an interrupt
takes place immediately after an I/O instruction when the short chip select
option is enabled.

(d) IrDA bug—This bug is documented in TN236,

Rabbit 3000 IrDA Bug

. When

configured to operate in the IrDA mode, the serial port may at times generate
an extra pulse before the start bit is transmitted. This pulse may appear either
before a multi-character transmission or before a single-character transmission.
If the beginning of the start bit coincides with when the IrDA pulse generator
output is high, there will be a spurious 1/16th-bit cell pulse on the transmit
output.

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Rabbit 3000 Microprocessor User’s Manual

First revision (Rabbit 3000A)

—Available in two packages and identified by

IL2T

for

the LQFP package and

IZ2T

for the TFBGA package. This version began shipping in

August 2003. All the bugs in the original Rabbit 3000 were fixed. The Rabbit 3000A
contains a number of new features and improvements.

(a) A new mode of operation known as System/User mode was added. This mode

provides a framework for separating application code from system-critical
code, which helps prevent application code from crashing the entire device.
System/User mode is described in detail in Appendix C.

(b) The ability to write-protect 64 KB physical memory blocks was added, with

the option of further protecting two of the 64 KB blocks in 4 KB segments.
Attempts to write to a protected block triggers a Priority 3 write-protection
interrupt.

Priority 3 stack violation interrupt.

(d) RAM segment relocation was added. This feature allows a 1, 2, or 4 KB

segment of the logical memory space to be mapped as data (or for program
execution) when separate I/D space is enabled.

(e) Secondary watchdog timer added. The secondary watchdog timer was added to

function as a safety net for the periodic interrupt.

(f) Two new opcodes were added to support multiply-and-add and multiply-and-

subtract operations on large unsigned integers. These operations can be used to
speed up public-key calculations.

(g) Six new opcodes were added to support block-copy operations from I/O

addresses to memory addresses and vice-versa.

(h) The I/O address space has been expanded to 16 bits to make room for new

peripherals.

(i) Two new features were added to further expand the external I/O interface

capabilities of the processor. First, an option was added to enable or disable the
auxiliary I/O bus interface for a given I/O bank. If the auxiliary I/O bus is dis-
abled for a given external I/O bank, the processor uses the memory bus for
external I/O transactions. The second feature is the addition of an option for
enabling hold time for external I/O read operations. The option shortens the
read strobes by one clock cycle.

(j) The low-power capability of the processor was further expanded with the addi-

tion of short chip select timing for all clock modes (except for divide-by-one
mode) and for reads, writes, or both.

(k) The PWM outputs can now trigger a PWM interrupt each cycle or every

other/fourth/eighth cycle. In addition, the PWM output can be suppressed
every other cycle, three out of every four cycles, or seven out of every eight
cycles. These options were added to provide support for driving servos in addi-
tion to generating audio using the Rabbit 3000A.

Appendix B Rabbit 3000 Revisions

277

(l) The quadrature decoder hardware can be configured to use a 10-bit counter in

place of the existing 8-bit counter.

(m)An option was added to alternatively multiplex PWM outputs, slave chip select

(/SCS), and Serial Ports E and F transmit and receive clocks on other pins.

(n) The Schmitt trigger IC normally required for the low power 32.768 kHz oscil-

lator circuit is now integrated inside the Rabbit 3000A.

NOTE:

Based on this modification, a new low-power oscillator circuit is recommended

for use with Rabbit 3000A-based systems. Please refer to TN235,

External 32.768 kHz

Oscillator Circuits

, for more information on the circuit.

Rabbit 3000 chips identified by

UL2T

for the LQFP package and

DZ2J

for the TFBGA

package are RoHS-compliant. The

UL2T

and

DZ2J

RoHS versions were introduced in

mid-2007, and the

IL2T

and

IZ2T

non-RoHS versions are no longer avaialble.

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B.1 Discussion of Fixes and Improvements

Table B-1 lists the bug fixes, improvements, and additions for the various revisions of the
Rabbit 3000.

Table B-1. Summary of Rabbit 3000 Improvements and Fixes

Description

Rabbit

3000

(IL1T/IZ1T)

Rabbit

3000A

(IL2T/IZ2T)

ID Registers for version/revision identification.

System/User mode.

Memory protection scheme.

Stack protection.

RAM segment relocation.

Secondary watchdog timer.

Multiply-add and multiply-subtract.

Variants of block move opcodes.

16-bit internal I/O address space.

External I/O interface enhancements.

Expanded low-power capability.

PWM improvements.

Quadrature decoder improvements.

Integrated Schmitt trigger for 32 kHz oscillator input.

Alternate output port connection for numerous peripherals.

Port A decode bug fix.

LDIR/LDDR with wait states bug fix.

Interrupt after I/O with short /CSx enabled bug fix.

IrDA bug fix.

Appendix B Rabbit 3000 Revisions

279

B.1.1 Rabbit Internal I/O Registers

Table B-2 summarizes the reset state of the new I/O registers added in the Rabbit 3000A
revision. Table B-3 summarizes the reset state of the existing I/O registers with new features.

Table B-2. Reset State of New Rabbit 3000A I/O Registers

Register Name

Mnemonic

I/O

Address

R/W

Reset

Secondary Watchdog Timer Register

SWDTR

0x000C

11111111

RAM Segment Register

RAMSR

0x0448

00000000

Write Protect Control Register

WPCR

0x0440

00000000

Stack Limit Control Register

STKCR

0x0444

00000000

Stack Low Limit Register

STKLLR

0x0445

xxxxxxxx

Stack High Limit Register

STKHLR

0x0446

xxxxxxxx

Write Protect Low Register

WPLR

0x0460

00000000

Write Protect High Register

WPHR

0x0461

00000000

Write Protect Segment A Register

WPSAR

0x0480

00000000

Write Protect Segment A Low Register

WPSALR

0x0481

00000000

Write Protect Segment A High Register

WPSAHR

0x0482

00000000

Write Protect Segment B Register

WPSBR

0x0484

00000000

Write Protect Segment B Low Register

WPSBLR

0x0485

00000000

Write Protect Segment B High Register

WPSBHR

0x0486

00000000

Real Time Clock User Enable Register

RTUER

0x0300

00000000

Slave Port User Enable Register

SPUER

0x0320

00000000

Parallel Port A User Enable Register

PAUER

0x0330

00000000

Parallel Port B User Enable Register

PBUER

0x0340

00000000

Parallel Port C User Enable Register

PCUER

0x0350

00000000

Parallel Port D User Enable Register

PDUER

0x0360

00000000

Parallel Port E User Enable Register

PEUER

0x0370

00000000

Parallel Port F User Enable Register

PFUER

0x0338

00000000

Parallel Port G User Enable Register

PGUER

0x0348

00000000

Input Capture User Enable Register

ICUER

0x0358

00000000

I/O Bank User Enable Register

IBUER

0x0380

00000000

PWM User Enable Register

PWUER

0x0388

00000000

Quad Decode User Enable Register

QDUER

0x0390

00000000

280

Rabbit 3000 Microprocessor User’s Manual

External Interrupt User Enable Register

IUER

0x0398

00000000

Timer A User Enable Register

TAUER

0x03A0

00000000

Timer B User Enable Register

TBUER

0x03B0

00000000

Serial Port A User Enable Register

SAUER

0x03C0

00000000

Serial Port B User Enable Register

SBUER

0x03D0

00000000

Serial Port C User Enable Register

SCUER

0x03E0

00000000

Serial Port D User Enable Register

SDUER

0x03F0

00000000

Serial Port E User Enable Register

SEUER

0x03C8

00000000

Serial Port F User Enable Register

SFUER

0x03D8

00000000

Enable Dual-Mode Register

EDMR

0x0420

00000000

Quad Decode Count1 High Register

QDC1HR

0x0095

xxxxxxxx

Quad Decode Count 2 High Register

QDC2HR

0x0097

xxxxxxxx

Table B-2. Reset State of New Rabbit 3000A I/O Registers (continued)

Register Name

Mnemonic

I/O

Address

R/W

Reset

Appendix B Rabbit 3000 Revisions

281

Table B-3. Reset State of I/O Registers Modified in Rabbit 3000A

Register Name

Mnemonic

I/O

Address

R/W

Rabbit

3000

Reset

Rabbit

3000A

Reset

Global Power Save Control Register

GPSCR

0x000D

0000x000

00000000

Global Revision Register

GREV

0x002F

0xx00000

0xx00001

MMU Expanded Code Register

MECR

0x0018

R/W

xxxxx000

00000000

Memory Timing Control Register

MTCR

0x0019

xxxx0000

00000000

Breakpoint/Debug Control Register

BDCR

0x001C

0xxxxxxx

00000000

I/O Bank 0 Control Register

IB0CR

0x0080

000000xx

00000000

I/O Bank 1 Control Register

IB1CR

0x0081

000000xx

00000000

I/O Bank 2 Control Register

IB2CR

0x0082

000000xx

00000000

I/O Bank 3 Control Register

IB3CR

0x0083

000000xx

00000000

I/O Bank 4 Control Register

IB4CR

0x0084

000000xx

00000000

I/O Bank 5 Control Register

IB5CR

0x0085

000000xx

00000000

I/O Bank 6 Control Register

IB6CR

0x0086

000000xx

00000000

I/O Bank 7 Control Register

IB7CR

0x0087

000000xx

00000000

PWM LSB 0 Register

PWL0R

0x0088

xxxxxxxx

xxxxx00x

PWM LSB 1 Register

PWL1R

0x008A

xxxxxxxx

xxxxx00x

PWM LSB 2 Register

PWL2R

0x008C

xxxxxxxx

xxxxx00x

PWM LSB 3 Register

PWL3R

0x008E

xxxxxxxx

xxxxx00x

Quad Decode Control Register

QDCR

0x0091

00xx0000

00000000

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Rabbit 3000 Microprocessor User’s Manual

B.1.2 Peripheral and ISR Address

Table B-4. Rabbit 3000 I/O Address Ranges

and Interrupt Service Vectors

On-Chip Peripheral

I/O Address Range

ISR Starting Address

System Management

0x0000–0x000F

{R[7:1], 0, 0x00}

Memory Management

0x0010–0x001F and

0x0400–0x04FF

No interrupts

Slave Port

0x0020–0x002F

{IIR[7:1], 0, 0x80}

Parallel Port A

0x0030–0x0037

No interrupts

Parallel Port F

0x0038–0x003F

No interrupts

Parallel Port B

0x0040–0x0047

No interrupts

Parallel Port G

0x0048–0x004F

No interrupts

Parallel Port C

0x0050–0x0055

No interrupts

Input Capture

0x0056–0x005F

{IIR[7:1], 1, 0xA0}

Parallel Port D

0x0060–0x006F

No interrupts

Parallel Port E

0x0070–0x007F

No interrupts

External I/O Control

0x0080–0x0087

No interrupts

Pulse Width Modulator

0x0088–0x008F

{IIR[7:1], 1, 0x70}

Quadrature Decoder

0x0090–0x0097

{IIR[7:1], 1, 0x90}

External Interrupts

0x0098–0x009F

INT0 {EIR, 0x00}

INT1 {EIR, 0x10}

Timer A

0x00A0–0x00AF

{IIR[7:1], 0, 0xA0}

Timer B

0x00B0–0x00BF

{IIR[7:1], 0, 0xB0}

Serial Port A (async/cks)

0x00C0–0x00C7

{IIR[7:1], 0, 0xC0}

Serial Port E (async/HDLC)

0x00C8–0x00CF

{IIR[7:1], 1, 0xC0}

Serial Port B (async/cks)

0x00D0–0x00D7

{IIR[7:1], 0, 0xD0}

Serial Port F (async/HDLC)

0x00D8–0x00DF

{IIR[7:1], 1, 0xD0}

Serial Port C (async/cks)

0x00E0–0x00E7

{IIR[7:1], 0, 0xE0}

Serial Port D (async/cks)

0x00F0–0x00F7

{IIR[7:1], 0, 0xF0}

RST 10 instruction

n/a

{IIR[7:1], 0, 0x20}

RST 18 instruction

n/a

{IIR[7:1], 0, 0x30}

RST 20 instruction

n/a

{IIR[7:1], 0, 0x40}

RST 28 instruction

n/a

{IIR[7:1], 0, 0x50}

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Rabbit 3000 Microprocessor User’s Manual

B.1.5 Memory Protection

The ability to inhibit writes to physical memory was added. The sixteen 64 KB physical
memory blocks can be individually protected, and two of those blocks can additionally be
subdivided and protected at a granularity of 4 KB. When a write is attempted, a new
Priority 3 write-protection interrupt request is generated.

The write-protection can be enabled for the User mode only or for all modes (see
Appendix C for more information).

Figure B-1. Sample Memory Protection Layout

The new memory-protection registers are listed in Table B-6 through T able B-11.

Table B-6. Write Protect Control Register

Write Protect Control Register

(WPCR)

(Address = 0x0440)

Bit(s)

Value

Description

7:1

These bits are reserved and should be written with zeros.

write-protection in User mode only.

write-protection in System and User modes.

0x00000

0xFFFFF

0x40000

0x4FFFF

0x48000

WPHR = 0x85
WPLR = 0x6C

WPSAR = 0x04
WPSAHR = 0x07
WPSALR = 0xCC

Appendix B Rabbit 3000 Revisions

287

Table B-7. Write Protect Low Register

Write Protect Low Register

(WPLR)

(Address = 0x0460)

Bit(s)

Value

Description

Disable 64K write-protect for physical address 0x70000–0x7FFFF.

Enable 64K write-protect for physical address 0x70000–0x7FFFF.

Disable 64K write-protect for physical address 0x60000–0x6FFFF.

Enable 64K write-protect for physical address 0x60000–0x6FFFF.

Disable 64K write-protect for physical address 0x50000–0x5FFFF.

Enable 64K write-protect for physical address 0x50000–0x5FFFF.

Disable 64Kwrite-protect for physical address 0x40000–0x4FFFF.

Enable 64K write-protect for physical address 0x40000–0x4FFFF.

Disable 64K write-protect for physical address 0x30000–0x3FFFF.

Enable 64Kwrite-protect for physical address 0x30000–0x3FFFF.

Disable 64K write-protect for physical address 0x20000–0x2FFFF.

Enable 64K write-protect for physical address 0x20000–0x2FFFF.

Disable 64K write-protect for physical address 0x10000–0x1FFFF.

Enable 64K write-protect for physical address 0x10000–0x1FFFF.

Disable 64K write-protect for physical address 0x00000–0x0FFFF.

Enable 64K write-protect for physical address 0x00000–0x0FFFF.

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Rabbit 3000 Microprocessor User’s Manual

Table B-8. Write Protect High Register

Write Protect High Register

(WPHR)

(Address = 0x0461)

Bit(s)

Value

Description

Disable 64K write-protect for physical address 0xF0000–0xFFFFF.

Enable 64K write-protect for physical address 0xF0000–0xFFFFF.

Disable 64K write-protect for physical address 0xE0000–0xEFFFF.

Enable 64K write-protect for physical address 0xE0000–0xEFFFF.

Disable 64K write-protect for physical address 0xD0000–0xDFFFF.

Enable 64K write-protect for physical address 0xD0000–0xDFFFF.

Disable 64K write-protect for physical address 0xC0000–0xCFFFF.

Enable 64K write-protect for physical address 0xC0000–0xCFFFF.

Disable 64K write-protect for physical address 0xB0000–0xBFFFF.

Enable 64K write-protect for physical address 0xB0000–0xBFFFF.

Disable 64K write-protect for physical address 0xA0000–0xAFFFF.

Enable 64K write-protect for physical address 0xA0000–0xAFFFF.

Disable 64K write-protect for physical address 0x90000–0x9FFFF.

Enable 64K write-protect for physical address 0x90000–0x9FFFF.

Disable 64K write-protect for physical address 0x80000–0x8FFFF.

Enable 64K write-protect for physical address 0x80000–0x8FFFF.

Table B-9. Write Protect Segment x Register

Write Protect Segment x Register

(WPSAR)

(Address = 0x0480)

(WPSBR)

(Address = 0x0484)

Bit(s)

Value

Description

7:4

These bits are reserved and should be written with all zeros.

3:0

When these four bits match bits [19:16] of the physical address, write-protect
that 64K range in 4K increments using WPSxLR and WPSxHR.

Appendix B Rabbit 3000 Revisions

289

Table B-10. Write Protect Segment x Low Register

Write Protect Segment x Low Register

(WPSALR)

(Address = 0x0481)

(WPSBLR)

(Address = 0x0485)

Bit(s)

Value

Description

Disable 4K write-protect for address offset 0x7000–0x7FFF in WP Segment x

Enable 4K write-protect for address offset 0x7000–0x7FFF in WP Segment x

Disable 4K write-protect for address offset 0x6000–0x6FFF in WP Segment x

Enable 4K write-protect for address offset 0x6000–0x6FFF in WP Segment x

Disable 4K write-protect for address offset 0x5000–0x5FFF in WP Segment x

Enable 4K write-protect for address offset 0x5000–0x5FFF in WP Segment x

Disable 4K write-protect for address offset 0x4000–0x4FFF in WP Segment x

Enable 4K write-protect for address offset 0x4000–0x4FFF in WP Segment x

Disable 4K write-protect for address offset 0x3000–0x3FFF in WP Segment x

Enable 4K write-protect for address offset 0x3000–0x3FFF in WP Segment x

Disable 4K write-protect for address offset 0x2000–0x2FFF in WP Segment x

Enable 4K write-protect for address offset 0x2000–0x2FFF in WP Segment x

Disable 4K write-protect for address offset 0x1000–0x1FFF in WP Segment x

Enable 4K write-protect for address offset 0x1000–0x1FFF in WP Segment x

Disable 4K write-protect for address offset 0x0000–0x0FFF in WP Segment x

Enable 4K write-protect for address offset 0x0000–0x0FFF in WP Segment x

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Table B-11. Write Protect Segment x High Register

Write Protect Segment x High Register

(WPSAHR)

(Address = 0x0482)

(WPSBHR)

(Address = 0x0486)

Bit(s)

Value

Description

Disable 4K write-protect for address offset 0xF000–0xFFFF in WP Segment x

Enable 4K write-protect for address offset 0xF000–0xFFFF in WP Segment x

Disable 4K write-protect for address offset 0xE000–0xEFFF in WP Segment x

Enable 4K write-protect for address offset 0xE000–0xEFFF in WP Segment x

Disable 4K write-protect for address offset 0xD000–0xDFFF in WP Segment x

Enable 4K write-protect for address offset 0xD000–0xDFFF in WP Segment x

Disable 4K write-protect for address offset 0xC000–0xCFFF in WP Segment x

Enable 4K write-protect for address offset 0xC000–0xCFFF in WP Segment x

Disable 4K write-protect for address offset 0xB000–0xBFFF in WP Segment x

Enable 4K write-protect for address offset 0xB000–0xBFFF in WP Segment x

Disable 4K write-protect for address offset 0xA000–0xAFFF in WP Segment x

Enable 4K write-protect for address offset 0xA000–0xAFFF in WP Segment x

Disable 4K write-protect for address offset 0x9000–0x9FFF in WP Segment x

Enable 4K write-protect for address offset 0x9000–0x9FFF in WP Segment x

Disable 4Kwrite-protect for address offset 0x8000–0x8FFF in WP Segment x

Enable 4K write-protect for address offset 0x8000–0x8FFF in WP Segment x

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Rabbit 3000 Microprocessor User’s Manual

The stack protection registers are listed in Table B-12, Table B-13, and Table B-14.

Table B-12. Stack Limit Control Register

Stack Limit Control Register

(STKCR)

(Address = 0x0444)

Bit(s)

Value

Description

7:1

These bits are reserved and should be written with zeros.

Disable stack-limit checking.

Enable stack-limit checking.

Table B-13. Stack Low Limit Register

Stack Low Limit Register

(STKLLR)

(Address = 0x0445)

Bit(s)

Value

Description

7:0

Lower limit for stack limit checking. If a stack operation or stack-relative
memory access is attempted at an address less than {STKLLR, 0x10} a stack
limit violation interrupt is generated.

Table B-14. Stack High Limit Register

Stack High Limit Register

(STKHLR)

(Address = 0x0446)

Bit(s)

Value

Description

7:0

Upper limit for stack limit checking. If a stack operation or stack-relative
memory access is attempted at an address greater than {STKHLR, 0x0EF} a
stack limit violation interrupt is generated.

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Rabbit 3000 Microprocessor User’s Manual

B.1.8 Secondary Watchdog Timer

The secondary watchdog timer (SWDT) is an eight-bit modulo n + 1 counter clocked by
the 32.768 kHz clock. The timer is off by default, and is enabled by writing a 0x5F to the
WDTCR. The secondary watchdog timer register (SWDTR) holds the time constant
value. Depending on the value loaded into the SWDTR, the timer can request an interrupt
anywhere from 30.5 µs to 7.8 ms. If a 0x5F is written to the WDTCR prior to end of the
countdown period, the timer will not request an interrupt. If the counter counts down to
zero, a level-3 interrupt is generated. The SWDT is intended as a safety net for the peri-
odic interrupt, and would normally be restarted in the service routine for the periodic inter-
rupt. Although the hardware was intended to primarily be used by an operating system
when the System/User mode is enabled, it can be used as a configurable periodic interrupt
as well.

Table B-16. Watchdog Timer Control Register—Updated

Watchdog Timer Control Register (WDTCR) Address = 0x0008)

Bit(s)

Value

Description

7:0

0x5A

Restart the watchdog timer, with a 2-second time-out period.

0x57

Restart the watchdog timer, with a 1-second time-out period.

0x59

Restart the watchdog timer, with a 500 ms time-out period.

0x53

Restart the watchdog timer, with a 250 ms time-out period.

0x5F

Restart the secondary watchdog timer.

other

No effect on watchdog timer or secondary watchdog timer.

Table B-17. Secondary Watchdog Timer Register

Secondary Watchdog Timer Register (SWDTR) (Address = 0x000C)

Bit(s)

Value

Description

7:0

The time constant for the secondary watchdog timer is stored. This time constant
will take effect the next time that the secondary watchdog counter counts down
to zero. The timer counts modulo n + 1, where n is the programmed time
constant. The secondary watchdog can be disabled by writing the sequence
0x5A-0x52-0x44 to this register.

Appendix B Rabbit 3000 Revisions

295

B.1.9 New Opcodes

Eight new opcodes were added to the Rabbit 3000A. UMA and UMS allow multiply-and-
add and multiply-and-subtract operations on large integers, and were added to speed up
common cryptographic math used in public-key calculations. The remaining six expand
the block copy operations available, especially to and from I/O addresses (internal and
external). These opcodes are listed in Table B-18.

B.1.9.1 New UMA/UMS Opcodes

The new

UMA

and

UMS

opcodes perform the following operation:

{CY:DE':(HL)} = (IX) ± [(IY) * DE + DE' + CY];

where HL, IX, and IY increment after each byte, repeated BC times. This fundamental
operation allows the addition or subtraction of two arbitrarily-long unsigned integers after
one is scaled by a single-byte value. This operation is common in many cryptographic
operations.

Table B-18. New Rabbit 3000 Opcodes

Instruction Bytes Clks A

S Z V C

Operation

UMA

8+8i

{CY:DE':(HL) = (IX) + [(IY) * DE + DE' + CY];

BC = BC-1; IX = IX+1; IY = IY+1; HL = HL+1;

repeat while BC !=0

UMS

8+8i

{CY:DE:(HL) = (IX) - [(IY) * DE + DE' + CY];

BC = BC-1; IX = IX+1; IY = IY+1; HL = HL+1;

repeat while BC !=0

LDDSR

6+7i

(DE) = (HL); BC = BC - 1; HL = HL - 1;
repeat while BC != 0

LDISR

6+7i

(DE) = (HL); BC = BC - 1; HL = HL + 1;
repeat while BC != 0

LSDR

6+7i

(DE) = (HL); BC = BC - 1; DE = DE - 1;
HL = HL - 1; repeat while BC != 0

LSIR

6+7i

(DE) = (HL); BC = BC - 1; DE = DE + 1;
HL = HL + 1; repeat while BC != 0

LSDDR

6+7i

(DE) = (HL); BC = BC - 1; DE = DE - 1;
repeat while BC != 0

LSIDR

6+7i

(DE) = (HL); BC = BC - 1; DE = DE + 1;
repeat while BC != 0

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Rabbit 3000 Microprocessor User’s Manual

B.1.9.2 New Block Copy Opcodes

The LDxR family of block move opcodes has been expanded. In the Rabbit 3000 proces-
sor, block copy operations could only be done between memory addresses, or from mem-
ory to an I/O address. In addition, the destination I/O address would increment (or
decrement if using LDDR) after each byte, making the block copy opcodes effectively
useless for repeated reads or writes to a peripheral (for example, a device on the external
I/P bus).

Six new block copy opcodes were added to the Rabbit 3000 revision. These opcodes can
copy from an I/O address as well as to one, and either the source or destination address can
remain fixed instead of changing after each byte. The new opcodes are described in
Table B-19.

Table B-19. Rabbit 3000 Revision Block Copy Opcode Effects

Opcode

Source

Address

Change

Destination

Address

Change

IOI/IOE
Affects

LDDR

destination

LDIR

destination

LDDSR

none

destination

LDISR

none

destination

LSDR

source

LSIR

source

LSDDR

none

source

LSIDR

none

source

Appendix B Rabbit 3000 Revisions

297

B.1.10 Expanded I/O Memory Addressing

In the Rabbit 3000, only the lower 8 bits of an I/O address were decoded. To provide room
for new peripherals, this was expanded to 16 bits. To ensure backwards compatibility, the
processor always comes up in 8-bit I/O address mode; the 16-bit I/O address mode needs
to be enabled in the MMIDR register by setting bit 7 to 1.

The updated MMIDR register is listed in Table B-20.

NOTE:

Bits 7 was always written with a zero in the original Rabbit 3000 chip.

Table B-20. MMU Instruction/Data Register

MMU Instruction/Data Register

(MMIDR)

(Address = 0x010)

Bit(s)

Value

Description

8-bit internal I/O addresses (address range 0x0000–0x00FF).

15-bit internal I/O addresses (address range 0x0000–0x7FFF, required to access
internal I/O addresses of 0x0100 and higher).

This bit is ignored and will always return zero when read.

Enable A16 and A19 inversion independent of instruction/data.

Enable A16 and A19 inversion (controlled by bits 0-3) for data accesses only.
This enables the instruction/data split for the separate I and D space.

Normal /CS1 operation.

Force /CS1 always active. This will not cause any conflicts as long as the
memory using /CS1 does not also share an Output Enable or Write Enable with
another memory.

Normal operation.

For a DATASEG access, invert A19 before MBxCR (bank select) decision.

Normal operation.

For a DATASEG access: invert A16

Normal operation.

For root access, invert A19 before MBxCR (bank select) decision.

Normal operation.

For root access, invert A16

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B.1.11 External I/O Improvements

Three new features have been added to the external I/O strobes: the ability to invert the
strobe signal, the ability to shorten a read strobe by one clock, and the ability to direct a
strobe to either the alternate I/O bus (if enabled) or the memory bus.

The new control bits for the external I/O strobes are listed in Table B-21.

NOTE:

Bits [1:0] were always written with zero in the original Rabbit 3000 chip.

Table B-21. I/O Bank x Control Register

I/O Bank x Control Register

(IB0CR)

(Address = 0x0080)

(IB1CR)

(Address = 0x0081)

(IB2CR)

(Address = 0x0082)

(IB3CR)

(Address = 0x0083)

(IB4CR)

(Address = 0x0084)

(IB5CR)

(Address = 0x0085)

(IB6CR)

(Address = 0x0086)

(IB7CR)

(Address = 0x0087)

Bit(s)

Value

Description

7:6

Fifteen wait states for accesses in this bank.

Seven wait states for accesses in this bank.

Three wait states for accesses in this bank.

One wait state for accesses in this bank.

5:4

The Ix signal is an I/O chip select.

The Ix signal is an I/O read strobe.

The Ix signal is an I/O write strobe.

The Ix signal is an I/O data (read or write) strobe.

Writes are not allowed to this bank. Transactions are normal in every other way;
only the write strobe is inhibited.

Writes are allowed to this bank.

Active-Low Ix signal.

Inverted (active-High) Ix.

Normal I/O Transaction timing.

Shorten read strobe by one clock cycle. Transaction length remains the same.

Use I/O bus if enabled.

Always use memory data bus.

Appendix B Rabbit 3000 Revisions

299

B.1.12 Short Chip Select Timing for Writes

The Rabbit 3000 provided the ability to produce shorter chip select strobes for reads when
in a reduced-speed mode. A new feature has been added to produce short chip select
strobes for writes as well, and can be controlled by the GPCSR register.

The new control bit for the short chip selects are listed in Table B-22.

NOTE:

Bit 3 was always written with zero in the original Rabbit 3000 chip.

Table B-22. Global Power Save Control Register

Global Power Save Control Register

(GPSCR)

(Address = 0x000D)

Bit(s)

Value

Description

7:5

000

Self-timed chip selects are disabled.

001

This bit combination is reserved and should not be used.

010

This bit combination is reserved and should not be used.

011

This bit combination is reserved and should not be used.

100

296 ns self-timed chip selects (192 ns best case, 457 ns worst case).

101

234 ns self-timed chip selects (151 ns best case, 360 ns worst case).

110

171 ns self-timed chip selects (111 ns best case, 264 ns worst case).

111

109 ns self-timed chip selects (71 ns best case, 168 ns worst case).

Normal Chip Select timing for read cycles.

Short Chip Select timing for read cycles (not available in full speed).

Normal Chip Select timing for write cycles

Short Chip Select timing for write cycles (not available in full speed).

2:0

000

The 32 kHz clock divider is disabled.

001

This bit combination is reserved and should not be used.

010

This bit combination is reserved and should not be used.

011

This bit combination is reserved and should not be used.

100

32 kHz oscillator divided by two (16.384 kHz).

101

32 kHz oscillator divided by four (8.192 kHz).

110

32 kHz oscillator divided by eight (4.096 kHz).

111

32 kHz oscillator divided by sixteen (2.048 kHz).

300

Rabbit 3000 Microprocessor User’s Manual

B.1.12.1 Clock Select and Power Save Modes

Table B-24 outlines the power save modes available in the Rabbit 3000A. The GCSR is
shown in Table B-23 for reference.

Table B-23. Global Control/Status Register

Global Control/Status Register

(GCSR)

(Address = 0x00)

Bit(s)

Value

Description

7:6

(rd-only)

No reset or watchdog timer time-out since the last read.

The watchdog timer timed out. These bits are cleared by a read of this
register.

This bit combination is not possible.

Reset occurred. These bits are cleared by a read of this register.

No effect on the periodic interrupt. This bit will always be read as zero.

Force a periodic interrupt to be pending.

4:2

xxx

See table below for decode of this field.

1:0

Periodic interrupts are disabled.

Periodic interrupts use Interrupt Priority 1.

Periodic interrupts use Interrupt Priority 2.

Periodic interrupts use Interrupt Priority 3.

Table B-24. Clock Select Field of GCSR

Clock Select

Bits 4:2 GCSR

CPU Clock

Peripheral

Clock

Main

Oscillator

Power-Save CS

if Enabled by

GPSCR

000

osc/8

short CS option

001

osc/8

osc

short CS option

010

osc

none

011

osc/2

short CS option

100

32 kHz or fraction

self-timed option

short CS option

101

32 kHz or fraction

32KHz or fraction

off

self-timed option

short CS option

110

osc/4

short CS option

111

osc/6

short CS option

302

Rabbit 3000 Microprocessor User’s Manual

Figure B-4. Short Chip Select Timing: CLK/6, Read Operation

Figure B-5. Short Chip Select Timing: CLK/4, Read Operation

o s c illa t o r

A D D R

D A T A

T 1

T 2

V a l i d

/ O E x

/ C S x

c lo c k

d iv i de - by - 6 m o de

oscillato r

ADDR

DATA

Valid

/OEx

/CSx

clock

divide-by-4 mode

304

Rabbit 3000 Microprocessor User’s Manual

When operating from the 32 kHz oscillator, the same options are available, but the timing
is somewhat different. This is illustrated in the diagrams below for the four different cases.
In these case the chip selects are one clock cycle (of the 32 kHz clock) long.

Figure B-7. Short Chip Select Timing: 2 kHz, Read Operation

Figure B-8. Short Chip Select Timing: 4 kHz, Read Operation

32KHz

ADDR

DATA

Valid

MEMOExB

MEMCSxB

clock

2KHz ope ratio n

/OEx

/CSx

2 kHz ope ratio n

32 kHz

ADDR

DATA

Valid

/OEx

/CSx

clock

4 kHz operation

Appendix B Rabbit 3000 Revisions

305

Figure B-9. Short Chip Select Timing: 8 kHz, Read Operation

Figure B-10. Short Chip Select Timing: 16 kHz, Read Operation

32 kHz

ADD R

DAT A

Valid

/O Ex

/CSx

clock

8 kHz ope ratio n

32 kHz

ADD R

DAT A

Valid

/O Ex

/CSx

clock

16 kHz ope ratio n

308

Rabbit 3000 Microprocessor User’s Manual

Figure B-13. Short Chip Select Timing: CLK/6, Write Operation

Figure B-14. Short Chip Select Timing: CLK/4, Write Operation

oscillator

ADDR

DATA

TWA

Valid

/WEx

/CSx

clock

divide-by-6 mode

o s c illa t o r

A D D R

D A T A

T 1

T W A

V a l i d

/ W E x

/ C S x

c lo c k

d iv i de - by - 4 m o de

T 2

310

Rabbit 3000 Microprocessor User’s Manual

The timing diagrams below illustrate the actual timing for the 32KHz cases of write
cycles. In these cases the chip selects are active for one clock cycle before and one clock
cycle after the trailing edge of the write signal.

Figure B-16. Short Chip Select Timing: 2 kHz, Write Operation

Figure B-17. Short Chip Select Timing: 4 kHz, Write Operation

32KHz

ADDR

DATA

TWA

Valid

MEMWExB

MEMCSxB

clock

2KHz operation

/WEx

/CSx

2 kHz operation

32 kHz

ADDR

DATA

TWA

Valid

/WEx

/CSx

clock

4 kHz operation

Appendix B Rabbit 3000 Revisions

311

Figure B-18. Short Chip Select Timing: 8 kHz, Write Operation

Figure B-19. Short Chip Select Timing: 16 kHz, Write Operation

32 kHz

ADDR

DATA

TWA

Valid

/WEx

/CSx

clock

8 kHz operation

32 kHz

ADDR

DATA

TWA

Valid

/WEx

/CSx

clock

16 kHz operation

Appendix B Rabbit 3000 Revisions

313

B.1.13 Pulse Width Modulator Improvements

Several new features have been added to the pulse width modulator. First, a new PWM
interrupt can be set up to be requested on every PWM cycle, every other cycle, every
fourth cycle, or every eighth cycle. The setup for this interrupt is done in the PWL0R and
PWL1R registers, listed in Table B-25 and Table B-26.

Options are available to suppress the PWM output for seven-of-eight, three-of-four and
one-of-two iterations of the PWM counter The one-of-eight option works nicely with R/C
servos, which require a 1 ms to 2 ms pulse width and a 20 ms period. This option gives the
full resolution for the pulse width while still meeting the period requirements. The one-of-
four and one-of-two options can be used to create more virtual PWM channels using soft-
ware to multiplex the PWM outputs. There is a separate option to only generate an inter-
rupt during the active iteration of the PWM count. The timing is shown below.

Figure B-21. PWM Interrupt and Output Timing

iteration

1/4 out put

1/8 out put

1/2 out put

1/8 interrupt

1/4 interrupt

1/2 interrupt

314

Rabbit 3000 Microprocessor User’s Manual

Table B-25. PWM LSB 0 Register

PWM LSB 0 Register

(PWL0R)

(Address = 0x0088)

Bit(s)

Value

Description

7:6

write

The least significant two bits for the Pulse Width Modulator count are stored.

5:4

Normal PWM operation.

Suppress PWM output seven out of eight iterations of PWM counter.

Suppress PWM output three out of four iterations of PWM counter.

Suppress PWM output one out of two iterations of PWM counter.

This bit is ignored and should be written with zero.

2:1

Pulse Width Modulator interrupts are disabled.

Pulse Width Modulator interrupts use Interrupt Priority 1.

Pulse Width Modulator interrupts use Interrupt Priority 2.

Pulse Width Modulator interrupts use Interrupt Priority 3.

PWM output High for single block.

Spread PWM output throughout the cycle.

Table B-26. PWM LSB 1 Register

PWM LSB 1 Register

(PWL1R)

(Address = 0x008A)

Bit(s)

Value

Description

7:6

write

The least significant two bits for the Pulse Width Modulator count are stored.

5:4

Normal PWM operation.

Suppress PWM output seven out of eight iterations of PWM counter.

Suppress PWM output three out of four iterations of PWM counter.

Suppress PWM output one out of two iterations of PWM counter.

This bit is ignored and should be written with zero.

2:1

Normal PWM interrupt operation.

Suppress PWM interrupts seven out of eight iterations of PWM counter.

Suppress PWM interrupts three out of four iterations of PWM counter.

Suppress PWM interrupts one out of two iterations of PWM counter.

PWM output High for single block.

Spread PWM output throughout the cycle.

316

Rabbit 3000 Microprocessor User’s Manual

B.1.14 Quadrature Decoder Improvements

The Quadrature Decoder counters can now be expanded to 10 bits instead of 8 bits. This is
controlled by bit 5 in QDCR, listed in Table B-28. The additional two bits can be read in the
QDCxHR registers, listed in Table B-29. Reading the lower 8 bits of the Quadrature Decoder
latches the upper 2 bits, which can then be read at any time afterwards. The latch is cleared
when the upper 2 bits are read, and subsequent reads of these upper two bits will return the
current counter value until they are latched again by another read of the lower 8 bits.

NOTE:

Bit 5 of QDCR was always written with a zero in the original Rabbit 3000 chip.

Table B-28. Quadrature Decoder Control Register

Quadrature Decoder Control Register

(QDCR)

(Address = 0x0091)

Bit(s)

Value

Description

7:6

Disable Quadrature Decoder 2 inputs. Writing a new value to these bits will not
cause Quadrature Decoder 2 to increment or decrement.

This bit combination is reserved and should not be used.

Quadrature Decoder 2 inputs from Port F bits 3 and 2.

Quadrature Decoder 2 inputs from Port F bits 7 and 6.

Eight bit quadrature decoder counters.

Ten bit quadrature decoder counters.

This bit is reserved and should be written as zero.

3:2

Disable Quadrature Decoder 1 inputs. Writing a new value to these bits will not
cause Quadrature Decoder 1 to increment or decrement.

This bit combination is reserved and should not be used.

Quadrature Decoder 1 inputs from Port F bits 1 and 0.

Quadrature Decoder 1 inputs from Port F bits 5 and 4.

1:0

Quadrature Decoder interrupts are disabled.

Quadrature Decoder interrupt use Interrupt Priority 1.

Quadrature Decoder interrupt use Interrupt Priority 2.

Quadrature Decoder interrupt use Interrupt Priority 3.

Table B-29. Quadrature Decoder Count High Register

Quadrature Decoder Count High Register

(QDC1HR)

(Address = 0x0095)

(QDC2HR)

(Address = 0x0097)

Bit(s)

Value

Description

7:2

read

These bits are reserved and will always read as zeros.

1:0

read

The current value of bits 9-8 of the Quadrature Decoder counter is reported.

Appendix B Rabbit 3000 Revisions

317

Figure B-22. Quadrature Decode, 8-bit and 10-bit Counter Timing

Cnt (8 bit)

Interrupt

I input

Q input

Cnt (10 bit)

000

001

002

003

004

005

006

007

008

007

006

005

004

003

002

001

000

3FF

Appendix C System/User Mode

319

PPENDIX

C. S

YSTEM

SER

ODE

The Rabbit 3000A is the first Rabbit microprocessor to incorporate a “system/user mode.”
The purpose of the System/User mode is to provide two tiers of control in the CPU:

sys-

tem

, which provides full access to all processor resources; and

user

, a more restricted

mode.

Table C-1 describes the essential differences between the System mode and the User
mode. The System mode is essentially the same as the normal operation of the Rabbit
3000 and earlier processors.

The main intent of the System/User mode is to protect critical code (for example, code that
performs remote firmware updates), data, and the current processor state (memory setup,
peripheral control, etc.) from inadvertent changes by the user’s standard code. By remov-
ing access to the processor’s I/O registers and preventing memory writes to critical
regions, the user’s code can run without the danger of locking up the processor to the point
where it cannot be restarted remotely and/or new code uploaded.

Table C-1. Differences Between System and User Modes

System Mode

User Mode

All peripherals accessible.

No peripherals accessible by default.

All processor control registers available.

No processor control registers available.

All interrupt priorities available.

Interrupt Priority 3 not allowed.

IDET opcode has no effect.

IDET opcode causes Priority 3 “system mode
violation” interrupt.

No write protection when 0x00 is written to
WPCR (write protection in User mode only)

Write to protected segment causes Priority 3
“write protection violation” interrupt.

Easy to enter user mode (SETUSR opcode).

Difficult to enter system mode (requires
interrupt, SYSCALL, or RST opcode).

320

Rabbit 3000 Microprocessor User’s Manual

C.1 System/User Mode Opcodes

Seven new opcodes have been added to support the System/User mode, and are listed in
Table C-2. All but IDET are placed in previously empty opcode table assignments. IDET
shares the value of

LD E,E

in the opcode table, and will perform that operation when the

System/User mode is disabled, or when it is enabled and in the System mode. In addition,
if the

ALTD

prefix appears before the opcode,

LD E’,E

is always executed instead.

The processor keeps a one-byte stack (called the SU register) that is analogous to the IP
register that keeps track of the interrupt priority. Every time

SETUSR

is executed (to enter

the User mode), or an interrupt occurs, or

SYSCALL

RST

is executed (to enter the Sys-

tem mode), the current mode is pushed onto the SU register. When a

SURES

is executed,

the previous mode is popped off the SU register.

The effects of each opcode are:

•

The

SETUSR

opcode puts the processor into the User mode by pushing the correct value

into the SU register.

•

PUSH SU

and

POP SU

push and pop the single-byte SU register on/off the SP stack.

•

SURES

pops the current processor mode off the SU register, returning it to the previous

mode.

•

IDET

causes an interrupt if executed in the User mode, and does nothing in the System

mode.

•

RDMODE

returns the current mode in the carry flag (0 for System mode, 1 for User mode).

•

SYSCALL

is essentially a new

RST

opcode, and was added to allow User mode access to

the System mode without using one of the existing

RST

opcodes. It will put the processor

into the System mode and execute code in the corresponding interrupt-vector table entry.

Table C-2. New System/User Mode Opcodes

Instruction

Bytes

clk

S Z V C

Operation

Priv

SETUSR

- SU = {SU[5:0], 0x01}

Yes

PUSH SU

- (SP-1) = SU; SP = SP - 1

Yes

POP SU

- SU = (SP); SP = SP + 1

Yes

SURES

- SU = {SU[1:0], SU[7:2]}

Yes

IDET

Performs

LD E,E

, but if

(EDMF && SU[0]) then the System
Violation interrupt flag is set; if ALTD
appears before it always does

LD E’,E

RDMODE

* CF = SU[0]

Yes

SYSCALL

SP = SP - 2; PC = {R,v} where
v = SYSCALL offset

Appendix C System/User Mode

321

C.2 System/User Mode Registers

Table C-3 lists the new I/O registers added to support the System/User mode.

The Enable Dual Mode Register (EDMR) is used to enable and disable the System/User
mode. All other I/O registers listed in the table are “User mode enable” registers for each
peripheral. On startup, User mode access is not allowed to all the peripherals (all writes to
I/O registers for that peripheral are ignored), but can be enabled by writing to the appropri-
ate register. Note that User mode writes to all other I/O registers are always ignored.

Table C-3. System/User Mode I/O Registers

Register Name

Mnemonic

I/O

Address

R/W

Reset

Enable Dual-Mode Register

EDMR

0x0420

00000000

Real Time Clock User Enable Register

RTUER

0x0300

00000000

Slave Port User Enable Register

SPUER

0x0320

00000000

Parallel Port A User Enable Register

PAUER

0x0330

00000000

Parallel Port B User Enable Register

PBUER

0x0340

00000000

Parallel Port C User Enable Register

PCUER

0x0350

00000000

Parallel Port D User Enable Register

PDUER

0x0360

00000000

Parallel Port E User Enable Register

PEUER

0x0370

00000000

Parallel Port F User Enable Register

PFUER

0x0338

00000000

Parallel Port G User Enable Register

PGUER

0x0348

00000000

Input Capture User Enable Register

ICUER

0x0358

00000000

I/O Bank User Enable Register

IBUER

0x0380

00000000

PWM User Enable Register

PWUER

0x0388

00000000

Quad Decode User Enable Register

QDUER

0x0390

00000000

External Interrupt User Enable Register

IUER

0x0398

00000000

Timer A User Enable Register

TAUER

0x03A0

00000000

Timer B User Enable Register

TBUER

0x03B0

00000000

Serial Port A User Enable Register

SAUER

0x03C0

00000000

Serial Port B User Enable Register

SBUER

0x3D0

00000000

Serial Port C User Enable Register

SCUER

0x3E0

00000000

Serial Port D User Enable Register

SDUER

0x3F0

00000000

Serial Port E User Enable Register

SEUER

0x03C8

00000000

Serial Port F User Enable Register

SFUER

0x3D8

00000000

322

Rabbit 3000 Microprocessor User’s Manual

The I/O banks on Port E (enabled for the User mode by IBUER) have a slightly different
operation in the User mode. Disabling user access to a given I/O bank not only causes
writes to the corresponding IBxCR register to be ignored in the User mode, but also inhib-
its the strobe associated with that I/O bank.

Access to the internal I/O registers listed in Table C-4 is always denied in the User mode.

Table C-4. I/O Addresses Inaccessible in User Mode

Register Name

Mnemonic

I/O Address

Global Control/Status Register

GCSR

0x0000

Watchdog Timer Control Register

WDTCR

0x0008

Watchdog Timer Test Register

WDTTR

0x0009

Global Clock Modulator 0 Register

GCM0R

0x000A

Global Clock Modulator 1 Register

GCM1R

0x000B

Secondary Watchdog Timer Register

* These registers are only available on the Rabbit 3000A.

SWDTR

0x000C

Global Power Save Control Register

GPSCR

0x000D

Global Output Control Register

GOCR

0x000E

Global Clock Double Register

GCDR

0x000F

MMU Instruction/Data Register

MMIDR

0x0010

Stack Segment Register

STACKSEG

0x0011

Data Segment Register

DATASEG

0x0012

Segment Size Register

SEGSIZE

0x0013

Memory Bank 0 Control Register

MB0CR

0x0014

Memory Bank 1 Control Register

MB1CR

0x0015

Memory Bank 2 Control Register

MB2CR

0x0016

Memory Bank 3 Control Register

MB3CR

0x0017

MMU Expanded Code Register

MECR

0x0018

Memory Timing Control Register

MTCR

0x0019

Breakpoint/Debug Control Register

BDCR

0x001C

User Enable registers

0x03xx

Memory Protection registers

0x04xx

Appendix C System/User Mode

323

C.3 Interrupts

When enabled for User mode access, a peripheral interrupt (if it is capable of generating
an interrupt) can only be requested at Interrupt Priority Level -2 or -1. Interrupts (and

RST

and

SYSCALL

) all enter the System mode automatically. There will be times, however, that

an interrupt should be handled in the User mode. The solution to this is for the System
mode interrupt vector to reenter User mode before calling the User mode interrupt handler.
An example of both system and user interrupt handling is shown in Figure C-1.

Figure C-1. Interrupt Handing in System/User Mode

Some sample code for both System mode interrupts and User mode interrupts is shown
below.

system_isr: ; jumped to from interrupt vector table

... handle interrupt ...

sures ; reenter previous mode

ret

user_isr: ; jumped to from interrupt vector table

push su ; preserve current SU stack

setusr ; enter user mode

... handle interrupt ...

pop su ; restore previous SU stack

sures ; reenter previous mode

ret

INTERRUPT UNDER SYSTEM CONTROL

Application code (user)

ISR (system)

Application code (user)

INTERRUPT UNDER USER CONTROL

Application code (user)

Application ISR (user)

Application code (user)

ISR (system)

Appendix C System/User Mode

325

Table C-5. Interrupts—Priority and Action to Clear Requests

Priority

Interrupt Source

Action required to clear the interrupt

Highest

System Mode Violation

Automatically cleared by the interrupt acknowledge.

Stack Limit Violation

Automatically cleared by the interrupt acknowledge.

Write Protection Violation

Automatically cleared by the interrupt acknowledge.

Secondary Watchdog

Restart the Secondary Watchdog by writing to WDTCR.

External 1

Automatically cleared by the interrupt acknowledge.

External 0

Automatically cleared by the interrupt acknowledge.

Periodic (2 kHz)

Read the status from the GCSR.

Quadrature Decoder

Read the status from the QDSR.

Timer B

Read the status from the TBSR.

Timer A

Read the status from the TASR.

Input Capture

Read the status from the ICCSR.

PWM

Write any PWM register.

Slave Port

Rd: Read the data from the SPD0R, SPD1R or SPD2R.

Wr: Write data to the SPD0R, SPD1R, SPD2R or write a
dummy byte to the SPSR.

Serial Port E

Rx: Read the data from the SEDR or SEAR.

Tx: Write data to the SEDR, SEAR, SELR or write a dummy
byte to the SESR.

Serial Port F

Rx: Read the data from the SFDR or SFAR.

Tx: Write data to the SFDR, SFAR, SFLR or write a dummy
byte to the SFSR.

Serial Port A

Rx: Read the data from the SADR or SAAR.

Tx: Write data to the SADR, SAAR, SALR or write a dummy
byte to the SASR.

Serial Port B

Rx: Read the data from the SBDR or SBAR.

Tx: Write data to the SBDR, SBAR, SBLR or write a dummy
byte to the SBSR.

Serial Port C

Rx: Read the data from the SCDR or SCAR.

Tx: Write data to the SCDR, SCAR, SCLR or write a dummy
byte to the SCSR.

Lowest

Serial Port D

Rx: Read the data from the SDDR or SDAR.

Tx: Write data to the SDDR, SDAR, SDLR or write a dummy
byte to the SDSR.

328

Rabbit 3000 Microprocessor User’s Manual

C.4.3 Complete Operating System

This section describes a “full” use of the System/User mode—separating all common
functions into a System mode “operating system” while letting the application-specific
code run in the User mode.By default, the System mode handles all peripherals and inter-
rupts, as well as high-level interfaces such as a flash file system. However, the processor
will be running the application code in the User mode most of the time.

The application code can request direct access to a peripheral and/or interrupt from the
System mode. If allowed, the System mode can create an interrupt vector as described in
Section C.3 that will execute the user code interrupt handler.

When the application code wants to perform an action that is controlled by the System
mode, it can request the particular action by loading the appropriate value into HL and
executing

SYSCALL

. This requires generating a list of all the actions that the application

code would want to do, assigning values to each action, and implementing a

SYSCALL

handler in the System mode that parses the value passed to it and calls the appropriate
function.

Write protection should be enabled (User mode only) for all blocks containing system
code and data as well as any critical memory regions.

If any critical interrupts occur (stack limit violation, system mode violation, write protec-
tion violation), the System mode handlers can perform any of a number of operations:
restart the application code, signal another device, halt operation, and so on.

An overview of this level of operation is shown in Figure C-4.

Figure C-4. System/User Mode Setup for Operating System

Return from interrupts

Interrupts,

SYSCALL, RST

System Mode

User Mode

Application

code

User-defined

interrupts

Interrupt

handlers

Flash file

system

SYSCALL

handler

Appendix D Rabbit 3000A Internal I/O Registers

329

PPENDIX

ABBIT

3000A I

NTERNAL

I/O R

EGISTERS

Table D-1 provides a list of all the Rabbit 3000A internal I/O registers.

Table D-1. Rabbit 3000A Internal I/O Registers

Register Name

Mnemonic

I/O Address

R/W

Reset

Global Control/Status Register

GCSR

0x0000

R/W

11000000

Real Time Clock Control Register

RTCCR

0x0001

00000000

Real Time Clock Byte 0 Register

RTC0R

0x0002

R/W

xxxxxxxx

Real Time Clock Byte 1 Register

RTC1R

0x0003

xxxxxxxx

Real Time Clock Byte 2 Register

RTC2R

0x0004

xxxxxxxx

Real Time Clock Byte 3 Register

RTC3R

0x0005

xxxxxxxx

Real Time Clock Byte 4 Register

RTC4R

0x0006

xxxxxxxx

Real Time Clock Byte 5 Register

RTC5R

0x0007

xxxxxxxx

Watchdog Timer Control Register

WDTCR

0x0008

00000000

Watchdog Timer Test Register

WDTTR

0x0009

00000000

Global Clock Modulator 0 Register

GCM0R

0x000A

00000000

Global Clock Modulator 1 Register

GCM1R

0x000B

00000000

Secondary Watchdog Timer Register

SWDTR

0x000C

11111111

Global Power Save Control Register

GPSCR

0x000D

00000000

Global Output Control Register

GOCR

0x000E

00000000

Global Clock Double Register

GCDR

0x000F

00000000

Global ROM Configuration Register

GROM

0x002C

0xx00000

Global RAM Configuration Register

GRAM

0x002D

0xx00000

Global CPU Configuration Register

GCPU

0x002E

0xx00001

Global Revision Register

GREV

0x002F

0xx00001

MMU Instruction/Data Register

MMIDR

0x0010

R/W

00000000

330

Rabbit 3000 Microprocessor User’s Manual

Memory Bank 0 Control Register

MB0CR

0x0014

00001000

Memory Bank 1 Control Register

MB1CR

0x0015

xxxxxxxx

Memory Bank 2 Control Register

MB2CR

0x0016

xxxxxxxx

Memory Bank 3 Control Register

MB3CR

0x0017

xxxxxxxx

MMU Expanded Code Register

MECR

0x0018

R/W

00000000

Memory Timing Control Register

MTCR

0x0019

00000000

Breakpoint/Debug Control Register

BDCR

0x001C

00000000

RAM Segment Register

RAMSR

0x0448

00000000

Write Protect Control Register

WPCR

0x0440

00000000

Stack Limit Control Register

STKCR

0x0444

00000000

Stack Low Limit Register

STKLLR

0x0445

xxxxxxxx

Stack High Limit Register

STKHLR

0x0446

xxxxxxxx

Write Protect Low Register

WPLR

0x0460

00000000

Write Protect High Register

WPHR

0x0461

00000000

Write Protect Segment A Register

WPSAR

0x0480

00000000

Write Protect Segment A Low Register

WPSALR

0x0481

00000000

Write Protect Segment A High Register

WPSAHR

0x0482

00000000

Write Protect Segment B Register

WPSBR

0x0484

00000000

Write Protect Segment B Low Register

WPSBLR

0x0485

00000000

Write Protect Segment B High Register

WPSBHR

0x0486

00000000

Real Time Clock User Enable Register

RTUER

0x0300

00000000

Slave Port User Enable Register

SPUER

0x0320

00000000

Parallel Port A User Enable Register

PAUER

0x0330

00000000

Parallel Port F User Enable Register

PFUER

0x0338

00000000

Parallel Port B User Enable Register

PBUER

0x0340

00000000

Parallel Port G User Enable Register

PGUER

0x0348

00000000

Parallel Port C User Enable Register

PCUER

0x0350

00000000

Input Capture User Enable Register

ICUER

0x0358

00000000

Parallel Port D User Enable Register

PDUER

0x0360

00000000

Parallel Port E User Enable Register

PEUER

0x0370

00000000

Table D-1. Rabbit 3000A Internal I/O Registers (continued)

Register Name

Mnemonic

I/O Address

R/W

Reset

Appendix D Rabbit 3000A Internal I/O Registers

331

I/O Bank User Enable Register

IBUER

0x0380

00000000

PWM User Enable Register

PWUER

0x0388

00000000

Quad Decode User Enable Register

QDUER

0x0390

00000000

External Interrupt User Enable Register

IUER

0x0398

00000000

Timer A User Enable Register

TAUER

0x03A0

00000000

Timer B User Enable Register

TBUER

0x03B0

00000000

Serial Port A User Enable Register

SAUER

0x03C0

00000000

Serial Port E User Enable Register

SEUER

0x03C8

00000000

Serial Port B User Enable Register

SBUER

0x03D0

00000000

Serial Port F User Enable Register

SFUER

0x03D8

00000000

Serial Port C User Enable Register

SCUER

0x03E0

00000000

Serial Port D User Enable Register

SDUER

0x03F0

00000000

Enable Dual Mode Register

EDMR

0x0420

00000000

Slave Port Data 0 Register

SPD0R

0x0020

R/W

xxxxxxxx

Slave Port Data 1 Register

SPD1R

0x0021

R/W

xxxxxxxx

Slave Port Data 2 Register

SPD2R

0x0022

R/W

xxxxxxxx

Slave Port Status Register

SPSR

0x0023

00000000

Slave Port Control Register

SPCR

0x0024

R/W

0xx00000

Port A Data Register

PADR

0x0030

R/W

xxxxxxxx

Port B Data Register

PBDR

0x0040

R/W

00xxxxxx

Port B Data Direction Register

PBDDR

0x0047

11000000

Port C Data Register

PCDR

0x0050

R/W

x0x1x1x1

Port C Function Register

PCFR

0x0055

x0x0x0x0

Port D Data Register

PDDR

0x0060

R/W

xxxxxxxx

Port D Control Register

PDCR

0x0064

xx00xx00

Port D Function Register

PDFR

0x0065

xxxxxxxx

Port D Drive Control Register

PDDCR

0x0066

xxxxxxxx

Port D Data Direction Register

PDDDR

0x0067

00000000

Port D Bit 0 Register

PDB0R

0x0068

xxxxxxxx

Port D Bit 1 Register

PDB1R

0x0069

xxxxxxxx

Table D-1. Rabbit 3000A Internal I/O Registers (continued)

Register Name

Mnemonic

I/O Address

R/W

Reset

332

Rabbit 3000 Microprocessor User’s Manual

Port D Bit 2 Register

PDB2R

0x006A

xxxxxxxx

Port D Bit 3 Register

PDB3R

0x006B

xxxxxxxx

Port D Bit 4 Register

PDB4R

0x006C

xxxxxxxx

Port D Bit 5 Register

PDB5R

0x006D

xxxxxxxx

Port D Bit 6 Register

PDB6R

0x006E

xxxxxxxx

Port D Bit 7 Register

PDB7R

0x006F

xxxxxxxx

Port E Data Register

PEDR

0x0070

R/W

xxxxxxxx

Port E Control Register

PECR

0x0074

xx00xx00

Port E Function Register

PEFR

0x0075

00000000

Port E Data Direction Register

PEDDR

0x0077

00000000

Port E Bit 0 Register

PEB0R

0x0078

xxxxxxxx

Port E Bit 1 Register

PEB1R

0x0079

xxxxxxxx

Port E Bit 2 Register

PEB2R

0x007A

xxxxxxxx

Port E Bit 3 Register

PEB3R

0x007B

xxxxxxxx

Port E Bit 4 Register

PEB4R

0x007C

xxxxxxxx

Port E Bit 5 Register

PEB5R

0x007D

xxxxxxxx

Port E Bit 6 Register

PEB6R

0x007E

xxxxxxxx

Port E Bit 7 Register

PEB7R

0x007F

xxxxxxxx

Port F Data Register

PFDR

0x0038

R/W

xxxxxxxx

Port F Control Register

PFCR

0x003C

xx00xx00

Port F Function Register

PFFR

0x003D

xxxxxxxx

Port F Drive Control Register

PFDCR

0x003E

xxxxxxxx

Port F Data Direction Register

PFDDR

0x003F

00000000

Port G Data Register

PGDR

0x0048

R/W

xxxxxxxx

Port G Control Register

PGCR

0x004C

xx00xx00

Port G Function Register

PGFR

0x004D

xxxxxxxx

Port G Drive Control Register

PGDCR

0x004E

xxxxxxxx

Port G Data Direction Register

PGDDR

0x004F

00000000

I/O Bank 0 Control Register

IB0CR

0x0080

00000000

I/O Bank 1 Control Register

IB1CR

0x0081

00000000

Table D-1. Rabbit 3000A Internal I/O Registers (continued)

Register Name

Mnemonic

I/O Address

R/W

Reset

Appendix D Rabbit 3000A Internal I/O Registers

333

I/O Bank 2 Control Register

IB2CR

0x0082

00000000

I/O Bank 3 Control Register

IB3CR

0x0083

00000000

I/O Bank 4 Control Register

IB4CR

0x0084

00000000

I/O Bank 5 Control Register

IB5CR

0x0085

00000000

I/O Bank 6 Control Register

IB6CR

0x0086

00000000

I/O Bank 7 Control Register

IB7CR

0x0087

00000000

PWM LSB 0 Register

PWL0R

0x0088

xxxxx00x

PWM MSB 0 Register

PWM0R

0x0089

xxxxxxxx

PWM LSB 1 Register

PWL1R

0x008A

xxxxx00x

PWM MSB 1 Register

PWM1R

0x008B

xxxxxxxx

PWM LSB 2 Register

PWL2R

0x008C

xxxxx00x

PWM MSB 2 Register

PWM2R

0x008D

xxxxxxxx

PWM LSB 3 Register

PWL3R

0x008E

xxxxx00x

PWM MSB 3 Register

PWM3R

0x008F

xxxxxxxx

Input Capture Ctrl/Status Register

ICCSR

0x0056

R/W

00000000

Input Capture Control Register

ICCR

0x0057

xxxxxx00

Input Capture Trigger 1 Register

ICT1R

0x0058

00000000

Input Capture Source 1 Register

ICS1R

0x0059

xxxxxxxx

Input Capture LSB 1 Register

ICL1R

0x005A

xxxxxxxx

Input Capture MSB 1 Register

ICM1R

0x005B

xxxxxxxx

Input Capture Trigger 2 Register

ICT2R

0x005C

00000000

Input Capture Source 2 Register

ICS2R

0x005D

xxxxxxxx

Input Capture LSB 2 Register

ICL2R

0x005E

xxxxxxxx

Input Capture MSB 2 Register

ICM2R

0x005F

xxxxxxxx

Quad Decode Ctrl/Status Register

QDCSR

0x0090

R/W

xxxxxxxx

Quad Decode Control Register

QDCR

0x0091

00000000

Quad Decode Count 1 Register

QDC1R

0x0094

xxxxxxxx

Quad Decode Count1 High Register

QDC1HR

0x0095

xxxxxxxx

Quad Decode Count 2 Register

QDC2R

0x0096

xxxxxxxx

Quad Decode Count 2 High Register

QDC2HR

0x0097

xxxxxxxx

Table D-1. Rabbit 3000A Internal I/O Registers (continued)

Register Name

Mnemonic

I/O Address

R/W

Reset

334

Rabbit 3000 Microprocessor User’s Manual

Interrupt 0 Control Register

I0CR

0x0098

xx000000

Interrupt 1 Control Register

I1CR

0x0099

xx000000

Timer A Control/Status Register

TACSR

0x00A0

R/W

00000000

Timer A Prescale Register

TAPR

0x00A1

xxxxxxx1

Timer A Time Constant 1 Register

TAT1R

0x00A3

xxxxxxxx

Timer A Control Register

TACR

0x00A4

00000000

Timer A Time Constant 2 Register

TAT2R

0x00A5

xxxxxxxx

Timer A Time Constant 8 Register

TAT8R

0x00A6

xxxxxxxx

Timer A Time Constant 3 Register

TAT3R

0x00A7

xxxxxxxx

Timer A Time Constant 9 Register

TAT9R

0x00A8

xxxxxxxx

Timer A Time Constant 4 Register

TAT4R

0x00A9

xxxxxxxx

Timer A Time Constant 10 Register

TAT10R

0x00AA

xxxxxxxx

Timer A Time Constant 5 Register

TAT5R

0x00AB

xxxxxxxx

Timer A Time Constant 6 Register

TAT6R

0x00AD

xxxxxxxx

Timer A Time Constant 7 Register

TAT7R

0x00AF

xxxxxxxx

Timer B Control/Status Register

TBCSR

0x00B0

R/W

xxxxx000

Timer B Control Register

TBCR

0x00B1

xxxx0000

Timer B MSB 1 Register

TBM1R

0x00B2

xxxxxxxx

Timer B LSB 1 Register

TBL1R

0x00B3

xxxxxxxx

Timer B MSB 2 Register

TBM2R

0x00B4

xxxxxxxx

Timer B LSB 2 Register

TBL2R

0x00B5

xxxxxxxx

Timer B Count MSB Register

TBCMR

0x00BE

xxxxxxxx

Timer B Count LSB Register

TBCLR

0x00BF

xxxxxxxx

Serial Port A Data Register

SADR

0x00C0

R/W

xxxxxxxx

Serial Port A Address Register

SAAR

0x00C1

xxxxxxxx

Serial Port A Long Stop Register

SALR

0x00C2

xxxxxxxx

Serial Port A Status Register

SASR

0x00C3

0xx00000

Serial Port A Control Register

SACR

0x00C4

xx000000

Serial Port A Extended Register

SAER

0x00C5

00000000

Serial Port B Data Register

SBDR

0x00D0

R/W

xxxxxxxx

Table D-1. Rabbit 3000A Internal I/O Registers (continued)

Register Name

Mnemonic

I/O Address

R/W

Reset

Appendix D Rabbit 3000A Internal I/O Registers

335

Serial Port B Address Register

SBAR

0x00D1

xxxxxxxx

Serial Port B Long Stop Register

SBLR

0x00D2

xxxxxxxx

Serial Port B Status Register

SBSR

0x00D3

0xx00000

Serial Port B Control Register

SBCR

0x00D4

xx000000

Serial Port B Extended Register

SBER

0x00D5

00000000

Serial Port C Data Register

SCDR

0x00E0

R/W

xxxxxxxx

Serial Port C Address Register

SCAR

0x00E1

xxxxxxxx

Serial Port C Long Stop Register

SCLR

0x00E2

xxxxxxxx

Serial Port C Status Register

SCSR

0x00E3

0xx00000

Serial Port C Control Register

SCCR

0x00E4

xx000000

Serial Port C Extended Register

SCER

0x00E5

00000000

Serial Port D Data Register

SDDR

0x00F0

R/W

xxxxxxxx

Serial Port D Address Register

SDAR

0x00F1

xxxxxxxx

Serial Port D Long Stop Register

SDLR

0x00F2

xxxxxxxx

Serial Port D Status Register

SDSR

0x00F3

0xx00000

Serial Port D Control Register

SDCR

0x00F4

xx000000

Serial Port D Extended Register

SDER

0x00F5

00000000

Serial Port E Data Register

SEDR

0x00C8

R/W

xxxxxxxx

Serial Port E Address Register

SEAR

0x00C9

xxxxxxxx

Serial Port E Long Stop Register

SELR

0x00CA

xxxxxxxx

Serial Port E Status Register

SESR

0x00CB

0xx00000

Serial Port E Control Register

SECR

0x00CC

xx000000

Serial Port E Extended Register

SEER

0x00CD

00000000

Serial Port F Data Register

SFDR

0x00D8

R/W

xxxxxxxx

Serial Port F Address Register

SFAR

0x00D9

xxxxxxxx

Serial Port F Long Stop Register

SFLR

0x00DA

xxxxxxxx

Serial Port F Status Register

SFSR

0x00DB

0xx00000

Serial Port F Control Register

SFCR

0x00DC

xx000000

Serial Port F Extended Register

SFER

0x00DD

00000000

Table D-1. Rabbit 3000A Internal I/O Registers (continued)

Register Name

Mnemonic

I/O Address

R/W

Reset