TLIC_PRODUCT_CATALOG-html.html

MANUFACTURING PROCESS TECHNOLOGY OVERVIEW

90 nm

130 nm

0.18 µm

0.25 µm

0.35 µm

>0.40 µm

Logic

CMOS—SOI

CMOS

–

CMOS—general purpose*

CMOS—general purpose

CMOS—low power*

CMOS—low power

SMARTMOS™

–

SMOS9 LV (18V)*

SMOS8 MV (85V)

SMOS7 MV (45V)

SMOS5 HV+ (105V)

SMOS8 LV (18V)

SMOS7 LV (18V)

HVMOS (30V)

SMOS5 LV (18V)

SMOS5MV(45V)

RF/IF Silicon

–

RF CMOS

–

RF BiCMOS (24 GHz)

–

RF BiCMOS—SiGe (50 GHz)

RF BiCMOS—SiGe (47 GHz)

RF BiCMOS—SiGe (120 GHz)

RF BiCMOS—SiGe (75 GHz)

RF/IF III-V

–

GaAs pHEMT

GaAs Emode2

GaAs HBT (InGaP)

* Indicates future/limited availability

CMOS 90 nm

CMOS 130 nm

CMOS 0.18 µm

CMOS 0.25 µm

CMOS 0.35 µm

Technology Node

90 nm

130 nm

0.18 µm

0.25 µm

0.35 µm

Wafer Size

200 mm

Transistor Nodes

3—low power, general

5—low power, general

4—general purpose,

1—general purpose

purpose, high

high performance/SOI (3)

performance/SOI

performance/SOI (3)

Availability

High performance/SOI—Today

Today

General purpose—2005

BEOL

Cu (Low K)

# Metal Layers

5–9

3–6

3–4

# Poly Layers

–

1–2

Gate Density

>450K/mm2

>200K/mm2

>100K/mm2

>50K/mm2

>25K/mm2

Foundry Compatible

–

Static Memory

SRAM, ROM

Nonvolatile Memory

MRAM, eDRAM, Flash,

Flash, EEPROM

–

Flash, EEPROM

EEPROM (emulated)

(emulated)

(true)

Passives

–

Libraries

Applications

High-performance logic, mixed-signal, low-power, embedded solutions

CMOS PROCESS TECHNOLOGY

SMOS9

SMOS8

SMOS7

SMOS5

Technology Node

0.18 µm

0.25 µm

0.35 µm

>0.40 µm

Wafer Size

200 mm

150 mm

Voltage Capability

Low voltage (18V)

Low voltage (20V)

Low voltage (18V)

Mid voltage (80V)

Mid voltage (45V)

High voltage (105V)

Availability

2005

Today

# Metal Layers

–

3 or 4

2 or 3

# Poly Layers

–

1 or 2

Gate Density

–

>25K/mm2

>12K/mm2

>5K/mm2

Stand-alone Memory Modules

SRAM

Embedded Memory Modules

ROM

Power Devices

CMOS, LDMOS, bipolar

Analog Devices

–

Low voltage (2.5V, 5.5V, 7.5V, 20V)

Low voltage (3.3V, 7.5V, 10V, 20V, 45V)

–

Mid voltage (2.5V, 5.0V, 10V, 45V, 80V)

Libraries

Full mixed-signal/analog

design kit

Supports Synthesizable

Processor Core

–

Applications

Power management, motor control, high voltage, switching, regulators, mixed signal/analog

SMARTMOS™ PROCESS TECHNOLOGY

180 nm

0.25 µm

0.35 µm

Analog CMOS

RF CMOS

–

BiCMOS

–

BiCMOS-SiGe

–

Analog CMOS

Technology Node

180 nm

0.25 µm

0.35 µm

Wafer Size

200 mm

–

200 mm

Availability

Today

–

Today

Interconnect

–

AlCu

60 GHz

–

Devices

MOS: 35A (std Vt and low Vt), 50A or 70A DGO MOS,

MOS: 70A (std Vt, n-ch and p-ch),

isolated NMOS, diffused NPN, substrate PNP

substrate PNP

Capacitors

Si cap (8 fF/um2, 4.8 fF/um2 or 3.5 fF/um2),

–

Double poly cap (1 fF/um2),

MIM cap (1.6 fF/um2 or 5 fF/um2)

single poly cap (3.4fF/um2)

Resistors

Si resistor (60 ohm/sq or 375 ohm/sq), poly resistor

–

Si resistors (N-well: 500 ohm/sq or 700 ohm/sq),

(1500 ohm/sq), TaN resistor (50 ohm/sq)

poly resistor (DPA = 80 ohm/sq), (SPA = 63 ohm/sq)

Applications

Mixed signal, ADC, DAC

–

Mixed signal, ADC, DAC

RF CMOS

Technology Node

180 nm

0.25 µm

0.35 µm

Wafer Size

200 mm

–

Availability

Today

Q4 2004

–

Interconnect

AlCu

–

60 GHz

37 GHz

–

Devices

MOS: 35A (std Vt and low Vt), 50A or 70A DGO MOS,

MOS, isolated NMOS, n+ and

–

isolated NMOS with RFMOS model,

p+ VVCs; thick Al inductor

diffused NPN, substrate PNP

Capacitors

Si cap (8 fF/um2, 4.8 fF/um2 or 3.5 fF/um2),

MIM, MOS cap with high

–

MIM cap (1.6 fF/um2 or 5 fF/um2)

linearity implant

Resistors

Si resistor (60 ohm/sq or 375 ohm/sq),

n+ active and poly, p+ poly, high value poly

–

poly resistor (1500 ohm/sq),

TaN resistor (50 ohm/sq)

Voltage-Variable

N and P poly VVC single-ended and

–

Capacitor (VVC)

differential, thick copper inductor

and Inductor

(post passivation)

Applications

Transceiver (LNA, mixer, VCO, synthesizer, TIA)

–

RF/IF SILICON TECHNOLOGY

BiCMOS

Technology Node

180 nm

0.25 µm

0.35 µm

Wafer Size

–

200 mm

Availability

–

Today

Interconnect

–

AlCu

–

24 GHz (npn)

Devices

–

MOS: std, low Vt, naturals,

isolated NMOS; VVCs and diode varactors;

HV CMOS; substrate pnp, thick Al inductor

or thick Cu inductor

Capacitors

–

MIM, DPC, MIMxDPC

Resistors

–

n+ and p+ active and poly,

high-value poly, N-well

Applications

–

BiCMOS - SiGe

Technology Node

180 nm

0.25 µm

0.35 µm

Wafer Size

200 mm

–

200 mm

Availability

Today

–

Today

Interconnect

–

AlCu

50 GHz, 120 GHz

–

46 GHz, 80 GHz

Devices

SiGe:C HBT NPN. MOS: 35A

–

MOS: std, low Vt, naturals, isolated

(std Vt and low Vt), 50A or 70A

NMOS; VVCs and diode varactors;

DGO MOS, isolated NMOS with RFMOS

HV CMOS; substrate pnp, thick

model, diffused NPN, substrate PNP

Al inductor or thick Cu inductor

Capacitors

Si cap (8 fF/um2, 4.8 fF/um2

–

MIM, DPC, MIMxDPC

or 3.5 fF/um2), MIM cap

(1.6 fF/um2 or 5 fF/um2)

Resistors

Si resistor (60 ohm/sq or 375 ohm/sq),

–

n+ and p+ active and poly,

poly resistor (1500 ohm/sq),

high-value poly, N-well

TaN resistor (50 ohm/sq)

Voltage-Variable

N and P poly VVC

–

Capacitor (VVC)

single-ended and differential,

and Inductor

thick copper inductor (post passivation)

Applications

Transceiver (LNA, mixer, VCO, synthesizer, TIA)

–

RF/IF SILICON TECHNOLOGY CONTINUED

Attribute

Emode 2.5A

InGaP HBT2

PHEMT2

HVPHEMT2

IPD1

Wafer Size

150 mm

Gate Length (µ)

0.85

–

0.6

–

Emitter Width (µ)

–

0.6

–

Vth (V)

0.6

–

-1.2

-1

–

fT (GHz)

19 (20% Imax)

23 (Vg=-0.8)

11 (Vg=-0.6)

–

fmax (GHz)

29 (20% Imax)

50–60

–

21 (Vg=-0.6)

–

Operating Voltage (V)

3.2

3.5

–

Resistor

Thin film and epi

Epi

Thin film and epi

Thin film

Capacitor

MIM

Inductor

Au (air bridge)

Substrate Via

–

Availability

Today

Limited

Future Generations

RF/IF III-V GaAs TECHNOLOGY

Technology

Description

Highlighted Features/Specifications

Flip-Chip PBGA Assembly

Production-proven, flip-chip PBGA assembly process includes equipment

Packaging Capability: package size up to 50 mm x 50 mm,

and tooling set, materials list, process recipes and specifications,

BGA ball count 1200+, BGA pitch 0.8 mm to 1.27 mm,

control plans and FMEAs, packaging design guidelines,

die size up to 15 mm x 15 mm, bump count 1700+, bump pitch

development and production process, and knowledge transfer.

200 µm, bump composition Pb97Sn03, Pb95Sn05, Pb37Sn63.

Manufacturing Capability: pick and place directly from wafers to substrate,

speed sort at die attach, capacitor attach, laser mark on back of die,

package lid, no-clean die attach flux.

Electroplated Bumping

Production-proven electroplate wafer-bumping process includes

Bump dia/pitch: 100 µm/150 µm; bond pads: aluminum and pure

Technology

equipment and tooling set, process recipes, materials list,

Cu; bump alloy: high Pb (Pb95Sn05)/eutectic (Pb37Sn63)/low alpha

bump-design guidelines, development and production

Pb/Pb-free; wafer diameters: 100 mm to 200 mm

process knowledge transfer, Freescale documentation,

Enables other applications: integrated passives, wafer-level CSP,

training and support.

sacrificial metal wafer-level burn-in and test process.

Wafer-Level Burn-In

Production-proven WLBT: sacrificial metal technology enables

5-inch and 8-inch processes qualified. Technology transfer includes

and Test: Sacrificial

known good die and lowers total product cost through increased

complete technology documentation and patent coverage, training

Metal Method

yields and simplified process flow. Technology includes sacrificial

and support through qualification, access to valuable patents.

metal circuit design methodology, process technology and equipment

and fixture design and sources.

Wafer-Level Burn-In:

Burn-in and test methodology for die at the wafer level provides

Multiuse contactors. Available for wafers up to 300 mm in diameter.

Direct Contact Method

massive parallel test capabilities and lowers total product cost

through elimination of package-level burn-in and reduction of test time

at probe and final test, increased test yields and simplified process flow;

utilizes a direct contact per die method; provides a robust, full-wafer

contact process; and enables known good die (KGD), SiP and MCM

technologies. Technology includes process technology, equipment and

fixture design and sources, documentation, training and support.

Power QFN Package

A Freescale innovation, the Power QFN (PQFN) is a single or multi-chip

The PQFN offers superior thermal performance and proven solder

option to the HSOP package. The PQFN is available in both standard

joint reliability. The small footprint is JEDEC approved. The PQFN

and custom configurations. Technology includes patents, design and

is a cost-effective packaging alternative for multi-chip applications.

process know-how.

Array QFN Package

The Array QFN developed by Freescale is a lead-frame-based, chip-scale

The Array QFN bridges the gap between standard QFN and MAP BGA

semiconductor package offering low-cost, high-thermal performance

packages by offering a low-cost alternative for 80 to 120 I/O devices.

and high I/O density. The package is a multi-row version of the standard

The I/O density, combined with excellent thermal dissipation capability,

Quad Flat Pack No-Lead (QFN) package. Technology includes patents,

makes the Array QFN an attractive package.

design and process know-how.

QuickTest™ Test

Statistical software solution employs a unique, patented methodology

Three-part architecture includes automated analysis; Web-based,

Time Reduction

to reduce test time 5 percent to 25 percent while maintaining a

real-time reporting accessible anywhere in the world; and data storage.

six-sigma level of quality.

More than 30 million devices have been QuickTested with zero

product returns. Used on digital and mixed-signal semiconductor

products at both probe and final test.

PACKAGING AND TEST TECHNOLOGY

MATERIALS AND EQUIPMENT TECHNOLOGY

Technology

Microprocessors and Microcontrollers

Embedded Memories

Data Converters

Frequency Generation

Peripherals

Power Amplifiers

Power Management

Receivers

Signal Processing

Transmitters

DESIGN IP

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or
service names are the property of their respective owners.
© Freescale Semiconductor, Inc. 2004

Updated May 25, 2004

Technology

Description

Highlighted Features/Specifications

Product Applications

Modeling Software

Research IP

Software databases that model the

Detailed chemical species modeling

Plasma process development, plasma

Databases—Plasma

chemical species formation and

throughout a plasma process.

processing equipment development.

Chemistries

interaction in plasma environments;

currently focused on etch chemistries,

such as CxFx.

Modeling

Research IP

Software program to model

Program handles both standard and

Photolithography research,

Software—Photolithography

photolithographic effects of multiple

EUV modeling; provides rapid 2D

bitcell design.

layer film stacks, photo dose, layout

modeling capability.

shapes, reticle enhancement

technologies, etc.

Equipment

Manufacturing IP

Equipment modifications for chemical

Patent-pending improvements to

Semiconductor manufacturing,

Improvements—CMP

mechanical polishing (CMP) that

mass-market equipment.

compact disc or other polishing

increase equipment reliability and

applications.

reduce complexity and process scrap.

Copper Slurry Chemistries

Manufacturing IP

Proprietary slurry chemistries

Proven on high-yielding

Semiconductor manufacturing, other

developed for copper polishing.

0.13 µm CMOS process.

copper polishing applications.

Equipment

Manufacturing IP

Equipment modifications for

Provides improved control over

Semiconductor manufacturing,

Improvements—Metal Sputter

metal sputtering.

sputtering process, as well as

equipment development.

increased sputtering kit life.

Plating Chemistries

Manufacturing IP

Proprietary chemistries developed for

Ultrapure coatings with excellent

Semiconductor manufacturing,

and Processes

specialized metal-plating requirements.

controllability of layer thickness.

ultrathin metallic plating.

Contact:

Sarah Morris
(512) 996-4196
smorris@freescale.com