ac/Altera/FPGA_cyc2-html.html

June 2004,
v1.0

Added document to the Cyclone II Device
Handbook.

November
2004, v1.1

Updated

Figure 6–1

June 2004,
v1.0

Added document to the Cyclone II Device
Handbook.

Altera Corporation

1–1

November 2004

Preliminary

Chapter 1. Introduction

Introduction

Altera’s low-cost Cyclone

II FPGA family is based on a 1.2-V, 90-nm

SRAM process with densities over 68K logic elements (LEs) and up to
1.1 Mbits of embedded RAM. With features like embedded
18 × 18 multipliers to support high-performance DSP applications,
phase-locked loops (PLLs) for system clock management, and high-speed
external memory interface support for SRAM and DRAM devices,
Cyclone II devices are a cost-effective solution for high-volume
applications. Cyclone II devices support differential and single-ended
I/O standards, including LVDS at data rates up to 805 megabits per
second (Mbps) for the receiver and 622 Mbps for the transmitter, and
64-bit, 66-MHz PCI and PCI-X for interfacing with processors and ASSP
and ASIC devices. Altera also offers low-cost serial configuration devices
to configure Cyclone II devices. The Cyclone II FPGA family offers
commercial grade, industrial grade, and lead-free devices.

Features

The Cyclone II device family offers the following features:

■

High-density architecture with 4,608 to 68,288 LEs

■

M4K embedded memory blocks

●

Up to 1.1 Mbits of RAM available without reducing available
logic

●

4,096 memory bits per block (4,608 bits per block including
512 parity bits)

●

Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32,
and ×36

●

True dual-port (one read and one write, two reads, or two
writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes

●

Byte enables for data input masking during writes

●

Up to 250-MHz operation

■

Embedded multipliers

●

18- × 18-bit multipliers are each configurable as two
independent 9- × 9-bit multipliers with up to 250-MHz
performance

●

Optional input and output registers

■

Advanced I/O support

●

High-speed differential I/O standard support, including LVDS,
RSDS, mini-LVDS, LVPECL, differential HSTL, and differential
SSTL

●

Single-ended I/O standard support, including 2.5-V and 1.8-V
SSTL class I and II, 1.8-V and 1.5-V HSTL class I and II, 3.3-V PCI

CII51001-1.1

1–2

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Features

and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-,
and 1.8-V LVTTL

●

Peripheral component interconnect Special Interest Group (PCI
SIG)

PCI Local Bus Specification, Revision 3.0

compliance for

3.3-V operation at 33 or 66 MHz for 32- or 64-bit interfaces

●

100-MHz PCI-X 1.0 specification compatibility

●

High-speed external memory support, including DDR, DDR2,
and SDR SDRAM, and QDRII SRAM

●

Three dedicated registers per I/O element (IOE): one input
register, one output register, and one output-enable register

●

Programmable bus-hold feature

●

Programmable output drive strength feature

●

Programmable delays from the pin to the IOE or logic array

●

I/O bank grouping for unique V

CCIO

and/or V

REF

bank settings

●

MultiVolt

I/O standard support for 1.5-, 1.8-, 2.5-, and 3.3-V

interfaces

●

Hot-socketing operation support

●

Tri-state with weak pull-up on I/O pins before and during
configuration

●

Programmable open-drain outputs

●

Series on-chip termination support

■

Flexible clock management circuitry

●

Hierarchical clock network for up to 402.5-MHz performance

●

Up to four PLLs per device provide clock multiplication and
division, phase shifting, programmable duty cycle, and external
clock outputs, allowing system-level clock management and
skew control

●

Up to 16 global clock lines in the global clock network that drive
throughout the entire device

■

Device configuration

●

Fast serial configuration allows configuration times less than
100 ms

●

Decompression feature allows for smaller programming file
storage and faster configuration times

●

Supports multiple configuration modes: active serial, passive
serial, and JTAG-based configuration

●

Supports configuration through low-cost serial configuration
devices

●

Device configuration supports multiple voltages (either 3.3, 2.5,
or 1.8 V)

■

Intellectual property

●

Altera megafunction support

●

Altera MegaCore

function support

●

Altera Megafunctions Partners Program (AMPP

)

megafunctions support

Altera Corporation

Preliminary

1–3

November 2004

Cyclone II Device Handbook, Volume 1

Introduction

Table 1–1

lists the Cyclone II device family features.

Table 1–2

lists the

Cyclone II device package offerings and maximum user I/O pins.

Table 1–1. Cyclone II FPGA Family Features

Feature

EP2C5

EP2C8

EP2C20

EP2C35

EP2C50

EP2C70

LEs

4,608

8,256

18,752

33,216

50,528

68,416

M4K RAM blocks (4 Kbits
plus 512 parity bits

105

129

250

Total RAM bits

119,808

165,888

239,616

483,840

594,432

1,152,000

Embedded multipliers

150

PLLs

Maximum user I/O pins

142

182

315

475

450

622

Table 1–1

(1)

This is the total number of 18 × 18 multipliers. For the total number of 9 × 9 multipliers per device, multiply the
total number of 18 × 18 multipliers by 2.

Table 1–2. Cyclone II Package Options & Maximum User I/O Pins

Device

144-Pin TQFP

208-Pin PQFP

256-Pin

FineLine BGA

484-Pin

FineLine BGA

672-Pin

FineLine BGA

896-Pin

FineLine BGA

EP2C5

142

EP2C8

138

182

EP2C20

152

315

EP2C35

322

475

EP2C50

294

450

EP2C70

“LAB Control Signals” on page 2–8

422

622

Notes to

Table 1–2

(1)

Cyclone II devices support vertical migration within the same package (for example, designers can migrate
between the EP2C20 device in the 484-pin FineLine BGA

package and the EP2C35 and EP2C50 devices in the same

package).

(2)

TQFP: thin quad flat pack.

(3)

PQFP: plastic quad flat pack.

(4)

Contact your local Altera sales representative for more information on this device.

(5)

The I/O pin counts for the EP2C5 and EP2C8 devices include 8 dedicated clock pins that can be used for data
inputs. The I/O counts for the EP2C20, EP2C35, EP2C50, and EP2C70 devices include 16 dedicated clock pins that
can be used for data inputs.

Altera Corporation

2–1

November 2004

Preliminary

Chapter 2. Cyclone II

Architecture

Functional
Description

Cyclone™ II devices contain a two-dimensional row- and column-based
architecture to implement custom logic. Column and row interconnects of
varying speeds provide signal interconnects between logic array blocks
(LABs), embedded memory blocks, and embedded multipliers.

The logic array consists of LABs, with 16 logic elements (LEs) in each
LAB. An LE is a small unit of logic providing efficient implementation of
user logic functions. LABs are grouped into rows and columns across the
device. Cyclone II devices range in density from 4,608 to 68,416 LEs.

Cyclone II devices provide a global clock network and up to four phase-
locked loops (PLLs). The global clock network consists of up to 16 global
clock lines that drive throughout the entire device. The global clock
network can provide clocks for all resources within the device, such as
input/output elements (IOEs), LEs, embedded multipliers, and
embedded memory blocks. The global clock lines can also be used for
other high fan-out signals. Cyclone II PLLs provide general-purpose
clocking with clock synthesis and phase shifting as well as external
outputs for high-speed differential I/O support.

M4K memory blocks are true dual-port memory blocks with 4K bits of
memory plus parity (4,608 bits). These blocks provide dedicated true
dual-port, simple dual-port, or single-port memory up to 36-bits wide at
up to 250 MHz. These blocks are arranged in columns across the device
in between certain LABs. Cyclone II devices offer between 119 to
1,152 Kbits of embedded memory.

Each embedded multiplier block can implement up to either two 9 × 9-bit
multipliers, or one 18 × 18-bit multiplier with up to 250-MHz
performance. Embedded multipliers are arranged in columns across the
device.

Each Cyclone II device I/O pin is fed by an IOE located at the ends of LAB
rows and columns around the periphery of the device. I/O pins support
various single-ended and differential I/O standards, such as the 66- and
33-MHz, 64- and 32-bit PCI standard, PCI-X, and the LVDS I/O standard
at a maximum data rate of 805 megabits per second (Mbps) for inputs and
622 Mbps for outputs. Each IOE contains a bidirectional I/O buffer and
three registers for registering input, output, and output-enable signals.
Dual-purpose DQS, DQ, and DM pins along with delay chains (used to

CII51002-1.1

2–2

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Functional Description

phase-align double data rate (DDR) signals) provide interface support for
external memory devices such as DDR, DDR2, and single data rate (SDR)
SDRAM, and QDRII SRAM devices at up to 167 MHz.

Figure 2–1

shows a diagram of the Cyclone II EP2C20 device.

Figure 2–1. Cyclone II EP2C20 Device Block Diagram

The number of M4K memory blocks, embedded multiplier blocks, PLLs,
rows, and columns vary per device.

Table 2–1

lists the resources available

in each Cyclone II device.

PLL

IOEs

PLL

IOEs

Logic
Array

IOEs

M4K Blocks

Embedded
Multipliers

Table 2–1. Cyclone II Device Resources

Device

LAB Columns

LAB Rows

LEs

PLLs

M4K Memory

Blocks

Embedded

Multiplier

Blocks

EP2C5

4,608

EP2C8

8,256

EP2C20

18,752

EP2C35

33,216

105

EP2C50

50,528

129

EP2C70

68,416

250

150

Altera Corporation

Preliminary

2–3

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Logic Elements

The smallest unit of logic in the Cyclone II architecture, the LE, is compact
and provides advanced features with efficient logic utilization. Each LE
features:

■

A four-input look-up table (LUT), which is a function generator that
can implement any function of four variables

■

A programmable register

■

A carry chain connection

■

A register chain connection

■

The ability to drive all types of interconnects: local, row, column,
register chain, and direct link interconnects

■

Support for register packing

■

Support for register feedback

Figure 2–2

shows a Cyclone II LE.

Figure 2–2. Cyclone II LE

labclk1

labclk2

labclr2

LAB Carry-In

Clock &

Clock Enable

Select

LAB Carry-Out

Look-Up

Table
(LUT)

Carry

Chain

Row, Column,
And Direct Link
Routing

Programmable
Register

CLRN

ENA

Register Bypass

Packed
Register Select

Chip-Wide

Reset

(DEV_CLRn)

labclkena1

labclkena2

Synchronous

Load and

Clear Logic

LAB-Wide

Synchronous

Load

LAB-Wide

Synchronous

Clear

Asynchronous

Clear Logic

data1
data2
data3

data4

labclr1

Local Routing

2–4

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Logic Elements

Each LE’s programmable register can be configured for D, T, JK, or SR
operation. Each register has data, clock, clock enable, and clear inputs.
Signals that use the global clock network, general-purpose I/O pins, or
any internal logic can drive the register’s clock and clear control signals.
Either general-purpose I/O pins or internal logic can drive the clock
enable. For combinatorial functions, the LUT output bypasses the register
and drives directly to the LE outputs.

Each LE has three outputs that drive the local, row, and column routing
resources. The LUT or register output can drive these three outputs
independently. Two LE outputs drive column or row and direct link
routing connections and one drives local interconnect resources, allowing
the LUT to drive one output while the register drives another output. This
feature, register packing, improves device utilization because the device
can use the register and the LUT for unrelated functions. When using
register packing, the LAB-wide synchronous load control signal is not
available. See

for more information.

Another special packing mode allows the register output to feed back into
the LUT of the same LE so that the register is packed with its own fan-out
LUT, providing another mechanism for improved fitting. The LE can also
drive out registered and unregistered versions of the LUT output.

In addition to the three general routing outputs, the LEs within an LAB
have register chain outputs. Register chain outputs allow registers within
the same LAB to cascade together. The register chain output allows an
LAB to use LUTs for a single combinatorial function and the registers to
be used for an unrelated shift register implementation. These resources
speed up connections between LABs while saving local interconnect
resources. See

“MultiTrack Interconnect” on page 2–10

for more

information on register chain connections.

LE Operating Modes

The Cyclone II LE operates in one of the following modes:

■

Normal mode

■

Arithmetic mode

Each mode uses LE resources differently. In each mode, six available
inputs to the LE—the four data inputs from the LAB local interconnect,
the LAB carry-in from the previous carry-chain LAB, and the register
chain connection—are directed to different destinations to implement the
desired logic function. LAB-wide signals provide clock, asynchronous
clear, synchronous clear, synchronous load, and clock enable control for
the register. These LAB-wide signals are available in all LE modes.

Altera Corporation

Preliminary

2–5

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

The Quartus II software, in conjunction with parameterized functions
such as library of parameterized modules (LPM) functions, automatically
chooses the appropriate mode for common functions such as counters,
adders, subtractors, and arithmetic functions. If required, the designer
can also create special-purpose functions that specify which LE operating
mode to use for optimal performance.

Normal Mode

The normal mode is suitable for general logic applications and
combinatorial functions. In normal mode, four data inputs from the LAB
local interconnect are inputs to a four-input LUT (see

Figure 2–3

). The

Quartus II Compiler automatically selects the carry-in or the

data3

signal as one of the inputs to the LUT. LEs in normal mode support
packed registers and register feedback.

Figure 2–3. LE in Normal Mode

data1

Four-Input

LUT

data2

data3
cin (from cout
of previous LE)

data4

clock (LAB Wide)

ena (LAB Wide)

aclr (LAB Wide)

CLRN

ENA

sclear

(LAB Wide)

sload

(LAB Wide)

connection

Row, Column, and
Direct Link Routing

Local routing

Register Feedback

Packed Register Input

2–6

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Logic Elements

Arithmetic Mode

The arithmetic mode is ideal for implementing adders, counters,
accumulators, and comparators. An LE in arithmetic mode implements a
2-bit full adder and basic carry chain (see

Figure 2–4

). LEs in arithmetic

mode can drive out registered and unregistered versions of the LUT
output. Register feedback and register packing are supported when LEs
are used in arithmetic mode.

Figure 2–4. LE in Arithmetic Mode

The Quartus II Compiler automatically creates carry chain logic during
design processing, or the designer can create it manually during design
entry. Parameterized functions such as LPM functions automatically take
advantage of carry chains for the appropriate functions.

The Quartus II Compiler creates carry chains longer than 16 LEs by
automatically linking LABs in the same column. For enhanced fitting, a
long carry chain runs vertically, which allows fast horizontal connections
to M4K memory blocks or embedded multipliers through direct link
interconnects. For example, if a design has a long carry chain in a LAB
column next to a column of M4K memory blocks, any LE output can feed
an adjacent M4K memory block through the direct link interconnect.
Whereas if the carry chains ran horizontally, any LAB not next to the
column of M4K memory blocks would use other row or column
interconnects to drive a M4K memory block. A carry chain continues as
far as a full column.

clock (LAB Wide)

ena (LAB Wide)

aclr (LAB Wide)

CLRN

ENA

connection

sclear

(LAB Wide)

sload

(LAB Wide)

Row, column, and
direct link routing

Local routing

Three-Input

LUT

Three-Input

LUT

cin (from cout

of previous LE)

data2

data1

cout

Altera Corporation

Preliminary

2–7

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Logic Array
Blocks

Each LAB consists of:

■

16 LEs

■

LAB control signals

■

LE carry chains

■

Local interconnect

The local interconnect transfers signals between LEs in the same LAB.
Register chain connections transfer the output of one LE’s register to the
adjacent LE’s register within an LAB. The Quartus

II Compiler places

associated logic within an LAB or adjacent LABs, allowing the use of
local, and register chain connections for performance and area efficiency.

Figure 2–5

shows the Cyclone II LAB.

Figure 2–5. Cyclone II LAB Structure

Direct link
interconnect
from adjacent
block

Direct link
interconnect
to adjacent
block

Row Interconnect

Column
Interconnect

Local Interconnect

LAB

Direct link
interconnect
from adjacent
block

Direct link
interconnect
to adjacent
block

2–8

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Logic Array Blocks

LAB Interconnects

The LAB local interconnect can drive LEs within the same LAB. The LAB
local interconnect is driven by column and row interconnects and LE
outputs within the same LAB. Neighboring LABs, PLLs, M4K RAM
blocks, and embedded multipliers from the left and right can also drive
an LAB’s local interconnect through the direct link connection. The direct
link connection feature minimizes the use of row and column
interconnects, providing higher performance and flexibility. Each LE can
drive 48 LEs through fast local and direct link interconnects.

Figure 2–6

shows the direct link connection.

Figure 2–6. Direct Link Connection

LAB Control Signals

Each LAB contains dedicated logic for driving control signals to its LEs.
The control signals include:

■

Two clocks

■

Two clock enables

■

Two asynchronous clears

■

One synchronous clear

■

One synchronous load

LAB

Direct link
interconnect
to right

Direct link interconnect from
right LAB, M4K memory
block, embedded multiplier,
PLL, or IOE output

Direct link interconnect from

left LAB, M4K memory

block, embedded multiplier,

PLL, or IOE output

Local

Interconnect

Direct link

interconnect

to left

Altera Corporation

Preliminary

2–9

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

This gives a maximum of seven control signals at a time. When using the
LAB-wide synchronous load, the

clkena

labclk1

is not available.

Additionally, register packing and synchronous load cannot be used
simultaneously.

Each LAB can have up to four non-global control signals. Additional LAB
control signals can be used as long as they are global signals.

Synchronous clear and load signals are useful for implementing counters
and other functions. The synchronous clear and synchronous load signals
are LAB-wide signals that affect all registers in the LAB.

Each LAB can use two clocks and two clock enable signals. Each LAB’s
clock and clock enable signals are linked. For example, any LE in a
particular LAB using the

labclk1

signal also uses

labclkena1

. If the

LAB uses both the rising and falling edges of a clock, it also uses both
LAB-wide clock signals. De-asserting the clock enable signal turns off the
LAB-wide clock.

The LAB row clocks [5..0] and LAB local interconnect generate the LAB-
wide control signals. The MultiTrack

™

interconnect’s inherent low skew

allows clock and control signal distribution in addition to data.

Figure 2–7

shows the LAB control signal generation circuit.

Figure 2–7. LAB-Wide Control Signals

LAB-wide signals control the logic for the register’s clear signal. The LE
directly supports an asynchronous clear function. Each LAB supports up
to two asynchronous clear signals (

labclr1

and

labclr2

labclkena1

labclk2

labclk1

labclkena2

labclr1

Dedicated
LAB Row
Clocks

Local
Interconnect

syncload

synclr

labclr2

2–10

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

MultiTrack Interconnect

A LAB-wide asynchronous load signal to control the logic for the
register’s preset signal is not available. The register preset is achieved by
using a NOT gate push-back technique. Cyclone II devices can only
support either a preset or asynchronous clear signal.

In addition to the clear port, Cyclone II devices provide a chip-wide reset
pin (

DEV_CLRn

) that resets all registers in the device. An option set before

compilation in the Quartus II software controls this pin. This chip-wide
reset overrides all other control signals.

MultiTrack
Interconnect

In the Cyclone II architecture, connections between LEs, M4K memory
blocks, embedded multipliers, and device I/O pins are provided by the
MultiTrack interconnect structure with DirectDrive™ technology. The
MultiTrack interconnect consists of continuous, performance-optimized
routing lines of different speeds used for inter- and intra-design block
connectivity. The Quartus II Compiler automatically places critical paths
on faster interconnects to improve design performance.

DirectDrive technology is a deterministic routing technology that ensures
identical routing resource usage for any function regardless of placement
within the device. The MultiTrack interconnect and DirectDrive
technology simplify the integration stage of block-based designing by
eliminating the re-optimization cycles that typically follow design
changes and additions.

The MultiTrack interconnect consists of row (direct link, R4, and R24) and
column (register chain, C4, and C16) interconnects that span fixed
distances. A routing structure with fixed-length resources for all devices
allows predictable and repeatable performance when migrating through
different device densities.

Row Interconnects

Dedicated row interconnects route signals to and from LABs, PLLs, M4K
memory blocks, and embedded multipliers within the same row. These
row resources include:

■

Direct link interconnects between LABs and adjacent blocks

■

R4 interconnects traversing four blocks to the right or left

■

R24 interconnects for high-speed access across the length of the
device

Altera Corporation

Preliminary

2–11

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

The direct link interconnect allows an LAB, M4K memory block, or
embedded multiplier block to drive into the local interconnect of its left
and right neighbors. Only one side of a PLL block interfaces with direct
link and row interconnects. The direct link interconnect provides fast
communication between adjacent LABs and/or blocks without using row
interconnect resources.

The R4 interconnects span four LABs, three LABs and one M4K memory
block, or three LABs and one embedded multiplier to the right or left of a
source LAB. These resources are used for fast row connections in a four-
LAB region. Every LAB has its own set of R4 interconnects to drive either
left or right.

Figure 2–8

shows R4 interconnect connections from an LAB.

R4 interconnects can drive and be driven by LABs, M4K memory blocks,
embedded multipliers, PLLs, and row IOEs. For LAB interfacing, a
primary LAB or LAB neighbor (see

Figure 2–8

) can drive a given R4

interconnect. For R4 interconnects that drive to the right, the primary
LAB and right neighbor can drive on to the interconnect. For R4
interconnects that drive to the left, the primary LAB and its left neighbor
can drive on to the interconnect. R4 interconnects can drive other R4
interconnects to extend the range of LABs they can drive. Additionally,
R4 interconnects can drive R24 interconnects, C4, and C16 interconnects
for connections from one row to another.

Figure 2–8. R4 Interconnect Connections

Notes to

Figure 2–8

(1)

C4 interconnects can drive R4 interconnects.

(2)

This pattern is repeated for every LAB in the LAB row.

Primary
LAB (2)

R4 Interconnect

Driving Left

Adjacent LAB can
Drive onto Another
LAB's R4 Interconnect

C4 Column Interconnects (1)

R4 Interconnect
Driving Right

LAB

Neighbor

LAB

Neighbor

2–12

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

MultiTrack Interconnect

R24 row interconnects span 24 LABs and provide the fastest resource for
long row connections between non-adjacent LABs, M4K memory blocks,
dedicated multipliers, and row IOEs. R24 row interconnects drive to
other row or column interconnects at every fourth LAB. R24 row
interconnects drive LAB local interconnects via R4 and C4 interconnects
and do not drive directly to LAB local interconnects. R24 interconnects
can drive R24, R4, C16, and C4 interconnects.

Column Interconnects

The column interconnect operates similar to the row interconnect. Each
column of LABs is served by a dedicated column interconnect, which
vertically routes signals to and from LABs, M4K memory blocks,
embedded multipliers, and row and column IOEs. These column
resources include:

■

C4 interconnects traversing a distance of four blocks in an up and
down direction

■

C16 interconnects for high-speed vertical routing through the device

Cyclone II devices include an enhanced interconnect structure within
LABs for routing LE output to LE input connections faster using register
chain connections. The register chain connection allows the register
output of one LE to connect directly to the register input of the next LE in
the LAB for fast shift registers. The Quartus II Compiler automatically
takes advantage of these resources to improve utilization and
performance.

Figure 2–9

shows the register chain interconnects.

Altera Corporation

Preliminary

2–13

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Figure 2–9. Register Chain Interconnects

The C4 interconnects span four LABs, M4K blocks, or embedded
multipliers up or down from a source LAB. Every LAB has its own set of
C4 interconnects to drive either up or down.

Figure 2–10

shows the C4

interconnect connections from an LAB in a column. The C4 interconnects
can drive and be driven by all types of architecture blocks, including
PLLs, M4K memory blocks, embedded multiplier blocks, and column
and row IOEs. For LAB interconnection, a primary LAB or its LAB
neighbor (see

Figure 2–10

) can drive a given C4 interconnect. C4

interconnects can drive each other to extend their range as well as drive
row interconnects for column-to-column connections.

LE 1

LE 2

LE 3

LE 4

LE 5

LE 6

LE 7

LE 8

LE 9

LE 10

LE 11

LE 12

LE13

LE 14

LE 15

LE 16

Carry Chain

Routing to

Adjacent LE

Local

Interconnect

Local Interconnect
Routing Among LEs
in the LAB

Altera Corporation

Preliminary

2–15

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

C16 column interconnects span a length of 16 LABs and provide the
fastest resource for long column connections between LABs, M4K
memory blocks, embedded multipliers, and IOEs. C16 column
interconnects drive to other row and column interconnects at every
fourth LAB. C16 column interconnects drive LAB local interconnects via
C4 and R4 interconnects and do not drive LAB local interconnects
directly. C16 interconnects can drive R24, R4, C16, and C4 interconnects.

Device Routing

All embedded blocks communicate with the logic array similar to LAB-
to-LAB interfaces. Each block (for example, M4K memory, embedded
multiplier, or PLL) connects to row and column interconnects and has
local interconnect regions driven by row and column interconnects. These
blocks also have direct link interconnects for fast connections to and from
a neighboring LAB.

Table 2–2

shows the Cyclone II device’s routing scheme.

Table 2–2. Cyclone II Device Routing Scheme (Part 1 of 2)

Source

Destination

Register

Chain

Loca

l Inter

connect

Direct Link

Interconnect

R4 Interconn

ect

4 Interconnect

C4 Intercon

nect

C16 Interconnect

M4K RAM Bloc

Embe

dded Multiplier

PLL

Col

mn IO

w I

Local
Interconnect

Direct Link
Interconnect

R4
Interconnect

R24
Interconnect

C4
Interconnect

C16
Interconnect

2–16

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Global Clock Network & Phase-Locked Loops

Global Clock
Network &
Phase-Locked
Loops

Cyclone II devices provide global clock networks and up to four PLLs for
a complete clock management solution. Cyclone II clock network features
include:

■

Up to 16 global clock networks

■

Up to four PLLs

■

Global clock network dynamic clock source selection

■

Global clock network dynamic enable and disable

M4K memory
Block

Embedded
Multipliers

PLL

Column IOE

Row IOE

Table 2–2. Cyclone II Device Routing Scheme (Part 2 of 2)

Source

Destination

Register Chain

Local Inte

rconn

ect

Direct Link

Interconnect

R4 Interco

nnect

R24 Interconnect

C4 Interconnect

C16 Inter

connect

M4K

ock

Embedded Multiplier

Col

mn IO

Row IO

Altera Corporation

Preliminary

2–17

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Each global clock network has a clock control block to select from a
number of input clock sources (PLL clock outputs,

CLK[]

pins,

DPCLK[]

pins, and internal logic) to drive onto the global clock network.

Table 2–3

lists how many PLLs,

CLK[]

pins,

DPCLK[]

pins, and global clock

networks are available in each Cyclone II device.

CLK[]

pins are

dedicated clock pins and

DPCLK[]

pins are dual-purpose clock pins.

Figures 2–11

2–12

show the location of the Cyclone II PLLs,

CLK[]

inputs,

DPCLK[]

pins, and clock control blocks.

Table 2–3. Cyclone II Device Clock Resources

Device

Number of

PLLs

Number of

CLK Pins

Number of

DPCLK Pins

Number of

Global Clock

Networks

EP2C5

EP2C8

EP2C20

EP2C35

EP2C50

EP2C70

2–18

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Global Clock Network & Phase-Locked Loops

Figure 2–11. EP2C5 & EP2C8 PLL, CLK[], DPCLK[] & Clock Control Block Locations

Note to

Figure 2–11

(1)

There are four clock control blocks on each side.

PLL 2

CLK[7..4]

DPCLK7

DPCLK6

CLK[3..0]

DPCLK0

DPCLK1

DPCLK10

DPCLK8

DPCLK2

GCLK[7..0]

DPCLK4

PLL 1

Clock Control

Block (1)

Clock Control

Block (1)

Altera Corporation

Preliminary

2–19

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Figure 2–12. EP2C20 & Larger PLL, CLK[], DPCLK[] & Clock Control Block Locations

Notes to

Figure 2–12

(1)

There are four clock control blocks on each side.

(2)

Only one of the corner

CDPCLK

pins in each corner can feed the clock control block at a time. The other

CDPCLK

pins

can be used as general-purpose I/O pins.

Dedicated Clock Pins

Larger Cyclone II devices (EP2C20 and larger devices) have 16 dedicated
clock pins (

CLK[15..0]

, four pins on each side of the device). Smaller

Cyclone II devices (EP2C5 and EP2C8 devices) have eight dedicated clock
pins (

CLK[7..0]

, four pins on left and right sides of the device). These

CLK

pins drive the global clock network (GCLK), as shown in

Figures 2–11

2–12

PLL 4

PLL 3

PLL 2

CLK[7..4]

DPCLK7

CDPCLK5

CDPCLK4

DPCLK6

CLK[3..0]

DPCLK0

CDPCLK0

CDPCLK1

DPCLK1

CDPCLK7

DPCLK[9..8]

DPCLK[11..10]

CLK[11..8]

GCLK[15..0]

PLL 1

CDPCLK6

CDPCLK2

DPCLK[5..4]

DPCLK[3..2]

CLK[15..12]

CDPCLK3

Clock Control

Block (1)

Clock Control

Block (1)

(2)

2–20

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Global Clock Network & Phase-Locked Loops

If the dedicated clock pins are not used to feed the global clock networks,
they can be used as general-purpose input pins to feed the logic array
using the MultiTrack interconnect. However, if they are used as general-
purpose input pins, they do not have support for an I/O register and
must use LE-based registers in place of an I/O register.

Dual-Purpose Clock Pins

Cyclone II devices have either 20 dual-purpose clock pins,

DPCLK[19..0]

or 8 dual-purpose clock pins,

DPCLK[7..0]

. In the

larger Cyclone II devices (EP2C20 devices and higher), there are
20

DPCLK

pins; four on the left and right sides and six on the top and

bottom of the device. The corner

CDPCLK

pins are first multiplexed before

they drive into the clock control block. Since the signals pass through a
multiplexer before feeding the clock control block, these signals incur
more delay to the clock control block than other

DPCLK

pins that directly

feed the clock control block. In the smaller Cyclone II devices (EP2C5 and
EP2C8 devices), there are eight

DPCLK

pins; two on each side of the device

A programmable delay chain is available from the

DPCLK

pin to its fan-

out destinations. To set the propagation delay from the

DPCLK

pin to its

fan-out destinations, use the

Input Delay from Dual-Purpose Clock Pin

to Fan-Out Destinations

assignment in the Quartus II software.

These dual-purpose pins can connect to the global clock network for
high-fanout control signals such as clocks, asynchronous clears, presets,
and clock enables, or protocol control signals such as

TRDY

and

IRDY

for

PCI, or DQS signals for external memory interfaces.

Global Clock Network

The 16 or 8 global clock networks drive throughout the entire device.
Dedicated clock pins (

CLK[]

), PLL outputs, the logic array, and dual-

purpose clock (

DPCLK[]

) pins can also drive the global clock network.

The global clock network can provide clocks for all resources within the
device, such as IOEs, LEs, memory blocks, and embedded multipliers.
The global clock lines can also be used for control signals, such as clock
enables and synchronous or asynchronous clears fed from the external
pin, or DQS signals for DDR SDRAM or QDRII SRAM interfaces. Internal
logic can also drive the global clock network for internally generated
global clocks and asynchronous clears, clock enables, or other control
signals with large fan-out.

Altera Corporation

Preliminary

2–21

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Clock Control Block

There is a clock control block for each global clock network available in
Cyclone II devices. The clock control blocks are arranged on the device
periphery and there are a maximum of 16 clock control blocks available
per Cyclone II device. The larger Cyclone II devices (EP2C20 devices and
larger) have 16 clock control blocks, four on each side of the device. The
smaller Cyclone II devices (EP2C5 and EP2C8 devices) have eight clock
control blocks, four on the left and right sides of the device.

The control block has these functions:

■

Dynamic global clock network clock source selection

■

Dynamic enable/disable of the global clock network

In Cyclone II devices, the dedicated

CLK[]

pins, PLL counter outputs,

DPCLK[]

pins, and internal logic can all feed the clock control block. The

output from the clock control block in turn feeds the corresponding global
clock network.

The following sources can be inputs to a given clock control block:

■

Four clock pins on the same side as the clock control block

■

Three PLL clock outputs from a PLL

■

Four

DPCLK

pins (including

CDPCLK

pins) on the same side as the

clock control block

■

Four internally-generated signals

Of the sources listed, only two clock pins, two PLL clock outputs, one

DPCLK

pin, and one internally-generated signal are chosen to drive into a

clock control block.

Figure 2–13

shows a more detailed diagram of the

clock control block. Out of these six inputs, the two clock input pins and
two PLL outputs can be dynamic selected to feed a global clock network.
The clock control block supports static selection of

DPCLK

and the signal

from internal logic.

2–22

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Global Clock Network & Phase-Locked Loops

Figure 2–13. Clock Control Block

Notes to

Figure 2–13

(1)

The

CLKSWITCH

signal can either be set through the configuration file or it can be dynamically set when using the

manual PLL switchover feature. The output of the multiplexer is the input reference clock (f

) for the PLL.

(2)

The

CLKSELECT[1..0]

signals are fed by internal logic and can be used to dynamically select the clock source for

the global clock network when the device is in user mode.

(3)

The static clock select signals are set in the configuration file and cannot be dynamically controlled when the device
is in user mode.

(4)

Internal logic can be used to enabled or disabled the global clock network in user mode.

Global Clock Network Distribution

Cyclone II devices contains 16 global clock networks. The device uses
multiplexers with these clocks to form six-bit buses to drive column IOE
clocks, LAB row clocks, or row IOE clocks (see

Figure 2–14

). Another

multiplexer at the LAB level selects two of the six LAB row clocks to feed
the LE registers within the LAB.

CLKSWITCH

(1)

Static Clock Select

(3)

Static Clock

Select

(3)

Internal Logic

Clock Control Block

DPCLK or

CDPCLK

CLKSELECT[1..0]

(2)

CLKENA

(4)

inclk1
inclk0

CLK[

+ 3]

CLK[

+ 2]

CLK[

+ 1]

CLK[

]

C0
C1
C2

PLL

Global
Clock

Enable/
Disable

(3)

2–24

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Global Clock Network & Phase-Locked Loops

Figure 2–15. LAB & I/O Clock Regions

For more information on the global clock network and the clock control
block, see the

PLLs in Cyclone II Devices

chapter in Volume 1 of the

Cyclone II Device Handbook

Column I/O Clock Region

IO_CLK[5..0]

Column I/O Clock Region

IO_CLK[5..0]

I/O Clock Regions

8 or 16

Global Clock
Network

Row I/O Clock
Region
IO_CLK[5..0]

Cyclone Logic Array

LAB Row Clocks

labclk[5..0]

LAB Row Clocks

labclk[5..0]

LAB Row Clocks

labclk[5..0]

LAB Row Clocks

labclk[5..0]

LAB Row Clocks

labclk[5..0]

LAB Row Clocks

labclk[5..0]

Altera Corporation

Preliminary

2–25

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

PLLs

Cyclone II PLLs provide general-purpose clocking as well as support for
the following features:

■

Clock multiplication and division

■

Phase shifting

■

Programmable duty cycle

■

Up to three internal clock outputs

■

One dedicated external clock output

■

Clock outputs for differential I/O support

■

Manual clock switchover

■

Programmable bandwidth

■

Gated lock signal

■

Three different clock feedback modes

■

Control signals

Cyclone II devices contain either two or four PLLs.

Table 2–4

shows the

PLLs available for each Cyclone II device.

Table 2–5

describes the PLL features in Cyclone II devices.

Table 2–4. Cyclone II Device PLL Availability

Device

PLL1

PLL2

PLL3

PLL4

EP2C5

EP2C8

EP2C20

EP2C35

EP2C50

EP2C70

Table 2–5. Cyclone II PLL Features (Part 1 of 2)

Feature

Description

Clock multiplication and division

/ (

× post-scale counter)

and post-scale counter values (C0 to C2) range from 1 to 32.

ranges

from 1 to 4.

Phase shift

Cyclone II PLLs have an advanced clock shift capability that enables
programmable phase shifts in increments of at least 45°. The finest
resolution of phase shifting is determined by the voltage control oscillator
(VCO) period divided by 8 (for example, 1/1000 MHz/8 = down to 125-ps
increments).

2–26

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Global Clock Network & Phase-Locked Loops

Figure 2–16

shows a block diagram of the Cyclone II PLL.

Programmable duty cycle

The programmable duty cycle allows PLLs to generate clock outputs with
a variable duty cycle. This feature is supported on each PLL post-scale
counter (C0-C2).

Number of internal clock outputs

The Cyclone II PLL has three outputs which can drive the global clock
network. One of these outputs (C2) can also drive a dedicated

PLL

_OUT

pin (single ended or differential).

Number of external clock outputs

The C2 output drives a dedicated

PLL

_OUT

pin. If the C2 output is not

used to drive an external clock output, it can be used to drive the internal
global clock network. The C2 output can concurrently drive the external
clock output and internal global clock network.

Manual clock switchover

The Cyclone II PLLs support manual switchover of the reference clock
through internal logic. This enables a designer to switch between two
reference input clocks during user mode for applications that may require
clock redundancy or support for clocks with two different frequencies.

Programmable bandwidth

Cyclone II PLLs allow the designer to control the bandwidth over a finite
range to customize the PLL characteristics for a particular application.
Advanced control of the PLL bandwidth is provided through the
programmable characteristics of the PLL loop, including loop filter and
charge pump. The bandwidth range is determined after characterization.

Gated lock signal

The lock output indicates that there is a stable clock output signal in phase
with the reference clock. Cyclone II PLLs include a programmable counter
that holds the lock signal low for a user-selected number of input clock
transitions, allowing the PLL to lock before enabling the locked signal.
Either a gated locked signal or an ungated locked signal from the locked
port can drive internal logic or an output pin.

Clock feedback modes

In zero delay buffer mode, the external clock output pin is phase-aligned
with the clock input pin for zero delay.
In normal mode, the PLL compensates for the internal global clock network
delay from the input clock pin to the clock port of the IOE output registers
or registers in the logic array.
In no compensation mode, the PLL does not compensate for any clock
networks.

Control signals

The

pllenable

signal enables and disables the PLLs.

The

areset

signal resets/resynchronizes the inputs for each PLL.

The

pfdena

signal controls the phase frequency detector (PFD) output

with a programmable gate.

Table 2–5. Cyclone II PLL Features (Part 2 of 2)

Feature

Description

Altera Corporation

Preliminary

2–27

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Figure 2–16. Cyclone II PLL

Notes to

Figure 2–16

(1)

This input can be single-ended or differential. If a designer is using a differential I/O standard, then two

CLK

pins

are used. LVDS input is supported via the secondary function of the dedicated

CLK

pins. For example, the

CLK0

pin’s secondary function is

LVDSCLK1p

and the

CLK1

pin’s secondary function is

LVDSCLK1n

. If a differential I/O

standard is assigned to the PLL clock input pin, the corresponding

CLK(n)

pin is also completely used. The

Figure 2–16

shows the possible clock input connections (

CLK0

CLK1

) to PLL1.

(2)

This counter output is shared between a dedicated external clock output I/O and the global clock network.

For more information on Cyclone II PLLs, see the PLLs in the

Cyclone II

Devices

chapter in Volume 1 of the

Cyclone II Device Handbook

Embedded
Memory

The Cyclone II embedded memory consists of columns of M4K memory
blocks. The M4K memory blocks include input registers that synchronize
writes and output registers to pipeline designs and improve system
performance. The output registers can be bypassed, but input registers
cannot.

PFD

Loop
Filter

Lock Detect

& Filter

VCO

Charge

Pump

÷c0

÷c1

÷c2

Global
Clock

to I/O or
general routing

PLL<

#>_OUT

Post-Scale

Counters

VCO Phase Selection

Selectable at Each

PLL Output Port

CLK1

CLK3

CLK2

(1)

CLK0

(1)

inclk0

inclk1

down

VCO

Reference

Input Clock

REF

= f

(2)

Manual Clock

Switchover

Select Signal

2–28

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Embedded Memory

Each M4K block can implement various types of memory with or without
parity, including true dual-port, simple dual-port, and single-port RAM,
ROM, and first-in first-out (FIFO) buffers. The M4K blocks support the
following features:

■

4,608 RAM bits

■

250-MHz performance

■

True dual-port memory

■

Simple dual-port memory

■

Single-port memory

■

Byte enable

■

Parity bits

■

Shift register

■

FIFO buffer

■

ROM

■

Various clock modes

■

Address clock enable

Table 2–6

shows the capacity and distribution of the M4K memory blocks

in each Cyclone II device.

Table 2–7

summarizes the features supported by the M4K memory.

Table 2–6. M4K Memory Capacity & Distribution in Cyclone II Devices

Device

M4K Columns

M4K Blocks

Total RAM Bits

EP2C5

119,808

EP2C8

165,888

EP2C20

239,616

EP2C35

105

483,840

EP2C50

129

594,432

EP2C70

250

1,152,000

Table 2–7. M4K Memory Features (Part 1 of 2)

Feature

Description

Maximum performance

250 MHz

Total RAM bits per M4K block (including parity bits)

4,608

Altera Corporation

Preliminary

2–29

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Configurations supported

4K × 1
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32 (not available in true dual-port mode)
128 × 36 (not available in true dual-port mode)

Parity bits

One parity bit for each byte. The parity bit, along with
internal user logic, can implement parity checking for
error detection to ensure data integrity.

Byte enable

M4K blocks support byte writes when the write port has
a data width of 1, 2, 4, 8, 9, 16, 18, 32, or 36 bits. The
byte enables allow the input data to be masked so the
device can write to specific bytes. The unwritten bytes
retain the previous written value.

Packed mode

Two single-port memory blocks can be packed into a
single M4K block if each of the two independent block
sizes are equal to or less than half of the M4K block
size, and each of the single-port memory blocks is
configured in single-clock mode.

Address clock enable

M4K blocks support address clock enable, which is
used to hold the previous address value for as long as
the signal is enabled. This feature is useful in handling
misses in cache applications.

Memory initialization file (

.mif

)

When configured as RAM or ROM, the designer can
use an initialization file to pre-load the memory
contents.

Power-up condition

Outputs cleared

Output registers only

Same-port read-during-write

New data available at positive clock edge

Mixed-port read-during-write

Old data available at positive clock edge

Table 2–7

(1)

Maximum performance information is preliminary until device characterization.

Table 2–7. M4K Memory Features (Part 2 of 2)

Feature

Description

2–30

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Embedded Memory

Memory Modes

Table 2–8

summarizes the different memory modes supported by the

M4K memory blocks.

Table 2–8. M4K Memory Modes

Memory Mode

Description

Single-port memory

M4K blocks support single-port mode, used when
simultaneous reads and writes are not required.
Single-port memory supports non-simultaneous
reads and writes.

Simple dual-port memory

Simple dual-port memory supports a
simultaneous read and write.

Simple dual-port with mixed
width

Simple dual-port memory mode with different
read and write port widths.

True dual-port memory

True dual-port mode supports any combination of
two-port operations: two reads, two writes, or one
read and one write at two different clock
frequencies.

True dual-port with mixed
width

True dual-port mode with different read and write
port widths.

Embedded shift register

M4K memory blocks are used to implement shift
registers. Data is written into each address
location at the falling edge of the clock and read
from the address at the rising edge of the clock.

ROM

The M4K memory blocks support ROM mode. A
MIF initializes the ROM contents of these blocks.

FIFO buffers

A single clock or dual clock FIFO may be
implemented in the M4K blocks. Simultaneous
read and write from an empty FIFO buffer is not
supported.

Altera Corporation

Preliminary

2–31

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Clock Modes

Table 2–9

summarizes the different clock modes supported by the M4K

memory.

Table 2–10

shows which clock modes are supported by all M4K blocks

when configured in the different memory modes.

M4K Routing Interface

The R4, C4, and direct link interconnects from adjacent LABs drive the
M4K block local interconnect. The M4K blocks can communicate with
LABs on either the left or right side through these row resources or with
LAB columns on either the right or left with the column resources. Up to
16 direct link input connections to the M4K block are possible from the
left adjacent LAB and another 16 possible from the right adjacent LAB.
M4K block outputs can also connect to left and right LABs through each
16 direct link interconnects.

Figure 2–17

shows the M4K block to logic

array interface.

Table 2–9. M4K Clock Modes

Clock Mode

Description

Independent

In this mode, a separate clock is available for each port (ports A
and B). Clock A controls all registers on the port A side, while
clock B controls all registers on the port B side.

Input/output

On each of the two ports, A or B, one clock controls all registers
for inputs into the memory block: data input,

wren

, and address.

The other clock controls the block’s data output registers.

Read/write

Up to two clocks are available in this mode. The write clock
controls the block’s data inputs,

wraddress

, and

wren

. The read

clock controls the data output,

rdaddress

, and

rden

Single

In this mode, a single clock, together with clock enable, is used to
control all registers of the memory block. Asynchronous clear
signals for the registers are not supported.

Table 2–10. Cyclone II M4K Memory Clock Modes

Clocking Modes

True Dual-Port

Mode

Simple Dual-Port

Mode

Single-Port Mode

Independent

Input/output

Read/write

Single clock

2–32

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Embedded Multipliers

Figure 2–17. M4K RAM Block LAB Row Interface

For more information on Cyclone II embedded memory, see the

Cyclone II Memory Blocks

chapter in Volume 1 of the

Cyclone II Device

Handbook

Embedded
Multipliers

Cyclone II devices have embedded multiplier blocks optimized for
multiplier-intensive digital signal processing (DSP) functions, such as
finite impulse response (FIR) filters, fast Fourier transform (FFT)
functions, and discrete cosine transform (DCT) functions. Designers can
use the embedded multiplier in one of two basic operational modes,
depending on the application needs:

■

One 18-bit multiplier

■

Up to two independent 9-bit multipliers

dataout

M4K RAM

Block

datain

address

Direct link
interconnect
from adjacent LAB

Direct link
interconnect
to adjacent LAB

Direct link
interconnect
from adjacent LAB

Direct link
interconnect
to adjacent LAB

M4K RAM Block Local
Interconnect Region

C4 Interconnects

R4 Interconnects

LAB Row Clocks

Clocks

Byte enable

Control

Signals

Altera Corporation

Preliminary

2–33

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Embedded multipliers can operate at up to 250 MHz (for the fastest speed
grade) for 18 × 18 and 9 × 9 multiplications when using both input and
output registers.

Each Cyclone II device has one to three columns of embedded multipliers
that efficiently implement multiplication functions. An embedded
multiplier spans the height of one LAB row.

Table 2–11

shows the number

of embedded multipliers in each Cyclone II device and the multipliers
that can be implemented.

The embedded multiplier consists of the following elements:

■

Multiplier block

■

Input and output registers

■

Input and output interfaces

Figure 2–18

shows the multiplier block architecture.

Table 2–11. Number of Embedded Multipliers in Cyclone II Devices

Device

Embedded

Multiplier Columns

Embedded

Multipliers

9 × 9 Multipliers

18 × 18 Multipliers

EP2C5

EP2C8

EP2C20

EP2C35

EP2C50

172

EP2C70

150

300

150

“Global Clock Network & Phase-Locked Loops” on page 2–16

Table 2–11

(1)

Each device has either the number of 9 × 9-, or 18 × 18-bit multipliers shown. The total number of multipliers for
each device is not the sum of all the multipliers.

2–34

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Embedded Multipliers

Figure 2–18. Multiplier Block Architecture

Note to

Figure 2–18

(1)

If necessary, these signals can be registered once to match the data signal path.

Each multiplier operand can be a unique signed or unsigned number.
Two signals,

signa

and

signb

, control the representation of each

operand respectively. A logic 1 value on the

signa

signal indicates that

data A is a signed number while a logic 0 value indicates an unsigned
number.

Table 2–12

shows the sign of the multiplication result for the

various operand sign representations. The result of the multiplication is
signed if any one of the operands is a signed value.

CLRN

ENA

Data A

Data B

aclr

clock

ena

signa

(1)

signb

(1)

CLRN

ENA

CLRN

ENA

Data Out

Embedded Multiplier Block

Output

Input

Table 2–12. Multiplier Sign Representation

Data A (signa Value)

Data B (signb Value)

Result

Unsigned

Signed

Unsigned

Signed

Altera Corporation

Preliminary

2–35

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

There is only one

signa

and one

signb

signal for each dedicated

multiplier. Therefore, all of the data A inputs feeding the same dedicated
multiplier must have the same sign representation. Similarly, all of the
data B inputs feeding the same dedicated multiplier must have the same
sign representation. The

signa

and

signb

signals can be changed

dynamically to modify the sign representation of the input operands at
run time. The multiplier offers full precision regardless of the sign
representation and can be registered using dedicated registers located at
the input register stage.

Multiplier Modes

Table 2–13

summarizes the different modes that the embedded

multipliers can operate in.

Embedded Multiplier Routing Interface

The R4, C4, and direct link interconnects from adjacent LABs drive the
embedded multiplier row interface interconnect. The embedded
multipliers can communicate with LABs on either the left or right side
through these row resources or with LAB columns on either the right or
left with the column resources. Up to 16 direct link input connections to
the embedded multiplier are possible from the left adjacent LABs and
another 16 possible from the right adjacent LAB. Embedded multiplier

Table 2–13. Embedded Multiplier Modes

Multiplier Mode

Description

18-bit Multiplier

An embedded multiplier can be configured to support a
single 18 × 18 multiplier for operand widths up to 18 bits.
All 18-bit multiplier inputs and results can be registered
independently. The multiplier operands can accept
signed integers, unsigned integers, or a combination of
both.

9-bit Multiplier

An embedded multiplier can be configured to support
two 9 × 9 independent multipliers for operand widths up
to 9-bits. Both 9-bit multiplier inputs and results can be
registered independently. The multiplier operands can
accept signed integers, unsigned integers or a
combination of both.
There is only one

signa

signal to control the sign

representation of both data A inputs and one

signb

signal to control the sign representation of both data B
inputs of the 9-bit multipliers within the same dedicated
multiplier.

2–36

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Embedded Multipliers

outputs can also connect to left and right LABs through 18 direct link
interconnects each.

Figure 2–19

shows the embedded multiplier to logic

array interface.

Figure 2–19. Embedded Multiplier LAB Row Interface

There are five dynamic control input signals that feed the embedded
multiplier:

signa

signb

clk

clkena

, and

aclr

signa

and

signb

can be registered to match the data signal input path. The same

clk

clkena

, and

aclr

signals feed all registers within a single embedded

multiplier.

For more information on Cyclone II embedded multipliers, see the

Embedded Multipliers in Cyclone II Devices

chapter.

LAB

Row Interface

Block

Embedded Multiplier

[35..0]

Embedded Multiplier
to LAB Row Interface
Block Interconnect Region

36 Inputs per Row

36 Outputs per Row

R4 Interconnects

C4 Interconnects

Direct Link Interconnect
from Adjacent LAB

18 Direct Link Outputs
to Adjacent LABs

Direct Link Interconnect
from Adjacent LAB

Control

LAB Block

Interconect Region

LAB Block

Interconect Region

Altera Corporation

Preliminary

2–37

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

I/O Structure &
Features

IOEs support many features, including:

■

Differential and single-ended I/O standards

■

3.3-V, 64- and 32-bit, 66- and 33-MHz PCI compliance

■

Joint Test Action Group (JTAG) boundary-scan test (BST) support

■

Output drive strength control

■

Weak pull-up resistors during configuration

■

Tri-state buffers

■

Bus-hold circuitry

■

Programmable pull-up resistors in user mode

■

Programmable input and output delays

■

Open-drain outputs

■

DQ and DQS I/O pins

■

REF

pins

Cyclone II device IOEs contain a bidirectional I/O buffer and three
registers for complete embedded bidirectional single data rate transfer.

Figure 2–20

shows the Cyclone II IOE structure. The IOE contains one

input register, one output register, and one output enable register. The
designer can use the input registers for fast setup times and output
registers for fast clock-to-output times. Additionally, the designer can use
the output enable (OE) register for fast clock-to-output enable timing. The
Quartus II software automatically duplicates a single OE register that
controls multiple output or bidirectional pins. Designers can use IOEs as
input, output, or bidirectional pins.

Altera Corporation

Preliminary

2–39

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Figure 2–21. Row I/O Block Connection to the Interconnect

Notes to

Figure 2–21

(1)

The 35 data and control signals consist of five data out lines,

io_dataout[4..0]

, five output enables,

io_coe[4..0]

, five input clock enables,

io_cce_in[4..0]

, five output clock enables,

io_cce_out[4..0]

five clocks,

io_cclk[4..0]

, five asynchronous clear signals,

io_caclr[4..0]

, and five synchronous clear

signals,

io_csclr[4..0]

(2)

Each of the five IOEs in the row I/O block can have two

io_datain

input (combinatorial or registered) inputs.

R4 & R24 Interconnects

C4 Interconnects

I/O Block Local

Interconnect

35 Data and
Control Signals
from Logic Array (1)

io_datain0[4..0]
io_datain1[4..0]

(2)

io_clk[5..0]

Row I/O Block

Contains up to

Five IOEs

Direct Link

Interconnect

to Adjacent LAB

Direct Link

Interconnect

from Adjacent LAB

LAB Local
Interconnect

LAB

Row

I/O Block

2–40

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

I/O Structure & Features

Figure 2–22. Column I/O Block Connection to the Interconnect

Notes to

Figure 2–22

(1)

The 28 data and control signals consist of four data out lines,

io_dataout[3..0]

, four output enables,

io_coe[3..0]

, four input clock enables,

io_cce_in[3..0]

, four output clock enables,

io_cce_out[3..0]

four clocks,

io_cclk[3..0]

, four asynchronous clear signals,

io_caclr[3..0]

, and four synchronous clear

signals,

io_csclr[3..0]

(2)

Each of the four IOEs in the column I/O block can have two

io_datain

input (combinatorial or registered) inputs.

28 Data &

Control Signals

from Logic Array (1)

Column I/O
Block Contains
up to Four IOEs

I/O Block

Local Interconnect

io_datain0[3..0]
io_datain1[3..0] (2)

R4 & R24 Interconnects

LAB Local
Interconnect

C4 & C24 Interconnects

LAB

io_clk[5..0]

Column I/O Block

Altera Corporation

Preliminary

2–41

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

The pin’s

datain

signals can drive the logic array. The logic array drives

the control and data signals, providing a flexible routing resource. The
row or column IOE clocks,

io_clk[5..0]

, provide a dedicated routing

resource for low-skew, high-speed clocks. The global clock network
generates the IOE clocks that feed the row or column I/O regions (see

Figure 2–23

illustrates the signal paths through the I/O block.

Figure 2–23. Signal Path through the I/O Block

Each IOE contains its own control signal selection for the following
control signals:

ce_in

ce_out

aclr

preset

sclr

preset

clk_in

, and

clk_out

Figure 2–24

illustrates the control signal

selection.

Row or Column

io_clk[5..0]

io_datain0

io_datain1

io_dataout

io_coe

ce_in

ce_out

io_cce_in

aclr/preset

io_cce_out

sclr

io_caclr

clk_in

io_cclk

clk_out

dataout

Data and

Control

Signal

Selection

IOE

To Logic

Array

From Logic

Array

To Other
IOEs

io_csclr

2–42

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

I/O Structure & Features

Figure 2–24. Control Signal Selection per IOE

In normal bidirectional operation, the designer can use the input register
for input data requiring fast setup times. The input register can have its
own clock input and clock enable separate from the

and output

registers. The designer can use the output register for data requiring fast
clock-to-output performance. The

output enable timing. The

and output register share the same clock

source and the same clock enable source from the local interconnect in the
associated LAB, dedicated I/O clocks, or the column and row
interconnects. All registers share

sclr

and

aclr

, but each register can

individually disable

sclr

and

aclr

Figure 2–25

shows the IOE in

bidirectional configuration.

clk_out

ce_in

clk_in

ce_out

aclr/preset

sclr/preset

Dedicated I/O
Clock [5..0]

Local
Interconnect

io_coe

io_caclr

Local
Interconnect

io_csclr

io_cce_out

io_cce_in

io_cclk

Altera Corporation

Preliminary

2–43

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Figure 2–25. Cyclone II IOE in Bidirectional I/O Configuration

The Cyclone II device IOE includes programmable delays to ensure zero
hold times, minimize setup times, or increase clock to output times.

A path in which a pin directly drives a register may require a
programmable delay to ensure zero hold time, whereas a path in which a
pin drives a register through combinatorial logic may not require the
delay. Programmable delays decrease input-pin-to-logic-array and IOE
input register delays. The Quartus II Compiler can program these delays
to automatically minimize setup time while providing a zero hold time.

Chip-Wide Reset

OE Register

CCIO

Optional
PCI Clamp

Column

or Row

Interconect

ioe_clk[5..0]

Input Register

Input Pin to

Input Register Delay

or Input Pin to

Logic Array Delay

Drive Strength Control

Open-Drain Output

Slew Control

sclr/preset

clkout

ce_out

aclr/prn

clkin

ce_in

Output

Pin Delay

Programmable
Pull-Up
Resistor

Bus Hold

PRN

CLRN

Output Register

PRN

CLRN

PRN

CLRN

CCIO

data_in0

data_in1

ENA

2–44

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

I/O Structure & Features

Programmable delays can increase the register-to-pin delays for output
registers.

Table 2–14

shows the programmable delays for Cyclone II

devices.

There are two paths in the IOE for an input to reach the logic array. Each
of the two paths can have a different delay. This allows the designer to
adjust delays from the pin to internal LE registers that reside in two
different areas of the device. The designer sets the two combinatorial
input delays by selecting different delays for two different paths under
the

Input delay from pin to internal cells logic

option in the Quartus II

software. However, if the pin uses the input register, one of delays will be
disregarded since the IOE only has two paths to internal logic. If the input
register is used, the IOE uses one input path. The other input path is then
available for the combinatorial path, and only one input delay
assignment is applied.

The IOE registers in each I/O block share the same source for clear or
preset. The designer can program preset or clear for each individual IOE,
but both features cannot be used simultaneously. The designer can also
program the registers to power up high or low after configuration is
complete. If programmed to power up low, an asynchronous clear can
control the registers. If programmed to power up high, an asynchronous
preset can control the registers. This feature prevents the inadvertent
activation of another device’s active-low input upon power up. If one
register in an IOE uses a preset or clear signal then all registers in the IOE
must use that same signal if they require preset or clear. Additionally a
synchronous reset signal is available to the designer for the IOE registers.

External Memory Interfacing

Cyclone II devices support a broad range of external memory interfaces
such as SDR SDRAM, DDR SDRAM, DDR2 SDRAM, and QDRII SRAM
external memories. Cyclone II devices feature dedicated high-speed
interfaces that transfer data between external memory devices at up to
167 MHz/333 Mbps for DDR and DDR2 SDRAM devices and
167 MHz/667 Mbps for QDRII SRAM devices. The programmable DQS
delay chain allows designers to fine tune the phase shift for the input
clocks or strobes to properly align clock edges as needed to capture data.

Table 2–14. Cyclone II Programmable Delay Chain

Programmable Delays

Quartus II Logic Option

Input pin to logic array delay

Input delay from pin to internal cells

Input pin to input register delay

Input delay from pin to input register

Output pin delay

Delay from output register to output pin

Altera Corporation

Preliminary

2–45

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

In Cyclone II devices, all the I/O banks support SDR and DDR SDRAM
memory up to 167 MHz/333 Mbps. All I/O banks support DQS signals
with the DQ bus modes of ×8/×9, or ×16/×18.

Table 2–15

shows the

external memory interfaces supported in Cyclone II devices.

Cyclone II devices use data (DQ), data strobe (DQS), and clock pins to
interface with external memory.

Figure 2–26

shows the DQ and DQS pins

in the ×8/×9 mode.

Table 2–15. External Memory Support in Cyclone II Devices

Memory Standard

I/O Standard

Maximum Bus

Width

Maximum Clock

Rate Supported

(MHz)

Maximum Data

Rate Supported

(Mbps)

SDR SDRAM

LVTTL

167

DDR SDRAM

SSTL-2 class I

167

333

SSTL-2 class II

133

267

DDR2 SDRAM

SSTL-18 class I

167

333

SSTL-18 class II

125

250

1.8-V HSTL class I

167

668

1.8-V HSTL class II

100

400

Notes to

Table 2–15

(1)

The data rate is for designs using the Clock Delay Control circuitry.

(2)

The I/O standards are supported on all the I/O banks of the Cyclone II device.

(3)

The I/O standards are supported only on the I/O banks on the top and bottom of the Cyclone II device.

(4)

For maximum performance, Altera recommends using the 1.8-V HSTL I/O standard because of higher I/O drive
strength. QDRII SRAM devices also support the 1.5-V HSTL I/O standard.

2–46

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

I/O Structure & Features

Figure 2–26. Cyclone II Device DQ & DQS Groups in ×8/×9 Mode

Notes (1)

Notes to

Figure 2–26

(1)

Each DQ group consists of a DQS pin, DM pin, and up to nine DQ pins.

(2)

This is an idealized pin layout. For actual pin layout, refer to the pin table.

Cyclone II devices support the data strobe or read clock signal (DQS)
used in DDR and DDR2 SDRAM. Cyclone II devices can use either
bidirectional data strobes or unidirectional read clocks. The dedicated
external memory interface in Cyclone II devices also includes
programmable delay circuitry that can shift the incoming DQS signals to
center align the DQS signals within the data window.

The DQS signal is usually associated with a group of data (DQ) pins. The
phase-shifted DQS signals drive the global clock network, which is used
to clock the DQ signals on internal LE registers.

Table 2–16

shows the number of DQ pin groups per device.

DQ Pins

DQS Pin

DM Pin

DQ Pins

(2)

Table 2–16. Cyclone II DQS & DQ Bus Mode Support (Part 1 of 2)

Device

Package

Number of ×8

Groups

Number of ×9

Groups

Number of ×16

Groups

Number of ×18

Groups

EP2C5

144-pin TQFP

208-pin PQFP

EP2C8

144-pin TQFP

208-pin PQFP

256-pin FineLine BGA

EP2C20

256-pin FineLine BGA

484-pin FineLine BGA

EP2C35

484-pin FineLine BGA

672-pin FineLine BGA

Altera Corporation

Preliminary

2–47

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Designers can use any of the DQ pins for the parity pins in Cyclone II
devices. The Cyclone II device family supports parity in the ×8/×9, and
×16/×18 mode. There is one parity bit available per eight bits of data pins.

The data mask, DM, pins are required when writing to DDR SDRAM and
DDR2 SDRAM devices. A low signal on the DM pin indicates that the
write is valid. If the DM signal is high, the memory masks the DQ signals.
In Cyclone II devices, the DM pins are assigned and are the preferred
pins. Each group of DQS and DQ signals requires a DM pin.

When using the Cyclone II I/O banks to interface with the DDR memory,
at least one PLL with two clock outputs is needed to generate the system
and write clock. The system clock is used to clock the DQS write signals,
commands, and addresses. The write clock is shifted by –90° from the
system clock and is used to clock the DQ signals during writes.

Figure 2–27

illustrates DDR SDRAM interfacing from the I/O through

the dedicated circuitry to the logic array.

EP2C50

484-pin FineLine BGA

672-pin FineLine BGA

EP2C70

672-pin FineLine BGA

896-pin FineLine BGA

Notes to

Table 2–16

(1)

Numbers are preliminary until the devices are available.

(2)

EP2C5 and EP2C8 devices in the 144-pin TQFP package do not have any DQ pin groups in I/O bank 1.

Table 2–16. Cyclone II DQS & DQ Bus Mode Support (Part 2 of 2)

Note (1)

Device

Package

Number of ×8

Groups

Number of ×9

Groups

Number of ×16

Groups

Number of ×18

Groups

2–48

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

I/O Structure & Features

Figure 2–27. DDR SDRAM Interfacing

For more information on Cyclone II external memory interfaces, see the

External Memory Interfaces

chapter in Volume 1 of the

Cyclone II Device

Handbook

DQS

VCC

PLL

GND

clk

DataA

DataB

Resynchronizing
to System Clock

Global Clock

Clock Delay

Control Circuitry

-90˚ Shifted clk

Adjacent LAB LEs

Clock Control

Block

en/dis

Dynamic Enable/Disable

Circuitry

ENOUT

ena_register_mode

Altera Corporation

Preliminary

2–49

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Programmable Drive Strength

The output buffer for each Cyclone II device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL, LVCMOS,
SSTL-2 class I and II, SSTL-18 class I and II, HSTL-18 class I and II, and
HSTL-1.5 class I and II standards have several levels of drive strength that
the designer can control. Using minimum settings provides signal slew
rate control to reduce system noise and signal overshoot.

Table 2–17

shows the possible settings for the I/O standards with drive strength
control.

Table 2–17. Programmable Drive Strength (Part 1 of 2)

I/O Standard

Current Strength Setting (mA)

Top & Bottom I/O Pins

Side I/O Pins

LVTTL (3.3 V)

LVCMOS (3.3 V)

LVTTL/LVCMOS (2.5 V)

LVTTL/LVCMOS (1.8 V)

2–50

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

I/O Structure & Features

LVCMOS (1.5 V)

SSTL-2 class I

SSTL-2 class II

SSTL-18 class I

SSTL-18 class II

HSTL-18 class I

HSTL-18 class II

HSTL-15 class I

HSTL-15 class II

Table 2–17. Programmable Drive Strength (Part 2 of 2)

I/O Standard

Current Strength Setting (mA)

Top & Bottom I/O Pins

Side I/O Pins

Altera Corporation

Preliminary

2–51

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Open-Drain Output

Cyclone II devices provide an optional open-drain (equivalent to an
open-collector) output for each I/O pin. This open-drain output enables
the device to provide system-level control signals (that is, interrupt and
write-enable signals) that can be asserted by any of several devices.

Slew Rate Control

Slew rate control is performed by using programmable output drive
strength.

Bus Hold

Each Cyclone II device user I/O pin provides an optional bus-hold
feature. The bus-hold circuitry can hold the signal on an I/O pin at its
last-driven state. Since the bus-hold feature holds the last-driven state of
the pin until the next input signal is present, an external pull-up or pull-
down resistor is not necessary to hold a signal level when the bus is tri-
stated.

The bus-hold circuitry also pulls undriven pins away from the input
threshold voltage where noise can cause unintended high-frequency
switching. The designer can select this feature individually for each I/O
pin. The bus-hold output will drive no higher than V

CCIO

to prevent

overdriving signals.

If the bus-hold feature is enabled, the device cannot use the
programmable pull-up option. Disable the bus-hold feature
when the I/O pin is configured for differential signals. Bus hold
circuitry is not available on the dedicated clock pins.

The bus-hold circuitry is only active after configuration. When going into
user mode, the bus-hold circuit captures the value on the pin present at
the end of configuration.

The bus-hold circuitry uses a resistor with a nominal resistance (R

) of

approximately 7 k

Ω

to pull the signal level to the last-driven state. Refer

to the

DC Characteristics & Timing Specifications

chapter in Volume 1 of the

Cyclone II Device Handbook

for the specific sustaining current for each

CCIO

voltage level driven through the resistor and overdrive current

used to identify the next driven input level.

2–52

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

I/O Structure & Features

Programmable Pull-Up Resistor

Each Cyclone II device I/O pin provides an optional programmable pull-
up resistor during user mode. If the designer enables this feature for an
I/O pin, the pull-up resistor (typically 25 k

Ω

) holds the output to the

CCIO

level of the output pin’s bank.

If the programmable pull-up is enabled, the device cannot use
the bus-hold feature. The programmable pull-up resistors are
not supported on the dedicated configuration, JTAG, and
dedicated clock pins.

Advanced I/O Standard Support

shows the I/O standards supported by Cyclone II devices and

which I/O pins support them.

Table 2–18. Cyclone II Supported I/O Standards & Constraints (Part 1 of 2)

I/O Standard

Type

CCIO

Level

Top & Bottom

I/O Pins

Side I/O Pins

Input

Output

CLK,

DQS

User I/O

Pins

CLK,

DQS

PLL_OUT

User I/O

Pins

3.3-V LVTTL and LVCMOS

Single ended

3.3 V/

2.5 V

3.3 V

2.5-V LVTTL and LVCMOS

Single ended

3.3 V/

2.5 V

1.8-V LVTTL and LVCMOS

Single ended

1.8 V/

1.5 V

1.8 V

1.5-V LVCMOS

Single ended

1.8 V/

1.5 V

SSTL-2 class I

Voltage
referenced

2.5 V

SSTL-2 class II

Voltage
referenced

2.5 V

SSTL-18 class I

Voltage
referenced

1.8 V

SSTL-18 class II

Voltage
referenced

1.8 V

HSTL-18 class I

Voltage
referenced

1.8 V

HSTL-18 class II

Voltage
referenced

1.8 V

Altera Corporation

Preliminary

2–53

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

HSTL-15 class I

Voltage
referenced

1.5 V

HSTL-15 class II

Voltage
referenced

1.5 V

PCI and PCI-X

Single ended

3.3 V

Differential SSTL-2 class I or
class II

Pseudo
differential

2.5 V

Differential SSTL-18 class I
or class II

Pseudo
differential

1.8 V

1.8 V

Differential HSTL-15 class I
or class II

Pseudo
differential

1.5 V

1.5 V

Differential HSTL-18 class I
or class II

Pseudo
differential

1.8 V

1.8 V

LVDS

Differential

2.5 V

RSDS and mini-LVDS

Differential

2.5 V

Differential

3.3 V/
2.5 V/
1.8 V/
1.5 V

Notes to

Table 2–18

(1)

These pins support SSTL-18 class II and 1.8- and 1.5-V HSTL class II inputs.

(2)

PCI-X does not meet the IV curve requirement at the linear region. PCI-clamp diode is not available on top and
bottom I/O pins.

(3)

Pseudo-differential HSTL and SSTL outputs use two single-ended outputs with the second output programmed
as inverted. Pseudo-differential HSTL and SSTL inputs treat differential inputs as two single-ended HSTL and
SSTL inputs and only decode one of them.

(4)

This I/O standard is not supported on these I/O pins.

(5)

This I/O standard is only supported on the dedicated clock pins.

(6)

PLL_OUT

does not support differential SSTL-18 class II and differential 1.8 and 1.5-V HSTL class II.

(7)

mini-LVDS and RSDS are only supported on output pins.

(8)

LVPECL is only supported on clock inputs.

Table 2–18. Cyclone II Supported I/O Standards & Constraints (Part 2 of 2)

I/O Standard

Type

CCIO

Level

Top & Bottom

I/O Pins

Side I/O Pins

Input

Output

CLK,

DQS

User I/O

Pins

CLK,

DQS

PLL_OUT

User I/O

Pins

2–54

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

I/O Structure & Features

For more information on Cyclone II supported I/O standards, see the

Selectable I/O Standards in Cyclone II Devices

chapter in Volume 1 of the

Cyclone II Device Handbook

High-Speed Differential Interfaces

Cyclone II devices can transmit and receive data through LVDS signals at
a data rate of up to 622 Mbps and 805 Mbps, respectively. For the LVDS
transmitter and receiver, the Cyclone II device’s input and output pins
support serialization and deserialization through internal logic.

The reduced swing differential signaling (RSDS) and mini-LVDS
standards are derivatives of the LVDS standard. The RSDS and mini-
LVDS I/O standards are similar in electrical characteristics to LVDS, but
have a smaller voltage swing and therefore provide increased power
benefits and reduced electromagnetic interference (EMI). Cyclone II
devices support the RSDS and mini-LVDS I/O standards at data rates up
to 170 Mbps at the transmitter. For RSDS and mini-LVDS, the maximum
internal clock frequency is 85 MHz.

A subset of pins in each I/O bank (on both rows and columns) support
the high-speed I/O interface. The dual-purpose LVDS pins require an
external-resistor network at the transmitter channels in addition to 100-

Ω

termination resistors on receiver channels. These pins do not contain
dedicated serialization or deserialization circuitry. Therefore, internal
logic performs serialization and deserialization functions.

Cyclone II pin tables list the pins that support the high-speed I/O
interface. The number of LVDS channels supported in each device family
member is listed in

Table 2–19

Table 2–19. Cyclone II Device LVDS Channels (Part 1 of 2)

Device

Pin Count

Number of LVDS

Channels

EP2C5

144

33 (35)

208

58 (60)

EP2C8

144

31 (33)

208

55 (57)

256

77 (79)

EP2C20

256

56 (60)

484

132 (136)

EP2C35

484

135(139)

672

205 (209)

Altera Corporation

Preliminary

2–55

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

You can use I/O pins and internal logic to implement a high-speed I/O
receiver and transmitter in Cyclone II devices. Cyclone II devices do not
contain dedicated serialization or deserialization circuitry. Therefore,
shift registers, internal PLLs, and IOEs are used to perform serial-to-
parallel conversions on incoming data and parallel-to-serial conversion
on outgoing data.

The maximum internal clock frequency for a receiver is 402.5 MHz. The
maximum internal clock frequency for a transmitter is 311 MHz. The
maximum data rate of 805 Mbps is only achieved when DDIO registers
are used. The LVDS standard does not require an input reference voltage,
but it does require a 100-

Ω

termination resistor between the two signals

at the input buffer. An external resistor network is required on the
transmitter side.

For more information on Cyclone II differential I/O interfaces, see the

High-Speed Differential Interfaces in Cyclone II Devices

chapter in Volume 1

of the

Cyclone II Device Handbook

Series On-Chip Termination

On-chip termination helps to prevent reflections and maintain signal
integrity. This also minimizes the need for external resistors in high pin
count ball grid array (BGA) packages. Cyclone II devices provide I/O
driver on-chip impedance matching and on-chip series termination for
single-ended outputs and bidirectional pins.

EP2C50

484

122 (126)

672

193 (197)

EP2C70

672

164 (168)

896

261 (265)

Table 2–19

(1)

The first number represents the number of bidirectional I/O pins which can be
used as inputs or outputs. The number in parenthesis includes dedicated clock
input pin pairs which can only be used as inputs.

Table 2–19. Cyclone II Device LVDS Channels (Part 2 of 2)

Device

Pin Count

Number of LVDS

Channels

(1)

2–56

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

I/O Structure & Features

Cyclone II devices support driver impedance matching to the impedance
of the transmission line, typically 25 or 50

Ω

. When used with the output

drivers, on-chip termination sets the output driver impedance to 25 or
50

Ω

. Cyclone II devices also support I/O driver series termination

= 50

Ω

) for SSTL-2 and SSTL-18.

Table 2–20

lists the I/O standards

that support impedance matching and series termination.

The recommended frequency range of operation is pending
silicon characterization.

On-chip series termination can be supported on any I/O bank. V

CCIO

and

REF

must be compatible for all I/O pins in order to enable on-chip series

termination in a given I/O bank. I/O standards that support different R

values can reside in the same I/O bank as long as their V

CCIO

and V

REF

are

not conflicting.

When using on-chip series termination, programmable drive
strength is not available.

Impedance matching is implemented using the capabilities of the output
driver and is subject to a certain degree of variation, depending on the
process, voltage and temperature. The actual tolerance is pending silicon
characterization.

Table 2–20. I/O Standards Supporting Series Termination

I/O Standards

Target R

(

Ω

)

CCIO

(V)

3.3-V LVTTL and LVCMOS

3.3

2.5-V LVTTL and LVCMOS

2.5

1.8-V LVTTL and LVCMOS

1.8

SSTL-2 class I

2.5

SSTL-18 class I

1.8

Notes to

Table 2–20

(1)

Supported conditions are junction temperature (T

) = 0° to 85° C and

CCIO

= V

CCIO

±50 mV.

(2)

These R

values are nominal values. Actual impedance will vary across process,

voltage, and temperature conditions. Tolerance is pending characterization.

Altera Corporation

Preliminary

2–57

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

I/O Banks

The I/O pins on Cyclone II devices are grouped together into I/O banks
and each bank has a separate power bus. EP2C5 and EP2C8 devices have
four I/O banks (see

Figure 2–28

), while EP2C20, EP2C35, EP2C50, and

EP2C70 devices have eight I/O banks (see

Figure 2–29

). Each device I/O

pin is associated with one I/O bank. To accommodate voltage-referenced
I/O standards, each Cyclone II I/O bank has a

VREF

bus. Each bank in

EP2C5, EP2C8, EP2C20, EP2C35, and EP2C50 devices supports two

VREF

pins and each bank of EP2C70 supports three

VREF

pins. When using the

VREF

pins, each

VREF

pin must be properly connected to the appropriate

voltage level. In the event these pins are not used as

VREF

pins, they may

be used as regular I/O pins.

The top and bottom I/O banks (banks 2 and 4 in EP2C5 and EP2C8
devices and banks 3, 4, 7, and 8 in EP2C20, EP2C35, EP2C50, and EP2C70
devices) support all I/O standards listed in

, except the

PCI/PCI-X I/O standards. The left and right side I/O banks (banks 1 and
3 in EP2C5 and EP2C8 devices and banks 1, 2, 5, and 6 in EP2C20, EP2C35,
EP2C50, and EP2C70 devices) support I/O standards listed in

except SSTL-18 class II, HSTL-18 class II, and HSTL-15 class II I/O
standards. See

for a complete list of supported I/O standards.

The top and bottom I/O banks (banks 2 and 4 in EP2C5 and EP2C8
devices and banks 3, 4, 7, and 8 in EP2C20, EP2C35, EP2C50, and EP2C70
devices) support DDR2 memory up to 167 MHz/333 Mbps and QDR
memory up to 167 MHz/668 Mbps. The left and right side I/O banks (1
and 3 of EP2C5 and EP2C8 devices and 1, 2, 5, and 6 of EP2C20, EP2C35,
EP2C50, and EP2C70 devices) only support SDR and DDR SDRAM
interfaces. All the I/O banks of the Cyclone II devices support SDR
memory up to 167 MHz/167 Mbps and DDR memory up to
167 MHz/333 Mbps.

2–58

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

I/O Structure & Features

Figure 2–28. EP2C5 & EP2C8 I/O Banks

Notes (1)

I/O Bank 2

I/O Bank 3

I/O Bank 4

I/O Bank 1

All I/O Banks Support

■

3.3-V LVTTL/LVCMOS

■

2.5-V LVTTL/LVCMOS

■

1.8-V LVTTL/LVCMOS

■

1.5-V LVCMOS

■

LVDS

■

RSDS

■

mini-LVDS

■

LVPECL

■

SSTL-2 Class I and II

■

SSTL-18 Class I

■

HSTL-18 Class I

■

HSTL-15 Class I

■

Differential SSTL-2

■

Differential SSTL-18

■

Differential HSTL-18

■

Differential HSTL-15

I/O Bank 3
Also Supports the
3.3-V PCI & PCI-X
I/O Standards

I/O Bank 1

Also Supports the

3.3-V PCI & PCI-X

I/O Standards

Individual

Power Bus

I/O Bank 2 Also Supports

the SSTL-18 Class II,

HSTL-18 Class II, & HSTL-15

Class II I/O Standards

I/O Bank 4 Also Supports

the SSTL-18 Class II,

HSTL-18 Class II, & HSTL-15

Class II I/O Standards

Altera Corporation

Preliminary

2–59

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Figure 2–29. EP2C20, EP2C35, EP2C50 & EP2C70 I/O Banks

Notes to

(1)

This is a top view of the silicon die.

(2)

This is a graphic representation only. Refer to the pin list and the Quartus II software for exact pin locations.

Each I/O bank has its own

VCCIO

pins. A single device can support

1.5-V, 1.8-V, 2.5-V, and 3.3-V interfaces; each individual bank can support
a different standard with different I/O voltages. Each bank also has dual-
purpose

VREF

pins to support any one of the voltage-referenced

standards (e.g., SSTL-2) independently. If an I/O bank does not use
voltage-referenced standards, the

VREF

pins are available as user I/O

pins.

I/O Bank 2

Regular I/O Block

Bank 8

Regular I/O Block

Bank 7

I/O Bank 3

I/O Bank 4

I/O Bank 1

I/O Bank 5

I/O Bank 6

Individual

Power Bus

All I/O Banks Support

■

3.3-V LVTTL/LVCMOS

■

2.5-V LVTTL/LVCMOS

■

1.8-V LVTTL/LVCMOS

■

1.5-V LVCMOS

■

LVDS

■

RSDS

■

mini-LVDS

■

SSTL-2 Class I and II

■

SSTL-18 Class I

■

HSTL-18 Class I

■

HSTL-15 Class I

I/O Banks 3 & 4 Also Support

the SSTL-18 Class II,

HSTL-18 Class II, & HSTL-15

Class II I/O Standards

I/O Banks 7 & 8 Also Support

the SSTL-18 Class II,

HSTL-18 Class II, & HSTL-15

Class II I/O Standards

I/O Banks 5 & 6 Also
Support the 3.3-V PCI
& PCI-X I/O Standards

I/O Banks 1 & 2 Also

Support the 3.3-V PCI

& PCI-X I/O Standards

2–60

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

I/O Structure & Features

Each I/O bank can support multiple standards with the same V

CCIO

for

input and output pins. For example, when V

CCIO

is 3.3-V, a bank can

support LVTTL, LVCMOS, and 3.3-V PCI for inputs and outputs. Voltage-
referenced standards can be supported in an I/O bank using any number
of single-ended or differential standards as long as they use the same V

REF

and a compatible V

CCIO

value.

MultiVolt I/O Interface

The Cyclone II architecture supports the MultiVolt I/O interface feature,
which allows Cyclone II devices in all packages to interface with systems
of different supply voltages. Cyclone II devices have one set of V

pins

(

VCCINT

) that power the internal device logic array and input buffers that

use the LVPECL, LVDS, HSTL, or SSTL I/O standards. Cyclone II devices
also have four or eight sets of VCC pins (

VCCIO

) that power the I/O

output drivers and input buffers that use the LVTTL, LVCMOS, or PCI
I/O standards.

The Cyclone II

VCCINT

pins must always be connected to a 1.2-V power

supply. If the V

CCINT

level is 1.2 V, then input pins are 1.5-V, 1.8-V, 2.5-V,

and 3.3-V tolerant. The

VCCIO

pins can be connected to either a 1.5-V,

1.8-V, 2.5-V, or 3.3-V power supply, depending on the output
requirements. The output levels are compatible with systems of the same
voltage as the power supply (i.e., when

VCCIO

pins are connected to a

1.5-V power supply, the output levels are compatible with 1.5-V systems).
When

VCCIO

pins are connected to a 3.3-V power supply, the output high

is 3.3-V and is compatible with 3.3-V systems.

Table 2–21

summarizes

Cyclone II MultiVolt I/O support.

Table 2–21. Cyclone II MultiVolt I/O Support (Part 1 of 2)

CCIO

(V)

Input Signal

Output Signal

1.5 V

1.8 V

2.5 V

3.3 V

1.5 V

1.8 V

2.5 V

3.3 V

1.5

1.8

2.5

Altera Corporation

Preliminary

2–61

November 2004

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

3.3

(6)

Notes to

Table 2–21

(1)

The PCI clamping diode must be disabled to drive an input with voltages higher than V

CCIO

(2)

When V

CCIO

= 1.5-V or 1.8-V and a 2.5-V or 3.3-V input signal feeds an input pin, higher pin leakage current is

expected.

(3)

When V

CCIO

= 1.8-V, a Cyclone II device can drive a 1.5-V device with 1.8-V tolerant inputs.

(4)

When V

CCIO

= 3.3-V and a 2.5-V input signal feeds an input pin or when VCCIO = 1.8-V and a 1.5-V input signal

feeds an input pin, the V

CCIO

supply current will be slightly larger than expected. The reason for this increase is

that the input signal level does not drive to the V

CCIO

rail, which causes the input buffer to not completely shut off.

(5)

When V

CCIO

= 2.5-V, a Cyclone II device can drive a 1.5-V or 1.8-V device with 2.5-V tolerant inputs.

(6)

When V

CCIO

= 3.3-V, a Cyclone II device can drive a 1.5-V, 1.8-V, or 2.5-V device with 3.3-V tolerant inputs.

Table 2–21. Cyclone II MultiVolt I/O Support (Part 2 of 2)

Note (1)

CCIO

(V)

Input Signal

Output Signal

1.5 V

1.8 V

2.5 V

3.3 V

1.5 V

1.8 V

2.5 V

3.3 V

Altera Corporation

3–1

November 2004

Preliminary

Chapter 3. Configuration &

Testing

IEEE Std. 1149.1
(JTAG) Boundary
Scan Support

All Cyclone

™

II devices provide JTAG BST circuitry that complies with

the IEEE Std. 1149.1. JTAG boundary-scan testing can be performed either
before or after, but not during configuration. Cyclone II devices can also
use the JTAG port for configuration with the Quartus

II software or

hardware using either Jam Files (

.jam

) or Jam Byte-Code Files (

.jbc

Cyclone II devices support IOE I/O standard reconfiguration through the
JTAG BST chain. The JTAG chain can update the I/O standard for all
input and output pins any time before or during user mode through the

CONFIG_IO

instruction. Designers can use this capability for JTAG

testing before configuration when some of the Cyclone II pins drive or
receive from other devices on the board using voltage-referenced
standards. Since the Cyclone II device might not be configured before
JTAG testing, the I/O pins may not be configured for appropriate
electrical standards for chip-to-chip communication. Programming the
I/O standards via JTAG allows designers to fully test I/O connections to
other devices.

For information on I/O reconfiguration, see

MorphIO: An I/O

Reconfiguration Solution for Altera Devices White Paper

A device operating in JTAG mode uses four required pins:

TDI

TDO

TMS

and

TCK

. The

TCK

pin has an internal weak pull-down resister, while the

TDI

and

TMS

pins have weak internal pull-up resistors. The

TDO

output

pin and all JTAG input pin voltage is determined by the V

CCIO

of the bank

where it resides. The bank V

CCIO

selects whether the JTAG inputs are 1.5-,

1.8-, 2.5-, or 3.3-V compatible.

CII51003-1.1

3–2

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

IEEE Std. 1149.1 (JTAG) Boundary Scan Support

Cyclone II devices also use the JTAG port to monitor the logic operation
of the device with the SignalTap

II embedded logic analyzer. Cyclone II

devices support the JTAG instructions shown in

Table 3–1

Table 3–1. Cyclone II JTAG Instructions (Part

of 2)

JTAG Instruction

Instruction Code

Description

SAMPLE/PRELOAD

00 0000 0101

Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial
data pattern to be output at the device pins. Also used by the
SignalTap II embedded logic analyzer.

EXTEST

00 0000 1111

Allows the external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.

BYPASS

11 1111 1111

Places the 1-bit bypass register between the

TDI

and

TDO

pins,

which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation.

USERCODE

00 0000 0111

Selects the 32-bit

USERCODE

TDI

and

TDO

pins, allowing the

USERCODE

to be serially shifted

out of

TDO

IDCODE

00 0000 0110

Selects the

IDCODE

TDI

and

TDO

allowing the

IDCODE

to be serially shifted out of

TDO

HIGHZ

00 0000 1011

Places the 1-bit bypass register between the

TDI

and

TDO

pins,

which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation, while
tri-stating all of the I/O pins.

CLAMP

00 0000 1010

Places the 1-bit bypass register between the

TDI

and

TDO

pins,

which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation while
holding I/O pins to a state defined by the data in the boundary-scan
register.

ICR

instructions

Used when configuring a Cyclone II device via the JTAG port with
a USB Blaster

™

, ByteBlaster

™

II, MasterBlaster

™

ByteBlasterMV

™

download cable, or when using a Jam File or JBC

File via an embedded processor.

PULSE_NCONFIG

00 0000 0001

Emulates pulsing the

nCONFIG

pin low to trigger reconfiguration

even though the physical pin is unaffected.

Altera Corporation

Preliminary

3–3

November 2004

Cyclone II Device Handbook, Volume 1

Configuration & Testing

The Cyclone II device instruction register length is 10 bits and the

USERCODE

Tables 3–2

3–3

show the

boundary-scan register length and device

IDCODE

information for

Cyclone II devices.

CONFIG_IO

00 0000 1101

Allows configuration of I/O standards through the JTAG chain for
JTAG testing. Can be executed before, after, or during
configuration. Stops configuration if executed during configuration.
Once issued, the

CONFIG_IO

instruction will hold

nSTATUS

low

to reset the configuration device.

nSTATUS

is held low until the

device is reconfigured.

SignalTap II
instructions

Monitors internal device operation with the SignalTap II embedded
logic analyzer.

Table 3–1

(1)

Bus hold and weak pull-up resistor features override the high-impedance state of

HIGHZ

CLAMP

, and

EXTEST.

Table 3–1. Cyclone II JTAG Instructions (Part

of 2)

JTAG Instruction

Instruction Code

Description

Table 3–2. Cyclone II Boundary-Scan Register Length

Device

Boundary-Scan Register Length

EP2C5

450

EP2C8

597

EP2C20

969

EP2C35

1,449

EP2C50

1,374

EP2C70

1,890

Table 3–3. 32-Bit Cyclone II Device IDCODE (Part 1 of 2)

Device

IDCODE (32 Bits)

Version (4 Bits)

Part Number (16 Bits)

Manufacturer Identity (11 Bits)

LSB (1 Bit)

EP2C5

0000

0010 0000 1011 0001

000 0110 1110

EP2C8

0000

0010 0000 1011 0010

000 0110 1110

EP2C20

0000

0010 0000 1011 0011

000 0110 1110

EP2C35

0000

0010 0000 1011 0100

000 0110 1110

3–4

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

IEEE Std. 1149.1 (JTAG) Boundary Scan Support

Figure 3–1

shows the timing requirements for the JTAG signals.

Figure 3–1. Cyclone II JTAG Waveform

EP2C50

0000

0010 0000 1011 0101

000 0110 1110

EP2C70

0000

0010 0000 1011 0110

000 0110 1110

Notes to

Table 3–3

(1)

The most significant bit (MSB) is on the left.

(2)

The IDCODE’s least significant bit (LSB) is always 1.

Table 3–3. 32-Bit Cyclone II Device IDCODE (Part 2 of 2)

Device

IDCODE (32 Bits)

(1)

Version (4 Bits)

Part Number (16 Bits)

Manufacturer Identity (11 Bits)

LSB (1 Bit)

(2)

TDO

TCK

JPZX

JPCO

JPH

JPXZ

JCP

JPSU

JCL

JCH

TDI

TMS

Signal

to be

Captured

Signal

to be

Driven

JSZX

JSSU

JSH

JSCO

JSXZ

Altera Corporation

Preliminary

3–5

November 2004

Cyclone II Device Handbook, Volume 1

Configuration & Testing

Table 3–4

shows the JTAG timing parameters and values for Cyclone II

devices.

For more information on JTAG, see the

IEEE 1149.1 (JTAG) Boundary-Scan

Testing for Cyclone II Devices

chapter in the

Cyclone II Handbook

and

Jam

Programming & Test Language Specification

SignalTap II
Embedded Logic
Analyzer

Cyclone II devices support the SignalTap II embedded logic analyzer,
which monitors design operation over a period of time through the IEEE
Std. 1149.1 (JTAG) circuitry. A designer can analyze internal logic at speed
without bringing internal signals to the I/O pins. This feature is
particularly important for advanced packages, such as FineLine BGA

packages, because it can be difficult to add a connection to a pin during
the debugging process after a board is designed and manufactured.

For more information on the SignalTap II, see the

Signal Tap

chapter of

the

Quartus II Handbook, Volume 3

Table 3–4. Cyclone II JTAG Timing Parameters & Values

Symbol

Parameter

Min

Max

Unit

J C P

TCK

clock period

J C H

TCK

clock high time

J C L

TCK

clock low time

J P S U

JTAG port setup time

J P H

JTAG port hold time

J P C O

JTAG port clock to output

J P Z X

JTAG port high impedance to valid output

J P X Z

JTAG port valid output to high impedance

J S S U

Capture register setup time

J S H

Capture register hold time

J S C O

Update register clock to output

J S Z X

Update register high impedance to valid output

J S X Z

Update register valid output to high impedance

Notes to

Table 3–4

(1)

This information is preliminary.

(2)

This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins.
For 1.8-V LVTTL/LVCMOS and 1.5-V LVCMOS, the JTAG port and capture register clock setup time is 3 ns and
port clock to output time is 15 ns.

3–6

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Configuration

The logic, circuitry, and interconnects in the Cyclone II architecture are
configured with CMOS SRAM elements. Cyclone II devices are
reconfigurable and are 100% tested prior to shipment. As a result, the
designer does not have to generate test vectors for fault coverage
purposes, and can instead focus on simulation and design verification. In
addition, the designer does not need to manage inventories of different
ASIC designs. Cyclone II devices can be configured on the board for the
specific functionality required.

Cyclone II devices are configured at system power-up with data stored in
an Altera configuration device or provided by a system controller. The
Cyclone II device’s optimized interface allows the device to act as
controller in an active serial configuration scheme with EPCS serial
configuration devices. The serial configuration device can be
programmed via SRunner, the ByteBlaster II or USB Blaster download
cable, the Altera Programming Unit (APU), or third-party programmers.

In addition to EPCS serial configuration devices, Altera offers in-system
programmability (ISP)-capable configuration devices that can configure
Cyclone II devices via a serial data stream using the Passive serial (PS)
configuration mode. The PS interface also enables microprocessors to
treat Cyclone II devices as memory and configure them by writing to a
virtual memory location, simplifying reconfiguration. After a Cyclone II
device has been configured, it can be reconfigured in-circuit by resetting
the device and loading new configuration data. Real-time changes can be
made during system operation, enabling innovative reconfigurable
applications.

Operating
Modes

The Cyclone II architecture uses SRAM configuration elements that
require configuration data to be loaded each time the circuit powers up.
The process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
configuration, the device resets registers, enables I/O pins, and begins to
operate as a logic device. Together, the configuration and initialization
processes are called command mode. Normal device operation is called
user mode.

SRAM configuration elements allow Cyclone II devices to be
reconfigured in-circuit by loading new configuration data into the device.
With real-time reconfiguration, the device is forced into command mode
with the

nCONFIG

pin. The configuration process loads different

configuration data, reinitializes the device, and resumes user-mode
operation. Designers can perform in-field upgrades by distributing new
configuration files within the system or remotely.

Altera Corporation

Preliminary

3–7

November 2004

Cyclone II Device Handbook, Volume 1

Configuration & Testing

A built-in weak pull-up resistor pulls all user I/O pins to V

CCIO

before

and during device configuration.

The configuration pins support 1.5-V/1.8-V or 2.5-V/3.3-V I/O
standards. The voltage level of the configuration output pins is
determined by the V

CCIO

of the bank where the pins reside. The bank

CCIO

selects whether the configuration inputs are 1.5-V, 1.8-V, 2.5-V, or

3.3-V compatible.

Configuration
Schemes

Designers can load the configuration data for a Cyclone II device with
one of three configuration schemes (see

Table 3–5

), chosen on the basis of

the target application. Designers can use a configuration device,
intelligent controller, or the JTAG port to configure a Cyclone II device. A
low-cost configuration device can automatically configure a Cyclone II
device at system power-up.

Multiple Cyclone II devices can be configured in any of the three
configuration schemes by connecting the configuration enable (

nCE

) and

configuration enable output (

nCEO

) pins on each device.

For more information on configuration, see the

Configuring Cyclone II

Devices

chapter of the

Cyclone II Handbook, Volume 2

Cyclone II
Automated
Single Event
Upset Detection

Cyclone II devices offer on-chip circuitry for automated checking of
single event upset (SEU) detection. Some applications that require the
device to operate error free at high elevations or in close proximity to
earth's North or South Pole will require periodic checks to ensure
continued data integrity. The error detection cyclic redundancy check
(CRC) feature controlled by the

Device & Pin Options

dialog box in the

Quartus II software uses a 32-bit CRC circuit to ensure data reliability and
is one of the best options for mitigating SEU.

Table 3–5. Data Sources for Configuration

Configuration

Scheme

Data Source

Active serial (AS)

Low-cost serial configuration device

Passive serial (PS) Enhanced or EPC2 configuration device, MasterBlaster, ByteBlasterMV, ByteBlaster II or

USB Blaster download cable, or serial data source

JTAG

MasterBlaster, ByteBlasterMV, ByteBlaster II or USB Blaster download cable or a
microprocessor with a Jam or JBC file

3–8

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Cyclone II Automated Single Event Upset Detection

Designers can implement the error detection CRC feature with existing
circuitry in Cyclone II devices, eliminating the need for external logic. For
Cyclone II devices, the CRC is computed by the device during
configuration and checked against an automatically computed CRC
during normal operation. The

CRC_ERROR

pin reports a soft error when

configuration SRAM data is corrupted, triggering device reconfiguration.

Custom-Built Circuitry

Dedicated circuitry in the Cyclone II devices performs error detection
automatically. This error detection circuitry in Cyclone II devices
constantly checks for errors in the configuration SRAM cells while the
device is in user mode. Designers can monitor one external pin for the
error and use it to trigger a re-configuration cycle. The designer can select
the desired time between checks by adjusting a built-in clock divider.

Software Interface

In the Quartus II software version 4.1 and later, designers can turn on the
automated error detection CRC feature in the Device & Pin Options
dialog box. This dialog box allows you to enable the feature and set the
internal frequency of the CRC checker between 400 kHz to 100 MHz. This
controls the rate that the CRC circuitry verifies the internal configuration
SRAM bits in the FPGA device.

For more information on CRC, refer to the

Error Detection Using CRC in

Altera FPGAs

Application Note.

Altera Corporation

4–1

June 2004

Preliminary

Chapter 4. Hot Socketing,

ESD & Power-On Reset

Introduction

Cyclone™ II devices offer hot socketing (also known as hot plug-in, hot
insertion, or hot swap) and power sequencing support without the use of
any external devices. Designers can insert or remove a Cyclone II board
in a system during system operation without causing undesirable effects
to the board or to the running system bus.

The hot-socketing feature lessens the board design difficulty when using
Cyclone II devices on printed circuit boards (PCBs) that also contain a
mixture of 3.3-, 2.5-, 1.8-, and 1.5-V devices. With the Cyclone II
hot-socketing feature, designers no longer need to ensure a proper
power-up sequence for each device on the board.

The Cyclone II hot-socketing feature provides:

■

Board or device insertion and removal without external components
or board manipulation

■

Support for any power-up sequence

■

Non-intrusive I/O buffers to system buses during hot insertion

This chapter also discusses the electro-static discharge (ESD) protection
and the power-on reset (POR) circuitry in Cyclone II devices. The POR
circuitry keeps the devices in the reset state until the V

is within

operating range.

Cyclone II Hot-
Socketing
Specifications

Cyclone II devices offer hot-socketing capability with all three features
listed above without any external components or special design
requirements. The hot-socketing feature in Cyclone II devices offers the
following:

■

Designers can device before power-up without any damage to the
device itself.

■

I/O pins remain tri-stated during power-up. The device does not
drive out before or during power-up, thereby affecting other buses in
operation.

■

There are no internal current paths from I/O pins to V

CCIO

or V

CCINT

power supplies. Signals driven in on I/O pins will not power the
V

CCIO

or V

CCINT

power buses.

CII51004-1.0

4–2

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

June 2004

Cyclone II Hot-Socketing Specifications

Devices Can Be Driven before Power-Up

You can drive signals into the I/O pins, dedicated input pins, and
dedicated clock pins of Cyclone II devices before or during power-up or
power-down without damaging the device. Cyclone II devices support
any power-up or power-down sequence (V

CCIO

and V

CCINT

) to simplify

system level design.

I/O Pins Remain Tri-Stated during Power-Up

A device that does not support hot socketing may interrupt system
operation or cause contention by driving out before or during power-up.
In a hot-socketing situation, the Cyclone II device’s output buffers are
turned off during system power-up or power-down. The Cyclone II
device also does not drive out until the device is configured and has
attained proper operating conditions.

Signal Pins Do Not Have Internal Current Paths to V

CCIO

or V

CCINT

Power Supplies

Devices that do not support hot socketing can short power supplies
together when powered-up through the device signal pins. This irregular
power-up can damage both the driving and driven devices and can
disrupt card power-up.

Cyclone II devices do not have a current path from I/O pins, dedicated
input pins, or dedicated clock pins to the V

CCIO

or V

CCINT

pins before or

during power-up. A Cyclone II device may be inserted into (or removed
from) a powered-up system board without damaging or interfering with
system-board operation. When hot socketing, Cyclone II devices may
have a minimal effect on the signal integrity of the backplane.

You can power up or power down the V

CCIO

and V

CCINT

pins in

any sequence. The power supply ramp rates can range from
100 ns to 100 ms. Both V

supplies must power down within

100 ms of each other to prevent I/O pins from driving out.
During hot socketing, the I/O pin capacitance is less than 15 pF
and the clock pin capacitance is less than 20 pF. I/O pins can be
driven by active signals with a rise and fall time of 2 to 40 ns.
Cyclone II devices meet the following hot-socketing
specification.

The hot-socketing DC specification is: | I

IOPIN

| < 300

The hot-socketing AC specification is: | I

IOPIN

| < 8 mA

or | I

IOPIN

| > 8 mA for 10 ns or less

Altera Corporation

Preliminary

4–3

June 2004

Cyclone II Device Handbook, Volume 1

Hot Socketing, ESD & Power-On Reset

IOPIN

is the current at any user I/O pin on the device. The AC

specification has two requirements. The peak current during power-up or
power-down is < 8 mA. The peak current can exceed 8 mA for 10 ns or
less.

A possible concern for semiconductor devices in general regarding hot
socketing is the potential for latch-up. Latch-up can occur when electrical
subsystems are hot socketed into an active system. During hot socketing,
the signal pins may be connected and driven by the active system before
the power supply can provide current to the device’s V

and ground

planes. This condition can lead to latch-up and cause a low-impedance
path from V

to ground within the device. As a result, the device extends

a large amount of current, possibly causing electrical damage.

Altera has ensured by design of the I/O buffers and hot-socketing
circuitry, that Cyclone II devices are immune to latch-up during hot
socketing.

Hot-Socketing
Feature
Implementation
in Cyclone II
Devices

The hot-socketing feature turns off the output buffer during power up
(either V

CCINT

or V

CCIO

supplies) or power down. The hot-socket circuit

will generate an internal

HOTSCKT

signal when either V

CCINT

or V

CCIO

below the threshold voltage. Designs cannot use the

HOTSCKT

signal for

other purposes. The

HOTSCKT

signal will cut off the output buffer to

ensure that no DC current (except for weak pull-up leakage current) leaks
through the pin. When V

ramps up slowly, V

is still relatively low

even after the internal

POR

signal (not available to the FPGA fabric used

by customer designs) is released and the configuration is finished. The

CONF_DONE

nCEO

, and

nSTATUS

pins fail to respond, as the output

buffer cannot drive out because the hot-socketing circuitry will keep the
I/O pins tristated at this low V

voltage. Therefore, the hot-socketing

circuit has been removed on these configuration output or bidirectional
pins to ensure that they are able to operate during configuration. These
pins are expected to drive out during power-up and power-down
sequences.

Each I/O pin has the circuitry shown in

Figure 4–1

4–4

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

June 2004

Hot-Socketing Feature Implementation in Cyclone II Devices

Figure 4–1. Hot-Socketing Circuit Block Diagram for Cyclone II Devices

The POR circuit monitors V

CCINT

voltage level and keeps I/O pins tri-

stated until the device is in user mode. The weak pull-up resistor (R) from
the I/O pin to V

CCIO

keeps the I/O pins from floating. The voltage

tolerance control circuit permits the I/O pins to be driven by 3.3 V before
V

CCIO

and/or V

CCINT

are powered, and it prevents the I/O pins from

driving out when the device is not in user mode. The hot socket circuit
prevents I/O pins from internally powering V

CCIO

and V

CCINT

when

driven by external signals before the device is powered.

For more information, see the

DC Characteristics & Timing Specifications

chapter in Volume 1 of the

Cyclone II Device Handbook

for the value of the

internal weak pull-up resistors.

Figure 4–2

shows a transistor level cross section of the Cyclone II device

I/O buffers. This design ensures that the output buffers do not drive
when V

CCIO

is powered before V

CCINT

or if the I/O pad voltage is higher

than V

CCIO

. This also applies for sudden voltage spikes during hot

socketing. There is no current path from signal I/O pins to V

CCINT

CCIO

during hot socketing. The V

PAD

leakage current charges the voltage

tolerance control circuit capacitance.

Output Enable

Output

Hot Socket

Output

Pre-Driver

Voltage

Tolerance

Control

Power-On

Reset

Monitor

Weak

Pull-Up

Resistor

PAD

Input Buffer
to Logic Array

Altera Corporation

Preliminary

4–5

June 2004

Cyclone II Device Handbook, Volume 1

Hot Socketing, ESD & Power-On Reset

Figure 4–2. Transistor Level Diagram of FPGA Device I/O Buffers

Note to

Figure 4–2

(1)

This is the logic array signal or the larger of either the V

CCIO

or V

PAD

signal.

(2)

This is the larger of either the V

CCIO

or V

PAD

signal.

ESD Protection

Electro-static discharge (ESD) occurs when a charge moves from one
surface to another. ESD is a charge that moves between two surfaces with
different potentials. Destructive ESD can occur when the voltage
differential between the two surfaces is sufficiently high to break down
the dielectric strength of the medium separating the two surfaces. When
a static charge moves, it becomes a current that damages or destroys gate
oxide, metallization, and junctions.

ESD can occur in one of four ways: a charged body can touch an
integrated circuit (IC), a charged IC can touch a grounded surface, a
charged machine can touch an IC, or an electrostatic field can induce a
voltage across a dielectric sufficient to break it down.

ESD Testing

ESD can cause destructive damage to semiconductor IC devices like
FPGAs. The industry has introduced testing standards to minimize the
detrimental effects of ESD by ensuring all devices have undergone proper
standardized testing for quality and reliability. Three major ESD testing
methods exist for defining a passing level. Altera tests to human-body
model (HBM) and charged-device model (CDM). Machine model (MM)
testing is not typically performed because the results are similar to HBM
testing.

Logic Array

Signal

(1)

(2)

CCIO

PAD

n-well

p-well

p-substrate

4–6

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

June 2004

ESD Protection

Human-Body Model

The HBM simulates the action of a human body discharging accumulated
static charge through a device to ground. This model uses a series RC
network consisting of a 100-pF capacitor and a 1,500-

Ω

resistor. Altera

production devices meet the HBM ESD specifications of 1,000 V.

Machine Model

The MM simulates a machine discharging accumulated static charge
through a device to ground. This model uses a series RC network of a
200-pF capacitor, and nominal series resistance of less than 1

Ω

. The

output waveform usually is described in terms of peak current and
oscillating frequency for a given discharge voltage.

Charged-Device Model

The CDM simulates charging and discharging events that occur during
the manufacturing and testing processes. Potential for CDM events occur
when there is metal-to-metal contact in manufacturing. One example is a
device sliding down a shipping tube and hitting a metal surface. The
CDM addresses the possibility that a charge may reside on a lead frame
or package (e.g., from shipping) and discharge through a pin that
subsequently is grounded, causing damage to sensitive circuitry in the
path. The discharge current is limited only by the parasitic impedance
and capacitance of the device. CDM testing consists of charging a package
to a specified voltage, then discharging this voltage through the relevant
package leads. Altera production devices meet the CDM ESD
specification of 500 V.

ESD Circuitry

The CMOS output drivers in the I/O pins intrinsically provide ESD
protection. ESD voltage strikes can cause a positive voltage zap or a
negative voltage zap.

A positive ESD voltage zap occurs when a positive voltage is present on
an I/O pin because of an ESD charge event. This can cause the
N+ (drain)/P-substrate junction of the N-channel drain to break down
and the N+ (drain)/P-substrate/N+ (source) intrinsic bipolar transistor
to turn on to discharge ESD current from I/O pin to ground. The arrows
in

Figure 4–3

show the ESD current discharge path during a positive ESD

zap.

4–8

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

June 2004

Power-On Reset Circuitry

Figure 4–4. ESD Protection During Negative Voltage Zap

For the maximum specification of ESD protection, see the

Characteristics & Timing Specifications

chapter in Volume 1 of the

Cyclone II Device Handbook

. For more information on quality and

reliability, see the

Reliability Report

for Altera devices.

Power-On Reset
Circuitry

Cyclone II devices have a POR circuit to keep the whole device system in
reset state until the power supply voltage levels have stabilized during
power-up. The POR circuit monitors the V

CCINT

and V

CCIO

voltage levels

and tri-states all the user I/O pins while V

is ramping up until normal

user levels are reached. The POR circuitry also ensures that the V

CCIO

level of the two I/O banks that contains configuration pins (I/O banks 1
and 3 for EP2C5 and EP2C8, I/O banks 1 and 6 for EP2C20, EP2C35,
EP2C50, and EP2C70) as well as the logic array V

CCINT

voltage reach an

acceptable level before configuration is triggered. After the Cyclone II
device enters user mode, the POR circuit continues to monitor the V

CCINT

voltage level so that a brown-out condition during user mode can be
detected. If there is a V

CCINT

voltage sag below the POR trip point at

~600 to 700 mV during user mode, the POR circuit resets the device. If
there is a V

CCIO

voltage sag during user mode, the POR circuit will not

reset the device.

I/O

Gate

Source

Drain

Ground

I/O

N+

Gate

P-Substrate

Ground

Altera Corporation

5–1

November 2004

Preliminary

Chapter 5. DC

Characteristics & Timing

Specifications

Operating
Conditions

Cyclone™ II devices are offered in both commercial and industrial
grades. Commercial devices are offered in -6 (fastest), -7, -8 speed grades.

All parameter limits are representative of worst-case supply voltage and
junction temperature conditions. Unless otherwise noted, the parameter
values in this chapter apply to all Cyclone II devices. AC and DC
characteristics are specified using the same numbers for both commercial
and industrial grades. All parameters representing voltages are measured
with respect to ground.

Tables 5–1

through

5–4

provide information on absolute maximum

ratings.

Table 5–1. Cyclone II Device Absolute Maximum Ratings

Notes (1)

Symbol

Parameter

Conditions

Minimum

Maximum

Unit

CCINT

Supply voltage

With respect to ground

–0.5

1.8

CCIO

Output supply voltage

–0.5

4.6

DC input voltage

–0.5

4.6

OUT

DC output current, per pin

–25

STG

Storage temperature

No bias

–65

150

°C

Junction temperature

BGA packages under bias

125

°C

Notes to

Table 5–1

(1)

Conditions beyond those listed in this table will cause permanent damage to a device. These are stress ratings only.
Functional operation at these levels or any other conditions beyond those specified in this chapter is not implied.
Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse
affects on the device reliability.

(2)

See the

Operating Requirements for Altera Devices Data Sheet

for more information.

CII51005-1.1

5–2

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Operating Conditions

Table 5–2

specifies the recommended operating conditions for Cyclone II

devices. It shows the allowed voltage ranges for V

CCINT

, V

CCIO

, and the

operating junction temperature (T

). The LVTTL and LVCMOS inputs are

CCIO

only. The LVPECL input buffers on dedicated clock

pins are powered by V

CCINT

. The SSTL, HSTL, LVDS input buffers are

CCINT

and V

CCIO

Table 5–2. Recommended Operating Conditions

Symbol

Parameter

Conditions

Minimum

Maximum

Unit

CCINT

Supply voltage for internal
logic and input buffers

1.15

1.25

CCIO

Supply voltage for output
buffers, 3.3-V operation

3.00

Supply voltage for output
buffers, 2.5-V operation

2.375

2.625

Supply voltage for output
buffers, 1.8-V operation

1.71

1.89

Supply voltage for output
buffers, 1.5-V operation

1.4

1.6

Operating junction
temperature

For commercial use

°C

For industrial use

–40

100

°C

Notes to

Table 5–2

(1)

The maximum V

(both V

CCIO

and V

CCINT

) rise time is 100 ms, and V

must rise monotonically.

(2)

The V

CCIO

range given here spans the lowest and highest operating voltages of all supported I/O standards. The

recommended V

CCIO

range specific to each of the single-ended I/O standards is given in

Table 5–6

, and those

specific to the differential standards is given in

Table 5–8

(3)

The minimum and maximum values of 3.0 V and 3.6 V, respectively, for V

CCIO

only applies to the PCI and PCI-X

I/O standards. See

Table 5–6

for the voltage range of other I/O standards.

(4)

Contact Altera Applications for

and

values.

Table 5–3. DC Characteristics for User I/O, Dual-Purpose & Dedicated Pins (Part 1 of 2)

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Unit

Input voltage

–0.5

4.0

Input pin leakage
current

= V

CCIOmax

to 0 V

–10

OUT

Output voltage

CCIO

Tri-stated I/O pin
leakage current

= V

CCIOmax

to 0 V

–10

Altera Corporation

Preliminary

5–3

November 2004

Cyclone II Device Handbook, Volume 1

DC Characteristics & Timing Specifications

Table 5–4

shows the maximum V

overshoot voltage and the

dependency on the duty cycle of the input signal. See

Table 5–3

for more

information.

CC0

supply current

(standby) (all
memory blocks in
power-down mode)

= ground, no load, no

toggling inputs

CONF

Value of I/O pin pull-
up resistor before
and during
configuration

CCIO

= 3.0 V

Ω

CCIO

= 2.375 V

Ω

CCIO

= 1.71 V

150

Ω

Notes to

Table 5–3

(1)

All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before V

CCINT

and V

CCIO

are

powered.

(2)

The minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to the
voltages shown in

Table 5–4

, based on input duty cycle for input currents less than 100 mA. The overshoot is

dependent upon duty cycle of the signal. The DC case is equivalent to 100% duty cycle.

(3)

This value is specified for normal device operation. The value may vary during power-up. This applies for all
V

CCIO

settings (3.3, 2.5, 1.8, and 1.5 V).

(4)

Pin pull-up resistance values will lower if an external source drives the pin higher than V

CCIO

Table 5–3. DC Characteristics for User I/O, Dual-Purpose & Dedicated Pins (Part 2 of 2)

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Unit

Table 5–4. V

Overshoot Voltage for All Input Buffers

Maximum V

(V)

Input Signal Duty Cycle

4.0

100% (DC)

4.1

90%

4.2

50%

4.3

30%

4.4

17%

4.5

10%

5–4

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Operating Conditions

Single-Ended I/O Standards

Tables 5–6

5–7

provide operating condition information when using

single-ended I/O standards with Cyclone II devices.

Table 5–5

provides

descriptions for the voltage and current symbols used in

Tables 5–6

and

5–7

Table 5–5. Voltage & Current Symbol Definitions

Symbol

Definition

C C I O

Supply voltage for single-ended inputs and for output drivers

R E F

Reference voltage for setting the input switching threshold

I L

Input voltage that indicates a low logic level

I H

input voltage that indicates a high logic level

O L

Output voltage that indicates a low logic level

O H

Output voltage that indicates a high logic level

O L

Output current condition under which V

O L

is tested

O H

Output current condition under which V

O H

is tested

T T

Voltage applied to a resistor termination as specified by
HSTL and SSTL standards

Table 5–6. Recommended Operating Conditions for User I/O Pins Using Single-Ended I/O Standards (Part
1 of 2)

I/O Standard

CCIO

(V)

REF

(V)

Min

Nom

Max

Min

Nom

Max

Min

3.3-V LVTTL and
LVCMOS

3.135

3.3

3.465

0.8

1.7

2.5-V LVTTL and
LVCMOS

2.375

2.5

2.625

0.7

1.7

1.8-V LVTTL and
LVCMOS

1.710

1.8

1.890

0.35 × V

C C I O

0.65 × V

C C I O

1.5-V LVCMOS

1.425

1.5

1.575

0.35 × V

C C I O

0.65 × V

C C I O

PCI and PCI-X

3.000

3.3

3.600

0.3 × V

C C I O

0.5 × V

C C I O

SSTL-2 class I

2.375

2.5

2.625

1.19

1.25

1.31

R E F

– 0.18

R E F

+ 0.18

SSTL-2 class II

2.375

2.5

2.625

1.19

1.25

1.31

R E F

– 0.18

R E F

+ 0.18

SSTL-18 class I

1.7

1.8

1.9

0.833

0.9

0.969

R E F

– 0.125

R E F

+ 0.125

SSTL-18 class II

1.7

1.8

1.9

0.833

0.9

0.969

R E F

– 0.125

R E F

+ 0.125

1.8-V HSTL class I

1.71

1.8

1.89

0.85

0.9

0.95

R E F

– 0.1

R E F

+ 0.1

Altera Corporation

Preliminary

5–5

November 2004

Cyclone II Device Handbook, Volume 1

DC Characteristics & Timing Specifications

1.8-V HSTL class II

1.71

1.8

1.89

0.85

0.9

0.95

R E F

– 0.1

R E F

+ 0.1

1.5-V HSTL class I

1.425

1.5

1.575

0.71

0.75

0.79

R E F

– 0.1

R E F

+ 0.1

1.5-V HSTL class II

1.425

1.5

1.575

0.71

0.75

0.79

R E F

– 0.1

R E F

+ 0.1

Table 5–6

(1)

Nominal values (Nom) are for T

= 25° C, V

CCINT

= 1.2 V, and V

CCIO

= 1.5, 1.8, 2.5, and 3.3 V.

Table 5–7. DC Characteristics of User I/O Pins Using Single-Ended Standards (Part 1 of 2)

I/O Standard

Current Drive

Strength Setting

(mA)

Test Conditions

Voltage Thresholds

(mA)

Maximum V

(V) Minimum V

(V)

3.3-V LVTTL and
LVCMOS

–4

0.4

2.4

–8

–12

–16

–20

–24

2.5-V LVTTL and
LVCMOS

–4

0.4

C C I O

– 0.4

–8

–12

–16

1.8-V LVTTL and
LVCMOS

–2

0.4

C C I O

– 0.4

–4

–6

–8

–10

–12

1.5-V LVCMOS

–2

0.25 × V

C C I O

0.75 × V

C C I O

–4

–6

–8

PCI and PCI-X

1.5

–0.5

0.1 × V

C C I O

0.9 × V

C C I O

Table 5–6. Recommended Operating Conditions for User I/O Pins Using Single-Ended I/O Standards (Part
2 of 2)

Note (1)

I/O Standard

CCIO

(V)

REF

(V)

Min

Nom

Max

Min

Nom

Max

Min

5–6

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Operating Conditions

SSTL-2 class I

–8

– 0.57

+ 0.57

–12

SSTL-2 class II

–16

– 0.76

+ 0.76

–20

–24

SSTL-18 class I

–4

– 0.475

+ 0.475

–6

–8

–10

–12

SSTL-18 class II

–8

0.28

C C I O

– 0.28

–16

–18

1.8-V HSTL class I

–4

0.4

C C I O

– 0.4

–6

–8

–10

–12

1.8-V HSTL class II

–16

0.4

C C I O

– 0.4

–18

–20

1.5-V HSTL class I

–4

0.4

C C I O

– 0.4

–6

–8

–10

–12

1.5V HSTL class II

–16

0.4

C C I O

– 0.4

Table 5–7

(1)

The values in this table are based on the conditions listed in

Tables 5–2

and

5–6

Table 5–7. DC Characteristics of User I/O Pins Using Single-Ended Standards (Part 2 of 2)

Note (1)

I/O Standard

Current Drive

Strength Setting

(mA)

Test Conditions

Voltage Thresholds

(mA)

Maximum V

(V) Minimum V

(V)

Altera Corporation

Preliminary

5–7

November 2004

Cyclone II Device Handbook, Volume 1

DC Characteristics & Timing Specifications

Differential I/O Standards

The RSDS and mini-LVDS I/O standards are only supported on output
pins. The LVDS I/O standard is supported on both receiver input pins
and transmitter output pins.

For more information on how these differential I/O standards
are implemented, see the

High-Speed Differential Interfaces in

Cyclone II Devices

chapter in Volume 1 of the

Cyclone II Device

Handbook

Figure 5–1

shows the receiver input waveforms for all differential I/O

standards (LVDS, LVPECL, differential 1.5-V HSTL class I and II,
differential 1.8-V HSTL class I and II, differential SSTL-2 class I and II, and
differential SSTL-18 class I and II).

Figure 5–1. Receiver Input Waveforms for Differential I/O Standards

Notes to

Figure 5–1

(1)

is the differential input voltage. V

= |p – n|.

(2)

ICM

is the input common mode voltage. V

ICM

= (p – n)/2.

(3)

The p – n waveform is a function of the positive channel (p) and the negative channel (n).

Single-Ended Waveform

Differential Waveform (Mathematical Function of Positive & Negative Channel)

Positive Channel (p) = V

Negative Channel (n) = V

Ground

(1)

ICM

(2)

0 V

−

(3)

5–8

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Operating Conditions

Table 5–8

shows the recommended operating conditions for user I/O

pins with differential I/O standards.

Figure 5–2

shows the transmitter output waveforms for all supported

differential output standards (LVDS, mini-LVDS, RSDS, differential 1.5-V
HSTL class I and II, differential 1.8-V HSTL class I and II, differential
SSTL-2 class I and II, and differential SSTL-18 class I and II).

Table 5–8. Recommended Operating Conditions for User I/O Pins Using Differential Signal I/O Standards

I/O

Standard

CCIO

(V)

ICM

(V)

Min

Nom

Max

Min Nom

Max

Min

Nom

Max

Min

Max

Min

Max

LVDS

2.375

2.5

2.625

0.1

1.25

1.8

mini-LVDS

2.375

2.5

2.625

RSDS

2.375

2.5

2.625

LVPECL

3.135

3.3

3.465

0.1

0.6

0.95

2.2

2.1

2.88

Differential
1.5-V HSTL
class I
and II

1.425

1.5

1.575

0.2

C C I O

+ 0.6

0.68

0.9

R E F

– 0.1

R E F

+ 0.1

Differential
1.8-V HSTL
class I
and II

1.71

1.8

1.89

R E F

– 0.1

R E F

+ 0.1

Differential
SSTL-2
class I
and II

2.375

2.5

2.625

0.36

C C I O

+ 0.6

0.5 ×

C C I O

– 0.2

0.5 ×

C C I O

0.5 ×

C C I O

+ 0.2

R E F

– 0.1

R E F

+ 0.1

Differential
SSTL-18
class I
and II

1.7

1.8

1.9

0.25

C C I O

+ 0.6

0.5 ×

C C I O

– 0.2

0.5 ×

C C I O

0.5 ×

C C I O

+ 0.2

R E F

– 0.1

R E F

+ 0.1

Notes to

Table 5–8

(1)

Refer to the

High-Speed Differential Interfaces in Cyclone II Devices

chapter in Volume 1 of the

Cyclone II Device

Handbook

for measurement conditions on V

(2)

The RSDS and mini-LVDS I/O standards are only supported on output pins.

(3)

The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output
pins.

(4)

The differential 1.8-V and 1.5-V HSTL I/O standards are only supported on clock input pins and PLL output clock
pins.

(5)

The differential SSTL-18 and SSTL-2 I/O standards are only supported on clock input pins and PLL output clock
pins.

Altera Corporation

Preliminary

5–9

November 2004

Cyclone II Device Handbook, Volume 1

DC Characteristics & Timing Specifications

Figure 5–2. Transmitter Output Waveforms for Differential I/O Standards

Notes to

Figures 5–1

5–2

(1)

is the output differential voltage. V

= |p – n|.

(2)

OCM

is the output common mode voltage. V

OCM

= (p – n)/2.

(3)

The p – n waveform is a function of the positive channel (p) and the negative channel (n).

Table 5–9

shows the DC characteristics for user I/O pins with differential

I/O standards.

Single-Ended Waveform

Differential Waveform (Mathematical Function of Positive & Negative Channel)

Positive Channel (p) = V

Negative Channel (n) = V

Ground

(1)

0 V

OCM

(2)

−

(3)

Table 5–9. DC Characteristics for User I/O Pins Using Differential I/O Standards (Part 1 of 2)

I/O Standard

(mV)

∆

(mV)

OCM

(V)

Min

Typ

Max

Min Max

Min

Typ

Max

Min

Max

Min

Max

LVDS

247

600

1.125

1.25

1.375

mini-LVDS

300

600

1.2

1.4

RSDS

100

200

600

0.5

1.2

1.5

Differential 1.5-V
HSTL class I
and II

C C I O

– 0.4

0.4

Differential 1.8-V
HSTL class I
and II

C C I O

– 0.4

0.4

Differential
SSTL-2 class I

T T

0.57

T T

–

0.57

5–10

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

DC Characteristics for Different Pin Types

DC
Characteristics
for Different Pin
Types

Table 5–10

shows which types of pins that support bus hold circuitry.

Differential
SSTL-2 class II

T T

0.76

T T

–

0.76

Differential
SSTL-18 class I

0.5

C C I O

–

0.125

0.5 ×

C C I O

0.5 ×

C C I O

0.125

T T

0.475

T T

–

0.475

Differential
SSTL-18 class II

0.5

C C I O

–

0.125

0.5 ×

C C I O

0.5 ×

C C I O

0.125

C C I O

– 0.28

0.28

Notes to

Table 5–9

(1)

The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output
pins.

(2)

The RSDS and mini-LVDS I/O standards are only supported on output pins.

(3)

The differential 1.8-V HSTL and differential 1.5-V HSTL I/O standards are only supported on clock input pins and
PLL output clock pins.

(4)

The differential SSTL-18 and SSTL-2 I/O standards are only supported on clock input pins and PLL output clock
pins.

Table 5–9. DC Characteristics for User I/O Pins Using Differential I/O Standards (Part 2 of 2)

Note (1)

I/O Standard

(mV)

∆

(mV)

OCM

(V)

Min

Typ

Max

Min Max

Min

Typ

Max

Min

Max

Min

Max

Table 5–10. Bus Hold Support

Pin Type

Bus Hold

I/O pins using single-ended I/O standards

Yes

I/O pins using differential I/O standards

Dedicated clock pins

JTAG

Configuration pins

Altera Corporation

Preliminary

5–11

November 2004

Cyclone II Device Handbook, Volume 1

DC Characteristics & Timing Specifications

Table 5–11

specifies the bus hold parameters for general I/O pins.

Table 5–12

shows the Cyclone II device pin capacitance for different I/O

pin types.

Table 5–11. Bus Hold Parameters

Parameter

Conditions

CCIO

Level

Unit

1.8 V

2.5 V

3.3 V

Min

Max

Min

Max

Min

Max

Bus-hold low, sustaining
current

I N

I L

(maximum)

Bus-hold high, sustaining
current

I N

I L

(minimum)

–30

–50

–70

Bus-hold low, overdrive
current

0 V < V

I N

< V

C C I O

200

300

500

Bus-hold high, overdrive
current

0 V < V

I N

< V

C C I O

–200

–300

–500

Bus-hold trip point

0.68

1.07

0.7

1.7

0.8

2.0

Notes to

Table 5–11

(1)

There is no specification for bus-hold at V

CCIO

= 1.5 V for the HSTL I/O standard.

(2)

The bus-hold trip points are based on calculated input voltages from the JEDEC standard.

Table 5–12. Device Capacitance

Symbol

Parameter

Typical

Unit

I O

Input capacitance for user I/O pin

L V D S

Input capacitance for dual-purpose
LVDS/user I/O pin

V R E F

Input capacitance for dual-purpose

VREF

and user I/O pin.

D P C L K

Input capacitance for dual-purpose

DPCLK

and user I/O pin.

C L K

Input capacitance for clock pin.

Notes to

Table 5–12

(1)

Capacitance is sample-tested only. Capacitance is measured using time-domain
reflectometry (TDR). Measurement accuracy is within ±0.5 pF.

(2)

This specification will be available in a future version of the data sheet.

5–12

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Power Consumption

Table 5–13

shows the specification for ESD for all Cyclone II device pins.

Power
Consumption

Designers can calculate the power usage for their design using the Altera
power calculator and the simulation-based power estimation feature in
the Quartus

II software.

The interactive power calculator is typically used prior to designing the
FPGA in order to get a magnitude estimate of the device power. The
Quartus II software simulation-based power estimation feature allows
designers to apply test vectors against their design for more accurate
power consumption modeling.

In both cases, these calculations should only be used as an estimation of
power, not as a specification.

Contact Altera Applications for information on the Cyclone II power
calculator.

Table 5–13. ESD Protection

Symbol

Parameter

Maximum

Unit

ESD

H B M

Human body model

1,000

ESD

C D M

Charged device model

500

Charged device model for PLL
power pins and dedicated clocks
1, 3, 9, and 11

300

Altera Corporation

Preliminary

5–13

November 2004

Cyclone II Device Handbook, Volume 1

DC Characteristics & Timing Specifications

Cyclone II devices require a certain amount of power-up current to
successfully power up because of the nature of the leading-edge process
on which they are fabricated.

Table 5–14

will show the maximum power-

up current required to power up a Cyclone II device after device
characterization has been performed.

Designers should select power supplies and regulators that can supply
this amount of current when designing with Cyclone II devices. This
specification is for commercial operating conditions. Measurements were
performed with an isolated Cyclone II device on the board. Decoupling
capacitors were not used in this measurement. To factor in the current for
decoupling capacitors, sum up the current for each capacitor using the
following equation:

I = C (dV/dt)

The exact amount of current that will be consumed varies according to the
process, temperature, and power ramp rate. The duration of the I

CCINT

power-up requirement depends on the V

CCINT

voltage supply rise time.

Altera recommends using the Cyclone II Power Calculator to estimate the
user-mode I

CCINT

consumption and then select power supplies or

regulators based on the higher value.

Timing
Specifications

The DirectDrive™ technology and MultiTrack™ interconnect ensure
predictable performance, accurate simulation, and accurate timing
analysis across all Cyclone II device densities and speed grades. This
section describes and specifies the performance, internal, external, and
PLL timing specifications.

Table 5–14. Cyclone II Power-Up Current (I

CCINT

) Requirements

Device

Maximum Power-Up Current

Requirement

Unit

EP2C5

EP2C8

EP2C20

EP2C35

EP2C50

EP2C70

(1)

This specification will be available in a future version of the data sheet.

5–14

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

Timing Specifications

This section shows the timing models for Cyclone II devices. Commercial
devices will meet this timing over the commercial temperature range.
Industrial devices will meet this timing over the industrial temperature
range. All specifications are representative of worst-case supply voltage
and junction temperature conditions.

The preliminary timing model will be added into a future revision of this
Data Sheet.

Preliminary & Final Timing Specifications

Timing models can have either preliminary or final status. The Quartus II
software issues an informational message during the design compilation
if the timing models are preliminary.

Table 5–15

shows the status of the

Cyclone II device timing models.

Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.

Final timing numbers are based on actual device operation and testing.
These numbers reflect the actual performance of the device under worst-
case voltage and junction temperature conditions.

Table 5–15. Cyclone II Device Timing Model Status

Device

Preliminary

Final

EP2C5

EP2C8

EP2C20

EP2C35

EP2C50

EP2C70

Altera Corporation

Preliminary

5–15

November 2004

Cyclone II Device Handbook, Volume 1

DC Characteristics & Timing Specifications

PLL Timing
Specifications

describes the Cyclone II PLL specifications when operating

within the commercial junction temperature range from 0° to 85° C.

PLL specifications under industrial temperature-range
operating conditions are pending silicon characterization. The
industrial junction temperature range specifications will be
available upon completion of the PLL characterization across
the industrial junction temperature range from -40 to 100° C.

Table 5–16. PLL Specifications

Symbol

Parameter

Min

Max

Unit

I N

Input frequency (-6 speed grade)

311

MHz

Input frequency (-7 speed grade)

270

MHz

Input frequency (-8 speed grade)

240

MHz

I N

DUTY

Input clock duty cycle

I N

JITTER

Input clock period jitter

200

O U T _ E X T

(external PLL

clock output)

PLL output frequency (-6 speed grade)

15.625

MHz

PLL output frequency (-7 speed grade)

15.625

MHz

PLL output frequency (-8 speed grade)

15.625

MHz

O U T

(to global clock)

PLL output frequency (-6 speed grade)

402.5

MHz

PLL output frequency (-7 speed grade)

350

MHz

PLL output frequency (-8 speed grade)

310

MHz

O U T

DUTY

Duty cycle for external clock output (when
set to 50%)

J I T T E R

Period jitter for external clock output

L O C K

Time required to lock from end of device
configuration

V C O

PLL internal VCO operating range

300

1,000

MHz

Notes to

Table 5–16

(1)

These numbers are preliminary and pending silicon characterization.

(2)

The t

JITTER

specification for the

PLL[2..1]_OUT

pins are dependent on the I/O pins in its

VCCIO

bank, how many

of them are switching outputs, how much they toggle, and whether or not they use programmable current
strength.

(3)

If the design enables divide by 2, a 300- to 499-MHz internal VCO frequency is available.

(4)

This parameter is limited in Quartus II software by the I/O maximum frequency. The maximum I/O frequency is
different for each I/O standard.

5–16

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

PLL Timing Specifications

High Speed I/O Timing Specifications

Since LVDS, mini-LVDS, and RSDS data communication is source
synchronous, timing analysis is different than other I/O standards. The
high-speed I/O signal is based on skew between the data and the clock
signal.

Designers should also consider board skew, cable skew, and clock jitter in
their calculation. This section provides details on high-speed I/O
standards timing parameters in Cyclone II devices.

Table 5–17

defines the parameters of the timing diagram shown in

Figure 5–3

Table 5–17. High-Speed I/O Timing Definitions

Parameter

Symbol

Description

High-speed I/O
data rate

HSIODR

High-speed receiver and transmitter input
and output data rate.

Period

TUI

Time unit interval.
TUI = 1/HSIODR.

Channel-to-
channel skew

TCCS

The timing difference between the fastest
and slowest output edges, including t

variation and clock skew. The clock is
included in the TCCS measurement.
TCCS = TUI – SW – (2 × RSKM)

Sampling window

The period of time during which the data
must be valid in order for you to capture it
correctly. Sampling window is the sum of
the setup time, hold time, and jitter. The
window of t

+ t

is expected to be

centered in the sampling window.
SW = TUI – TCCS – (2 × RSKM)

Receiver input
skew margin

RSKM

RSKM is defined by the total margin left
after accounting for the sampling window
and TCCS. The RSKM equation is:
RSKM = (TUI – SW – TCCS) / 2

Altera Corporation

Preliminary

5–17

November 2004

Cyclone II Device Handbook, Volume 1

DC Characteristics & Timing Specifications

Figure 5–3. High-Speed I/O Timing Diagram

Figure 5–4

shows the high-speed I/O timing budget.

Figure 5–4. High-Speed I/O Timing Budget

Note to

Figure 5–4

(1)

The equation for the high-speed I/O timing budget is:
period = TCCS + RSKM + SW + RSKM.

Table 5–18

shows the RSDS timing budget for Cyclone II devices at

170 Mbps. RSDS is supported for transmitting from Cyclone II devices.
Cyclone II devices can not receive RSDS data because the devices are
intended for applications where they will be driving display drivers.

Sampling Window (SW)

Time Unit Interval (TUI)

RSKM

TCCS

RSKM

TCCS

Internal Clock

External

Input Clock

Receiver

Input Data

Internal Clock Period

RSKM

0.5

TCCS

RSKM

0.5

TCCS

5–18

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

PLL Timing Specifications

Cyclone II devices support a maximum RSDS data rate of 170 Mbps using
DDIO registers. The maximum internal clock frequency when designing
for RSDS is 85 MHz.

In order to determine the transmitter timing requirements, RSDS receiver
timing requirements on the other end of the link must be taken into
consideration. RSDS receiver timing parameters are typically defined as
t

and t

requirements. Therefore, the transmitter timing parameter

specifications are t

(minimum) and t

(maximum). Refer to

Figure 5–4

for the timing budget.

The AC timing requirements for RSDS are shown in

Figure 5–5

Table 5–18. RSDS Transmitter Timing Specification

Symbol

Conditions

-6 Speed Grade

-7 Speed Grade

-8 Speed Grade

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

HSIODR

Using DDIO
registers

31.25 170

31.25

170

31.25

170

Mbps

Period

5.88

TCCS

1.68

4.00

RSKM

0.10

Notes to

Table 5–18

(1)

The minimum data rate is limited by 2 × f

(minimum) for the PLL specifications shown in

(2)

This is how large the sampling window (sum of t

, t

, and t

JITTER

) can be at the receiving device. The Cyclone II

device is a transmitter only for the RSDS I/O standard.

(3)

The RSKM is assumed to be 100 ps for a calculated sampling window. RSKM is a system parameter determined by
the designer.

Altera Corporation

Preliminary

5–19

November 2004

Cyclone II Device Handbook, Volume 1

DC Characteristics & Timing Specifications

Figure 5–5. RSDS Transmitter Clock to Data Relationship

Table 5–19

shows the mini-LVDS transmitter timing budget for Cyclone II

devices at 170 Mbps. Cyclone II devices can not receive mini-LVDS data
because the devices are intended for applications where they will be
driving display drivers. A maximum mini-LVDS data rate of 170 Mbps is
supported for Cyclone II devices using DDIO registers. The maximum
internal clock frequency when designing for mini-LVDS is 85 MHz.

Transmitter

Valid

Data

Transmitter

Valid

Data

Valid

Data

Total

Skew

Valid

Data

(2 ns)

Channel-to-Channel

Skew (1.68 ns)

Transmitter

Clock (5.88 ns)

At transmitter

tx_data[11..0]

At receiver

rx_data[11..0]

Table 5–19. mini-LVDS Transmitter Timing Specification

Symbol

Conditions

-6 Speed Grade

-7 Speed Grade

-8 Speed Grade

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

HSIODR

Using DDIO
registers

31.25

170

31.25

170

31.25

170

Mbps

Period

5.88

TCCS

0.388

5.292

RSKM

0.10

Notes to

Table 5–19

(1)

The minimum data rate is limited by 2 × f

(minimum) for the PLL specifications shown in

(2)

This is how large the sampling window (sum of t

, t

, and t

JITTER

) can be at the receiving device. The Cyclone II

device is a transmitter only for mini-LVDS.

(3)

RSKM assumed to be 100 ps for calculated SW. RSKM is a system parameter determined by the designer.

5–20

Preliminary

Altera Corporation

Cyclone II Device Handbook, Volume 1

November 2004

PLL Timing Specifications

In order to determine the transmitter timing requirements, mini-LVDS
receiver timing requirements on the other end of the link must be taken
into consideration. mini-LVDS receiver timing parameters are typically
defined as t

and t

requirements. Therefore, the transmitter timing

parameter specifications are t

(minimum) and t

(maximum). Refer to

Figure 5–4

for the timing budget.

The AC timing requirements for mini-LVDS are shown in

Figure 5–6

Figure 5–6. mini-LVDS Transmitter AC Timing Specification

Notes to

Figure 5–6

(1)

The data setup time, t

, is 0.225 × TUI.

(2)

The data hold time, t

, is 0.225 × TUI.

(1)

(2)

TUI

(1)

(2)

LVDSCLK[]n

LVDSCLK[]p

LVDS[]p

LVDS[]n

Altera Corporation

Preliminary

5–21

November 2004

Cyclone II Device Handbook, Volume 1

DC Characteristics & Timing Specifications

Table 5–20

shows the LVDS timing budget for Cyclone II devices.

Cyclone II devices support LVDS receivers at data rates up to 805 Mbps
and LVDS transmitters at data rates up to 622 Mbps.

Table 5–20. LVDS Timing Specification

Symbol

Conditions

-6 Speed Grade

-7 Speed Grade

-8 Speed Grade

Unit

Min Typ

Max

Min

Typ

Max

Min

Typ

Max

HSIODR

156.25

622

156.25

622

156.25

530

Mbps

125

622

125

622

125

530

Mbps

125

622

125

622

125

530

Mbps

62.5

622

62.5

622

62.5

530

Mbps

31.25

622

31.25

622

31.25

530

Mbps

15.625

311

15.625

311

15.625

265

Mbps

Period

1.608

1.886

TCCS

200

230

800

920

RSKM

304

368

Notes to

Table 5–20

(1)

The minimum data rate is limited by 2 × f

(minimum) for the PLL specifications shown in

(2)

The PLL must divide down the input clock frequency to have the internal clock frequency meet the specification
shown in