101 Innovation Drive
San Jose, CA 95134
www.altera.com

Cyclone II Device Handbook, Volume 1

CII5V1-3.3

Copyright © 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-
ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al-
tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap-
plication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera
Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in-
formation and before placing orders for products or services

.

ii

 Altera 

Corporation

Altera Corporation 

 

iii

  

Contents

Chapter Revision Dates  ........................................................................... xi

About This Handbook ............................................................................  xiii

How to Contact Altera .......................................................................................................................... xiii
Typographic Conventions .................................................................................................................... xiii

Section I. Cyclone II Device Family Data Sheet

Revision History .................................................................................................................................... 1–1

Chapter 1. Introduction

Introduction ............................................................................................................................................ 1–1

Low-Cost Embedded Processing Solutions .................................................................................. 1–1
Low-Cost DSP Solutions ................................................................................................................. 1–1

Features ................................................................................................................................................... 1–2
Referenced Documents ......................................................................................................................... 1–9
Document Revision History ................................................................................................................. 1–9

Chapter 2. Cyclone II Architecture

Functional Description .......................................................................................................................... 2–1
Logic Elements ....................................................................................................................................... 2–2

LE Operating Modes ........................................................................................................................ 2–4

Logic Array Blocks ................................................................................................................................ 2–7

LAB Interconnects ............................................................................................................................ 2–8
LAB Control Signals ......................................................................................................................... 2–8

MultiTrack Interconnect ..................................................................................................................... 2–10

Row Interconnects .......................................................................................................................... 2–10
Column Interconnects .................................................................................................................... 2–12
Device Routing ............................................................................................................................... 2–15

Global Clock Network & Phase-Locked Loops ............................................................................... 2–16

Dedicated Clock Pins ..................................................................................................................... 2–20
Dual-Purpose Clock Pins .............................................................................................................. 2–20
Global Clock Network ................................................................................................................... 2–21
Global Clock Network Distribution ............................................................................................ 2–23
PLLs .................................................................................................................................................. 2–25

Embedded Memory ............................................................................................................................. 2–27

Memory Modes ............................................................................................................................... 2–30
Clock Modes .................................................................................................................................... 2–31
M4K Routing Interface .................................................................................................................. 2–31

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Contents

Embedded Multipliers ........................................................................................................................ 2–32

Multiplier Modes ............................................................................................................................ 2–35
Embedded Multiplier Routing Interface ..................................................................................... 2–36

I/O Structure & Features .................................................................................................................... 2–37

External Memory Interfacing ....................................................................................................... 2–44
Programmable Drive Strength ..................................................................................................... 2–49
Open-Drain Output ........................................................................................................................ 2–50
Slew Rate Control ........................................................................................................................... 2–51
Bus Hold .......................................................................................................................................... 2–51
Programmable Pull-Up Resistor .................................................................................................. 2–51
Advanced I/O Standard Support ................................................................................................ 2–52
High-Speed Differential Interfaces .............................................................................................. 2–53
Series On-Chip Termination ......................................................................................................... 2–55
I/O Banks ........................................................................................................................................ 2–57
MultiVolt I/O Interface ................................................................................................................. 2–60

Chapter 3. Configuration & Testing

IEEE Std. 1149.1 (JTAG) Boundary Scan Support ............................................................................. 3–1
Configuration ......................................................................................................................................... 3–5
Operating Modes ................................................................................................................................... 3–5
Configuration Schemes ......................................................................................................................... 3–6
Cyclone II Automated Single Event Upset Detection ...................................................................... 3–7

Custom-Built Circuitry .................................................................................................................... 3–7
Software Interface ............................................................................................................................. 3–7

Document Revision History ................................................................................................................. 3–8

Chapter 4. Hot Socketing & Power-On Reset

Introduction ............................................................................................................................................ 4–1
Cyclone II Hot-Socketing Specifications ............................................................................................ 4–1

Devices Can Be Driven before Power-Up ..................................................................................... 4–2
I/O Pins Remain Tri-Stated during Power-Up ............................................................................ 4–2

Hot-Socketing Feature Implementation in Cyclone II Devices ....................................................... 4–3
Power-On Reset Circuitry .................................................................................................................... 4–5

"Wake-up" Time for Cyclone II Devices ....................................................................................... 4–5

Conclusion .............................................................................................................................................. 4–7
Document Revision History ................................................................................................................. 4–7

Chapter 5. DC Characteristics and Timing Specifications

Operating Conditions ........................................................................................................................... 5–1

Single-Ended I/O Standards .......................................................................................................... 5–5
Differential I/O Standards .............................................................................................................. 5–7

DC Characteristics for Different Pin Types ..................................................................................... 5–11

On-Chip Termination Specifications ........................................................................................... 5–12

Power Consumption ........................................................................................................................... 5–13
Timing Specifications .......................................................................................................................... 5–14

Preliminary and Final Timing Specifications ............................................................................. 5–14

Performance .................................................................................................................................... 5–

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Contents

Internal Timing ............................................................................................................................... 5–18
Cyclone II Clock Timing Parameters ........................................................................................... 5–23
Clock Network Skew Adders ....................................................................................................... 5–29
IOE Programmable Delay ............................................................................................................. 5–30
Default Capacitive Loading of Different I/O Standards .......................................................... 5–31
I/O Delays ....................................................................................................................................... 5–33
Maximum Input and Output Clock Rate .................................................................................... 5–46
High Speed I/O Timing Specifications ....................................................................................... 5–55
External Memory Interface Specifications .................................................................................. 5–63
JTAG Timing Specifications .......................................................................................................... 5–64
PLL Timing Specifications ............................................................................................................ 5–66

Duty Cycle Distortion ......................................................................................................................... 5–67

DCD Measurement Techniques ................................................................................................... 5–68

Referenced Documents ....................................................................................................................... 5–74
Document Revision History ............................................................................................................... 5–74

Chapter 6. Reference & Ordering Information

Software .................................................................................................................................................. 6–1
Device Pin-Outs ..................................................................................................................................... 6–1
Ordering Information ........................................................................................................................... 6–1
Document Revision History ................................................................................................................. 6–2

Section II. Clock Management

Revision History .................................................................................................................................... 6–1

Chapter 7. PLLs in Cyclone II Devices

Introduction ............................................................................................................................................ 7–1
Cyclone II PLL Hardware Overview .................................................................................................. 7–2

PLL Reference Clock Generation ................................................................................................... 7–6

Clock Feedback Modes ....................................................................................................................... 7–10

Normal Mode .................................................................................................................................. 7–10
Zero Delay Buffer Mode ................................................................................................................ 7–11
No Compensation Mode ............................................................................................................... 7–12
Source-Synchronous Mode ........................................................................................................... 7–13

Hardware Features .............................................................................................................................. 7–14

Clock Multiplication & Division .................................................................................................. 7–14
Programmable Duty Cycle ........................................................................................................... 7–15
Phase-Shifting Implementation .................................................................................................... 7–16
Control Signals ................................................................................................................................ 7–17
Manual Clock Switchover ............................................................................................................. 7–20

Clocking ................................................................................................................................................ 7–21

Global Clock Network ................................................................................................................... 7–21
Clock Control Block ....................................................................................................................... 7–24
Global Clock Network Clock Source Generation ...................................................................... 7–26
Global Clock Network Power Down ........................................................................................... 7–28

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Contents

clkena signals .................................................................................................................................. 7–29

Board Layout ........................................................................................................................................ 7–30

VCCA & GNDA ............................................................................................................................. 7–31
VCCD & GND ................................................................................................................................. 7–33

Conclusion ............................................................................................................................................ 7–33

Section III. Memory

Revision History .................................................................................................................................... 7–1

Chapter 8. Cyclone II Memory Blocks

Introduction ............................................................................................................................................ 8–1
Overview ................................................................................................................................................. 8–1

Control Signals .................................................................................................................................. 8–3
Parity Bit Support ............................................................................................................................. 8–4
Byte Enable Support ........................................................................................................................ 8–4
Packed Mode Support ..................................................................................................................... 8–6
Address Clock Enable ...................................................................................................................... 8–6

Memory Modes ...................................................................................................................................... 8–8

Single-Port Mode .............................................................................................................................. 8–9
Simple Dual-Port Mode ................................................................................................................. 8–10
True Dual-Port Mode ..................................................................................................................... 8–12
Shift Register Mode ........................................................................................................................ 8–14
ROM Mode ...................................................................................................................................... 8–16
FIFO Buffer Mode ........................................................................................................................... 8–16

Clock Modes ......................................................................................................................................... 8–16

Independent Clock Mode .............................................................................................................. 8–17
Input/Output Clock Mode ........................................................................................................... 8–19
Read/Write Clock Mode ............................................................................................................... 8–22
Single-Clock Mode ......................................................................................................................... 8–24
Power-Up Conditions & Memory Initialization ........................................................................ 8–27

Read-During- Write Operation at the Same Address .................................................................... 8–28

Same-Port Read-During-Write Mode .......................................................................................... 8–28
Mixed-Port Read-During-Write Mode ........................................................................................ 8–29

Conclusion ............................................................................................................................................ 8–30
Referenced Documents ....................................................................................................................... 8–30

Chapter 9. External Memory Interfaces

Introduction ............................................................................................................................................ 9–1
External Memory Interface Standards ................................................................................................ 9–2

DDR & DDR2 SDRAM .................................................................................................................... 9–2
QDRII SRAM ..................................................................................................................................... 9–5

Cyclone II DDR Memory Support Overview .................................................................................... 9–9

Data & Data Strobe Pins ................................................................................................................ 9–10
Clock, Command & Address Pins ............................................................................................... 9–14
Parity, DM & ECC Pins ................................................................................................................. 9–14

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Contents

Phase Lock Loop (PLL) .................................................................................................................. 9–15
Clock Delay Control ....................................................................................................................... 9–15
DQS Postamble ............................................................................................................................... 9–16
DDR Input Registers ...................................................................................................................... 9–18
DDR Output Registers ................................................................................................................... 9–21
Bidirectional DDR Registers ......................................................................................................... 9–22

Conclusion ............................................................................................................................................ 9–24
Document Revision History ............................................................................................................... 9–25

Section IV. I/O Standards

Revision History .................................................................................................................................... 9–1

Chapter 10. Selectable I/O Standards in Cyclone II Devices

Introduction .......................................................................................................................................... 10–1
Supported I/O Standards ................................................................................................................... 10–1

3.3-V LVTTL (EIA/JEDEC Standard JESD8-B) .......................................................................... 10–3
3.3-V LVCMOS (EIA/JEDEC Standard JESD8-B) ..................................................................... 10–4
3.3-V (PCI Special Interest Group [SIG] PCI Local Bus Specification Revision 3.0) ............. 10–4
3.3-V PCI-X ...................................................................................................................................... 10–6
Easy-to-Use, Low-Cost PCI Express Solution ............................................................................ 10–6
2.5-V LVTTL (EIA/JEDEC Standard EIA/JESD8-5) ................................................................. 10–7
2.5-V LVCMOS (EIA/JEDEC Standard EIA/JESD8-5) ............................................................ 10–7
SSTL-2 Class I and II (EIA/JEDEC Standard JESD8-9A) ......................................................... 10–7
Pseudo-Differential SSTL-2 ........................................................................................................... 10–8
1.8-V LVTTL (EIA/JEDEC Standard EIA/JESD8-7) ................................................................. 10–9
1.8-V LVCMOS (EIA/JEDEC Standard EIA/JESD8-7) .......................................................... 10–10
SSTL-18 Class I and II .................................................................................................................. 10–10
1.8-V HSTL Class I and II ............................................................................................................ 10–11
Pseudo-Differential SSTL-18 Class I and Differential SSTL-18 Class II ............................... 10–12
1.8-V Pseudo-Differential HSTL Class I and II ........................................................................ 10–13
1.5-V LVCMOS (EIA/JEDEC Standard JESD8-11) .................................................................. 10–14
1.5-V HSTL Class I and II ............................................................................................................ 10–14
1.5-V Pseudo-Differential HSTL Class I and II ........................................................................ 10–15
LVDS, RSDS and mini-LVDS ..................................................................................................... 10–16
Differential LVPECL .................................................................................................................... 10–17

Cyclone II I/O Banks ........................................................................................................................ 10–18
Programmable Current Drive Strength .......................................................................................... 10–24

Voltage-Referenced I/O Standard Termination ...................................................................... 10–26
Differential I/O Standard Termination .................................................................................... 10–26
I/O Driver Impedance Matching (R

S

) and Series Termination (R

S

) ..................................... 10–27

Pad Placement and DC Guidelines ................................................................................................. 10–27

Differential Pad Placement Guidelines ..................................................................................... 10–28
V

REF

 Pad Placement Guidelines ................................................................................................. 10–29

DC Guidelines ............................................................................................................................... 10–32

5.0-V Device Compatibility .............................................................................................................. 10–34

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Contents

Conclusion .......................................................................................................................................... 10–36
References ........................................................................................................................................... 10–37
Referenced Documents ..................................................................................................................... 10–38
Document Revision History ............................................................................................................. 10–38

Chapter 11. High-Speed Differential Interfaces in Cyclone II Devices

Introduction .......................................................................................................................................... 11–1
Cyclone II High-Speed I/O Banks .................................................................................................... 11–1
Cyclone II High-Speed I/O Interface ............................................................................................... 11–3
I/O Standards Support ....................................................................................................................... 11–4

LVDS Standard Support in Cyclone II Devices ......................................................................... 11–4
RSDS I/O Standard Support in Cyclone II Devices .................................................................. 11–7
mini-LVDS Standard Support in Cyclone II Devices ................................................................ 11–9
LVPECL Support in Cyclone II .................................................................................................. 11–11
Differential SSTL Support in Cyclone II Devices ..................................................................... 11–12
Differential HSTL Support in Cyclone II Devices ................................................................... 11–13

High-Speed I/O Timing in Cyclone II Devices ............................................................................. 11–14
Design Guidelines ............................................................................................................................. 11–16

Differential Pad Placement Guidelines ..................................................................................... 11–16
Board Design Considerations ..................................................................................................... 11–16

Conclusion .......................................................................................................................................... 11–17

Section V. DSP

Revision History .................................................................................................................................. 11–1

Chapter 12. Embedded Multipliers in Cyclone II Devices

Introduction .......................................................................................................................................... 12–1
Embedded Multiplier Block Overview ............................................................................................ 12–2
Architecture .......................................................................................................................................... 12–4

Input Registers ................................................................................................................................ 12–4
Multiplier Stage .............................................................................................................................. 12–5
Output Registers ............................................................................................................................. 12–6

Operational Modes .............................................................................................................................. 12–6

18-Bit Multipliers ............................................................................................................................ 12–7
9-Bit Multipliers .............................................................................................................................. 12–7

Software Support ................................................................................................................................. 12–9
Conclusion ............................................................................................................................................ 12–9

Section VI. Configuration & Test

Revision History .................................................................................................................................. 12–1

Chapter 13. Configuring Cyclone II Devices

Introduction .......................................................................................................................................... 13–1

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Cyclone II Device Handbook, Volume 1

Contents

Cyclone II Configuration Overview ................................................................................................. 13–1
Configuration File Format .................................................................................................................. 13–3
Configuration Data Compression ..................................................................................................... 13–3
Active Serial Configuration (Serial Configuration Devices) ......................................................... 13–6

Single Device AS Configuration ................................................................................................... 13–7
Multiple Device AS Configuration ............................................................................................ 13–12
Configuring Multiple Cyclone II Devices with the Same Design ......................................... 13–15
Estimating AS Configuration Time ........................................................................................... 13–18
Programming Serial Configuration Devices ............................................................................ 13–19

PS Configuration ................................................................................................................................ 13–22

Single Device PS Configuration Using a MAX II Device as an External Host .................... 13–22
Multiple Device PS Configuration Using a MAX II Device as an External Host ................ 13–26
PS Configuration Using a Microprocessor ............................................................................... 13–31
Single Device PS Configuration Using a Configuration Device ............................................ 13–32
Multiple Device PS Configuration Using a Configuration Device ....................................... 13–37
PS Configuration Using a Download Cable ............................................................................. 13–48

JTAG Configuration .......................................................................................................................... 13–53

Single Device JTAG Configuration ............................................................................................ 13–55
JTAG Configuration of Multiple Devices ................................................................................. 13–58
Jam STAPL .................................................................................................................................... 13–60
Configuring Cyclone II FPGAs with JRunner .......................................................................... 13–60
Combining JTAG & Active Serial Configuration Schemes .................................................... 13–61
Programming Serial Configuration Devices In-System Using the JTAG Interface ............ 13–61

Device Configuration Pins ............................................................................................................... 13–64
Conclusion .......................................................................................................................................... 13–70

Chapter 14. IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone II Devices

Introduction .......................................................................................................................................... 14–1
IEEE Std. 1149.1 BST Architecture .................................................................................................... 14–2
IEEE Std. 1149.1 Boundary-Scan Register ........................................................................................ 14–4

Boundary-Scan Cells of a Cyclone II Device I/O Pin ............................................................... 14–4

IEEE Std. 1149.1 BST Operation Control .......................................................................................... 14–6

SAMPLE/PRELOAD Instruction Mode ..................................................................................... 14–9
Capture Phase ............................................................................................................................... 14–10
Shift & Update Phases ................................................................................................................. 14–10
EXTEST Instruction Mode .......................................................................................................... 14–11
Capture Phase ............................................................................................................................... 14–12
Shift & Update Phases ................................................................................................................. 14–12
BYPASS Instruction Mode .......................................................................................................... 14–13
IDCODE Instruction Mode ......................................................................................................... 14–14
USERCODE Instruction Mode ................................................................................................... 14–14
CLAMP Instruction Mode .......................................................................................................... 14–14
HIGHZ Instruction Mode ........................................................................................................... 14–15
I/O Voltage Support in JTAG Chain ......................................................................................... 14–15

Using IEEE Std. 1149.1 BST Circuitry ............................................................................................. 14–16
BST for Configured Devices ............................................................................................................. 14–17
Disabling IEEE Std. 1149.1 BST Circuitry ....................................................................................... 14–18

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Contents

Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing ............................................................. 14–18
Boundary-Scan Description Language (BSDL) Support .............................................................. 14–19
Conclusion .......................................................................................................................................... 14–19
References ........................................................................................................................................... 14–19
Document Revision History ............................................................................................................. 14–20

Section VII. PCB Layout Guidelines

Revision History .................................................................................................................................. 14–1

Chapter 15. Package Information for Cyclone II Devices

Introduction .......................................................................................................................................... 15–1
Thermal Resistance .............................................................................................................................. 15–2
Package Outlines ................................................................................................................................. 15–4

144-Pin Plastic Thin Quad Flat Pack (TQFP) – Wirebond ........................................................ 15–4
208-Pin Plastic Quad Flat Pack (PQFP) – Wirebond ................................................................. 15–7
240-Pin Plastic Quad Flat Pack (PQFP) ....................................................................................... 15–9
256-Pin FineLine Ball-Grid Array, Option 2 – Wirebond ....................................................... 15–11
484-Pin FineLine BGA, Option 3 – Wirebond .......................................................................... 15–13
484-Pin Ultra FineLine BGA – Wirebond ................................................................................. 15–15
672-Pin FineLine BGA Package, Option 3 – Wirebond ........................................................... 15–17
896-Pin FineLine BGA Package – Wirebond ............................................................................ 15–19

Altera Corporation 

 

xi

  

Chapter Revision Dates

The chapters in this book, 

Cyclone II Device Handbook, Volume 1

, were revised on the following dates. 

Where chapters or groups of chapters are available separately, part numbers are listed.

Chapter 1. Introduction

Revised:

February 2008

Part number:

CII51001-3.2

Chapter 2. Cyclone II Architecture

Revised:

February 2007

Part number:

CII51002-3.1

Chapter 3. Configuration & Testing

Revised:

February 2007

Part number:

CII51003-2.2

Chapter 4. Hot Socketing & Power-On Reset

Revised:

February 2007

Part number:

CII51004-3.1

Chapter 5. DC Characteristics and Timing Specifications

Revised:

February 2008

Part number:

CII51005-4.0

Chapter 6. Reference & Ordering Information

Revised:

February 2007

Part number:

CII51006-1.4

Chapter 7. PLLs in Cyclone II Devices

Revised:

February 2007

Part number:

CII51007-3.1

Chapter 8. Cyclone II Memory Blocks

Revised:

February 2008

Part number:

CII51008-2.4

Chapter 9. External Memory Interfaces

Revised:

February 2007

Part number:

CII51009-3.1

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Corporation

  

Chapter Revision Dates

Cyclone II Device Handbook, Volume 1

Chapter 10. Selectable I/O Standards in Cyclone II Devices

Revised:

February 2008

Part number:

CII51010-2.4

Chapter 11. High-Speed Differential Interfaces in Cyclone II Devices

Revised:

February 2007

Part number:

CII51011-2.2

Chapter 12. Embedded Multipliers in Cyclone II Devices

Revised:

February 2007

Part number:

CII51012-1.2

Chapter 13. Configuring Cyclone II Devices

Revised:

February 2007

Part number:

CII51013-3.1

Chapter 14. IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone II Devices

Revised:

February 2007

Part number:

CII51014-2.1

Chapter 15. Package Information for Cyclone II Devices

Revised:

February 2007

Part number:

CII51015-2.3

Altera Corporation 

  

xiii

Cyclone II Device Handbook, Volume 1

About This Handbook

This handbook provides comprehensive information about the Altera

®

 

Cyclone

®

II family of devices. 

How to Contact 
Altera

For the most up-to-date information about Altera products, refer to the 
following table.

Typographic 
Conventions

This document uses the typographic conventions shown below.

Contact 

(1)

Contact 
Method

Address

 

Technical support

Website

www.altera.com/support

Technical training

Website

www.altera.com/training

Email

custrain@altera.com

Product literature

Website

www.altera.com/literature

 

Altera literature services

Email

literature@altera.com

Non-technical support (General)

(Software Licensing)

Email

nacomp@altera.com

 

Email

authorization@altera.com

Note to table:

(1)

You can also contact your local Altera sales office or sales representative. 

Visual Cue

Meaning

Bold Type with Initial 
Capital Letters

 

Command names, dialog box titles, checkbox options, and dialog box options are 
shown in bold, initial capital letters. Example: 

Save As

 dialog box. 

bold type

 

External timing parameters, directory names, project names, disk drive names, 
filenames, filename extensions, and software utility names are shown in bold 
type. Examples: 

f

MAX

, \qdesigns

 directory, 

d:

 drive, 

chiptrip.gdf

 file.

Italic Type with Initial Capital 
Letters

 

Document titles are shown in italic type with initial capital letters. Example: 

AN 

75: High-Speed Board Design.

xiv

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Cyclone II Device Handbook, Volume 1

Typographic Conventions

Italic type

 

Internal timing parameters and variables are shown in italic type. 
Examples: 

t

PIA

, 

n

 + 1.

Variable names are enclosed in angle brackets (< >) and shown in italic type. 
Example: 

<file name>

, 

<project name>

.pof

 file. 

Initial Capital Letters

Keyboard keys and menu names are shown with initial capital letters. Examples: 
Delete key, the Options menu. 

“Subheading Title”

References to sections within a document and titles of on-line help topics are 
shown in quotation marks. Example: “Typographic Conventions.”

Courier type

 

Signal and port names are shown in lowercase Courier type. Examples: 

data1

, 

tdi

, 

input.

 Active-low signals are denoted by suffix 

n

, e.g., 

resetn

.

Anything that must be typed exactly as it appears is shown in Courier type. For 
example: 

c:\qdesigns\tutorial\chiptrip.gdf

. Also, sections of an 

actual file, such as a Report File, references to parts of files (e.g., the AHDL 
keyword 

SUBDESIGN

), as well as logic function names (e.g., 

TRI

) are shown in 

Courier. 

1., 2., 3., and
a., b., c., etc.

Numbered steps are used in a list of items when the sequence of the items is 
important, such as the steps listed in a procedure. 

■

●

•

 

Bullets are used in a list of items when the sequence of the items is not important. 

v

 

The checkmark indicates a procedure that consists of one step only.

1

 

The hand points to information that requires special attention. 

c

The caution indicates required information that needs special consideration and 
understanding and should be read prior to starting or continuing with the 
procedure or process.

w

The warning indicates information that should be read prior to starting or 
continuing the procedure or processes

r

 

The angled arrow indicates you should press the Enter key.

f

 

The feet direct you to more information on a particular topic. 

Visual Cue

Meaning

Altera Corporation 

 

Section I–1

Preliminary

Section I. Cyclone II

Device Family Data Sheet

This section provides information for board layout designers to 
successfully layout their boards for Cyclone

®

II devices. It contains the 

required PCB layout guidelines, device pin tables, and package 
specifications.

This section includes the following chapters:

■

Chapter 1. Introduction

■

Chapter 2. Cyclone II Architecture

■

Chapter 3. Configuration & Testing

■

Chapter 4. Hot Socketing & Power-On Reset

■

Chapter 5. DC Characteristics and Timing Specifications

■

Chapter 6. Reference & Ordering Information

Revision History 

Refer to each chapter for its own specific revision history. For information 
on when each chapter was updated, refer to the Chapter Revision Dates 
section, which appears in the complete handbook.

Section I–2

 

Altera Corporation

Preliminary

Revision History

Cyclone II Device Handbook, Volume 1

Altera Corporation 

 

1–1

February 2008

1. Introduction

Introduction

Following the immensely successful first-generation Cyclone

®

 device 

family, Altera

®

 Cyclone II FPGAs extend the low-cost FPGA density 

range to 68,416 logic elements (LEs) and provide up to 622 usable I/O 
pins and up to 1.1 Mbits of embedded memory. Cyclone II FPGAs are 
manufactured on 300-mm wafers using TSMC's 90-nm low-k dielectric 
process to ensure rapid availability and low cost. By minimizing silicon 
area, Cyclone II devices can support complex digital systems on a single 
chip at a cost that rivals that of ASICs. Unlike other FPGA vendors who 
compromise power consumption and performance for low-cost, Altera’s 
latest generation of low-cost FPGAs—Cyclone II FPGAs, offer 60% higher 
performance and half the power consumption of competing 90-nm 
FPGAs. The low cost and optimized feature set of Cyclone II FPGAs make 
them ideal solutions for a wide array of automotive, consumer, 
communications, video processing, test and measurement, and other 
end-market solutions. Reference designs, system diagrams, and IP, found 
at 

www.altera.com

, are available to help you rapidly develop complete 

end-market solutions using Cyclone II FPGAs.

Low-Cost Embedded Processing Solutions

Cyclone II devices support the Nios II embedded processor which allows 
you to implement custom-fit embedded processing solutions.  Cyclone II 
devices can also expand the peripheral set, memory, I/O, or performance 
of embedded processors.  Single or multiple Nios II embedded processors 
can be designed into a Cyclone II device to provide additional 
co-processing power or even replace existing embedded processors in 
your system.  Using Cyclone II and Nios II together allow for low-cost, 
high-performance embedded processing solutions, which allow you to 
extend your product's life cycle and improve time to market over 
standard product solutions.

Low-Cost DSP Solutions

Use Cyclone II FPGAs alone or as DSP co-processors to improve 
price-to-performance ratios for digital signal processing (DSP) 
applications. You can implement high-performance yet low-cost DSP 
systems with the following Cyclone II features and design support:

■

Up to 150 18 × 18 multipliers

■

Up to 1.1 Mbit of on-chip embedded memory

■

High-speed interfaces to external memory

CII51001-3.2

1–2

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2008

Features

■

DSP intellectual property (IP) cores

■

DSP Builder interface to The Mathworks Simulink and Matlab 
design environment

■

DSP Development Kit, Cyclone II Edition

Cyclone II devices include a powerful FPGA feature set optimized for 
low-cost applications including a wide range of density, memory, 
embedded multiplier, and packaging options. Cyclone II devices support 
a wide range of common external memory interfaces and I/O protocols 
required in low-cost applications. Parameterizable IP cores from Altera 
and partners make using Cyclone II interfaces and protocols fast and easy.

Features

The Cyclone II device family offers the following features:

■

High-density architecture with 4,608 to 68,416 LEs

●

M4K embedded memory blocks

●

Up to 1.1 Mbits of RAM available without reducing available 
logic

●

4,096 memory bits per block (4,608 bits per block including 512 
parity bits)

●

Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, 
and ×36

●

True dual-port (one read and one write, two reads, or two 
writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes

●

Byte enables for data input masking during writes

●

Up to 260-MHz operation

■

Embedded multipliers

●

Up to 150 18- × 18-bit multipliers are each configurable as two 
independent 9- × 9-bit multipliers with up to 250-MHz 
performance

●

Optional input and output registers

■

Advanced I/O support

●

High-speed differential I/O standard support, including LVDS, 
RSDS, mini-LVDS, LVPECL, differential HSTL, and differential 
SSTL 

●

Single-ended I/O standard support, including 2.5-V and 1.8-V, 
SSTL class I and II, 1.8-V and 1.5-V HSTL class I and II, 3.3-V PCI 
and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-, 
and 1.8-V LVTTL

●

Peripheral Component Interconnect Special Interest Group (PCI 
SIG) 

PCI Local Bus Specification, Revision 3.0

 

compliance for 3.3-V 

operation at 33 or 66 MHz for 32- or 64-bit interfaces 

●

PCI Express with an external TI PHY and an Altera PCI Express 
×1 Megacore

®

 function

Altera Corporation 

1–3

February 2008

Cyclone II Device Handbook, Volume 1

Introduction

●

133-MHz PCI-X 1.0 specification compatibility

●

High-speed external memory support, including DDR, DDR2, 
and SDR SDRAM, and QDRII SRAM supported by drop in 
Altera IP MegaCore functions for ease of use

●

Three dedicated registers per I/O element (IOE): one input 
register, one output register, and one output-enable register

●

Programmable bus-hold feature

●

Programmable output drive strength feature

●

Programmable delays from the pin to the IOE or logic array

●

I/O bank grouping for unique VCCIO and/or VREF bank 
settings

●

MultiVolt

™

 I/O standard support for 1.5-, 1.8-, 2.5-, and 

3.3-interfaces

●

Hot-socketing operation support

●

Tri-state with weak pull-up on I/O pins before and during 
configuration

●

Programmable open-drain outputs

●

Series on-chip termination support

■

Flexible clock management circuitry

●

Hierarchical clock network for up to 402.5-MHz performance

●

Up to four PLLs per device provide clock multiplication and 
division, phase shifting, programmable duty cycle, and external 
clock outputs, allowing system-level clock management and 
skew control 

●

Up to 16 global clock lines in the global clock network that drive 
throughout the entire device

■

Device configuration

●

Fast serial configuration allows configuration times less than 
100 ms

●

Decompression feature allows for smaller programming file 
storage and faster configuration times

●

Supports multiple configuration modes: active serial, passive 
serial, and JTAG-based configuration

●

Supports configuration through low-cost serial configuration 
devices

●

Device configuration supports multiple voltages (either 3.3, 2.5, 
or 1.8 V)

■

Intellectual property

●

Altera megafunction and Altera MegaCore function support, 
and Altera Megafunctions Partners Program (AMPP

SM

) 

megafunction support, for a wide range of embedded 
processors, on-chip and off-chip interfaces, peripheral 
functions, DSP functions, and communications functions and 

1–4

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2008

Features

protocols. Visit the Altera IPMegaStore at 

www.altera.com

 to 

download IP MegaCore functions.

●

Nios II Embedded Processor support

The Cyclone II family offers devices with the Fast-On feature, which 
offers a faster power-on-reset (POR) time. Devices that support the 
Fast-On feature are designated with an “A” in the device ordering code.  
For example, EP2C5A, EP2C8A, EP2C15A, and EP2C20A. The EP2C5A is 
only available in the automotive speed grade. The EP2C8A and EP2C20A 
are only available in the industrial speed grade. The EP2C15A is only 
available with the Fast-On feature and is available in both commercial 
and industrial grades. The Cyclone II “A” devices are identical in feature 
set and functionality to the non-A devices except for support of the faster 
POR time.

f

Cyclone II A devices are offered in automotive speed grade. For more 
information, refer to the Cyclone II section in the 

Automotive-Grade Device 

Handbook

.

f

For more information on POR time specifications for Cyclone II A and 
non-A devices, refer to the 

Hot Socketing & Power-On Reset

 

chapter in the 

Cyclone II Device Handbook

.

Table 1–1

 lists the Cyclone II device family features. 

Table 1–2

 lists the 

Cyclone II device package offerings and maximum user I/O pins.

Table 1–1. Cyclone II FPGA Family Features (Part 1 of 2)

Feature

EP2C5 

(2)

EP2C8 

(2)

EP2C15 

(1)

EP2C20 

(2)

EP2C35

EP2C50

EP2C70

LEs

4,608

8,256

14,448

18,752

33,216

50,528

68,416

M4K RAM blocks (4 
Kbits plus 
512 parity bits

26

36

52

52

105

129

250

Total RAM bits

119,808

165,888

239,616

239,616

483,840

594,432

1,152,00

0

Embedded 
multipliers 

(3)

13

18

26

26

35

86

150

PLLs

2

2

4

4

4

4

4

Altera Corporation 

1–5

February 2008

Cyclone II Device Handbook, Volume 1

Introduction

Maximum user 
I/O pins

158

182

315

315

475

450

622

Notes to 

Table 1–1

:

(1)

The EP2C15A is only available with the Fast On feature, which offers a faster POR time. This device is available in 
both commercial and industrial grade.

(2)

The EP2C5, EP2C8, and EP2C20 optionally support the Fast On feature, which is designated with an “A” in the 
device ordering  code. The EP2C5A is only available in the automotive speed grade. The EP2C8A and EP2C20A 
devices are only available in industrial grade.

(3)

This is the total number of 18 

×

 18 multipliers. For the total number of 9 

×

 9 multipliers per device, multiply the 

total number of 18 

×

 18 multipliers by 2.

Table 1–1. Cyclone II FPGA Family Features (Part 2 of 2)

Feature

EP2C5 

(2)

EP2C8 

(2)

EP2C15 

(1)

EP2C20 

(2)

EP2C35

EP2C50

EP2C70

1–6

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2008

Features

Cyclone II devices support vertical migration within the same package 
(for example, you can migrate between the EP2C35, EPC50, and EP2C70 
devices in the 672-pin FineLine BGA package). The exception to vertical 
migration support within the Cyclone II family is noted in 

Table 1–3

. 

Table 1–2. Cyclone II Package Options & Maximum User I/O Pins

Notes (1)

 

(2)

Device

144-Pin 

TQFP 

(3)

208-Pin 

PQFP 

(4)

240-Pin 

PQFP

256-Pin 

FineLine 

BGA

484-Pin 

FineLine 

BGA

484-Pin 

Ultra 

FineLine 

BGA

672-Pin 

FineLine 

BGA

896-Pin 

FineLine 

BGA

EP2C5 

(6)

 

(8)

89

142

—

158 

(5)

—

—

—

—

EP2C8 

(6)

85

138

—

182

—

—

—

—

EP2C8A 

(6)

, 

(7)

—

—

—

182

—

—

—

—

EP2C15A 

(6)

, 

(7)

—

—

—

152

315

—

—

—

EP2C20 

(6)

—

—

142

152

315

—

—

—

EP2C20A 

(6)

, 

(7)

—

—

—

152

315

—

—

—

EP2C35 

(6)

—

—

—

—

322

322

475

—

EP2C50 

(6)

—

—

—

—

294

294

450

—

EP2C70 

(6)

—

—

—

—

—

—

422

622

Notes to 

Table 1–2

:

(1)

Cyclone II devices support vertical migration within the same package (for example, you can migrate between the 
EP2C20 device in the 484-pin FineLine BGA package and the EP2C35 and EP2C50 devices in the same package).

(2)

The Quartus

®

 II software I/O pin counts include four additional pins, 

TDI

, 

TDO

, 

TMS

, and 

TCK

, which are not 

available as general purpose I/O pins.

(3)

TQFP: thin quad flat pack.

(4)

PQFP: plastic quad flat pack.

(5)

Vertical migration is supported between the EP2C5F256 and the EP2C8F256 devices. However, not all of the DQ 
and DQS groups are supported. Vertical migration between the EP2C5 and the EP2C15 in the F256 package is not 
supported.

(6)

The I/O pin counts for the EP2C5, EP2C8, and EP2C15A devices include 8 dedicated clock pins that can be used 
for data inputs. The I/O counts for the EP2C20, EP2C35, EP2C50, and EP2C70 devices include 16 dedicated clock 
pins that can be used for data inputs.

(7)

EP2C8A, EP2C15A, and EP2C20A have a Fast On feature that has a faster POR time. The EP2C15A is only available 
with the Fast On option.

(8)

The EP2C5 optionally support the Fast On feature, which is designated with an “A” in the device ordering code. 
The EP2C5A is only available in the automotive speed grade. Refer to the Cyclone II section in the 

Automotive-Grade 

Device Handbook

. 

Altera Corporation 

1–7

February 2008

Cyclone II Device Handbook, Volume 1

Introduction

Vertical migration means that you can migrate to devices whose 
dedicated pins, configuration pins, and power pins are the same for a 
given package across device densities.

1

When moving from one density to a larger density, I/O pins are 
often lost because of the greater number of power and ground 
pins required to support the additional logic within the larger 
device. For I/O pin migration across densities, you must cross 
reference the available I/O pins using the device pin-outs for all 
planned densities of a given package type to identify which I/O 
pins are migratable.

To ensure that your board layout supports migratable densities within 
one package offering, enable the applicable vertical migration path 
within the Quartus II software (go to Assignments menu, then Device, 
then click the 

Migration Devices

 button). After compilation, check the 

information messages for a full list of I/O, DQ, LVDS, and other pins that 
are not available because of the selected migration path. 

Table 1–3

 lists the 

Cyclone II device package offerings and shows the total number of 
non-migratable I/O pins when migrating from one density device to a 
larger density device.

Table 1–3. Total Number of Non-Migratable I/O Pins for Cyclone II Vertical Migration Paths

Vertical 

Migration Path

144-Pin TQFP

208-Pin 

PQFP 

256-Pin 

FineLine BGA 

(1)

484-Pin 

FineLine BGA 

(2)

484-Pin Ultra 

FineLine BGA

672-Pin 

FineLine BGA 

(3)

EP2C5 to 
EP2C8

4

4

1 

(4)

—

—

—

EP2C8 to 
EP2C15

—

—

30

—

—

—

EP2C15 to 
EP2C20

—

—

0

0

—

—

EP2C20 to 
EP2C35

—

—

16

—

—

EP2C35 to 
EP2C50

—

—

—

28

28 

(5)

28

EP2C50 to 
EP2C70

—

—

—

—

28

28

Notes to 

Table 1–3

:

(1)

Vertical migration between the EP2C5F256 to the EP2C15AF256 and the EP2C5F256 to the EP2C20F256 devices is 
not supported.

(2)

When migrating from the EP2C20F484 device to the EP2C50F484 device, a total of 39 I/O pins are non-migratable.

(3)

When migrating from the EP2C35F672 device to the EP2C70F672 device, a total of 56 I/O pins are non-migratable.

(4)

In addition to the one non-migratable I/O pin, there are 34 DQ pins that are non-migratable.

(5)

The pinouts of 484 FBGA and 484 UBGA are the same.

1–8

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2008

Features

Cyclone II devices are available in up to three speed grades: –6, –7, and 
–8, with –6 being the fastest. 

Table 1–4

 shows the Cyclone II device 

speed-grade offerings.

Table 1–4. Cyclone II Device Speed Grades

Device

144-Pin 

TQFP

208-Pin 

PQFP 

240-Pin 

PQFP

256-Pin 

FineLine 

BGA

484-Pin 

FineLine 

BGA

484-Pin 

Ultra 

FineLine 

BGA

672-Pin 

FineLine 

BGA

896-Pin 

FineLine 

BGA

EP2C5 

(1)

–

6, 

–

7, 

–

8

–

7, 

–

8

—

–

6, 

–

7, 

–

8 

—

—

—

—

EP2C8 

–

6, 

–

7, 

–

8

–

7, 

–

8

—

–

6, 

–

7, 

–

8

—

—

—

—

EP2C8A 

(2)

—

—

—

–

8

—

—

—

—

EP2C15A

—

—

—

–

6, 

–

7, 

–

8

–

6, 

–

7, 

–

8

—

—

—

EP2C20 —

—

–

8

–

6, 

–

7, 

–

8

–

6, 

–

7, 

–

8

—

—

—

EP2C20A 

(2)

—

—

—

–

8

–

8

—

—

—

EP2C35 —

—

—

—

–

6, 

–

7, 

–

8

–

6, 

–

7, 

–

8

–

6, 

–

7, 

–

8

—

EP2C50 —

—

—

—

–

6, 

–

7, 

–

8

–

6, 

–

7, 

–

8

–

6, 

–

7, 

–

8

—

EP2C70 

—

—

—

—

—

—

–

6, 

–

7, 

–

8

–

6, 

–

7, 

–

8

Notes to 

Table 1–4

:

(1)

The EP2C5 optionally support the Fast On feature, which is designated with an “A” in the device ordering code. 
The EP2C5A is only available in the automotive speed grade. Refer to the Cyclone II section in the 

Automotive-Grade 

Device Handbook

 

for detailed information.

(2)

EP2C8A and EP2C20A are only available in industrial grade.

Altera Corporation 

1–9

February 2008

Cyclone II Device Handbook, Volume 1

Introduction

Referenced 
Documents

This chapter references the following documents:

■

Hot Socketing & Power-On Reset

 chapter in 

Cyclone II Device Handbook

■

Automotive-Grade Device Handbook

 

Document 
Revision History

Table 1–5

 shows the revision history for this document.

Table 1–5. Document Revision History

Date & 

Document 

Version

Changes Made

Summary of Changes

February 2008 
v3.2

●

Added 

“Referenced Documents”

.

●

Updated 

“Features”

 section and 

Table 1–1

, 

Table 1–2

, 

and 

Table 1–4

 with information about EP2C5A.

—

February 2007 
v3.1

●

Added document revision history.

●

Added new 

Note (2)

 to 

Table 1–2

.

Note to explain difference 
between I/O pin count 
information provided in 

Table 1–2

 and in the Quartus II 

software documentation.

November 2005 
v2.1

●

Updated Introduction and Features.

●

Updated 

Table 1–3

.

—

July 2005 v2.0

●

Updated technical content throughout.

●

Updated 

Table 1–2

.

●

Added 

Tables 1–3

 and 

1–4

.

—

November 2004 
v1.1

●

Updated 

Table 1–2

.

●

Updated bullet list in the 

“Features”

 section.

—

June 2004 v1.0

Added document to the Cyclone II Device Handbook.

—

1–10

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2008

Document Revision History

Altera Corporation 

 

2–1

February 2007

2. Cyclone II Architecture

Functional 
Description

Cyclone

®

II devices contain a two-dimensional row- and column-based 

architecture to implement custom logic. Column and row interconnects 
of varying speeds provide signal interconnects between logic array 
blocks (LABs), embedded memory blocks, and embedded multipliers.

The logic array consists of LABs, with 16 logic elements (LEs) in each 
LAB. An LE is a small unit of logic providing efficient implementation of 
user logic functions. LABs are grouped into rows and columns across the 
device. Cyclone II devices range in density from 4,608 to 68,416 LEs.

Cyclone II devices provide a global clock network and up to four 
phase-locked loops (PLLs). The global clock network consists of up to 16 
global clock lines that drive throughout the entire device. The global clock 
network can provide clocks for all resources within the device, such as 
input/output elements (IOEs), LEs, embedded multipliers, and 
embedded memory blocks. The global clock lines can also be used for 
other high fan-out signals. Cyclone II PLLs provide general-purpose 
clocking with clock synthesis and phase shifting as well as external 
outputs for high-speed differential I/O support.

M4K memory blocks are true dual-port memory blocks with 4K bits of 
memory plus parity (4,608 bits). These blocks provide dedicated true 
dual-port, simple dual-port, or single-port memory up to 36-bits wide at 
up to 260 MHz. These blocks are arranged in columns across the device 
in between certain LABs. Cyclone II devices offer between 119 to 
1,152 Kbits of embedded memory.

Each embedded multiplier block can implement up to either two 9 × 9-bit 
multipliers, or one 18 × 18-bit multiplier with up to 250-MHz 
performance. Embedded multipliers are arranged in columns across the 
device.

Each Cyclone II device I/O pin is fed by an IOE located at the ends of LAB 
rows and columns around the periphery of the device. I/O pins support 
various single-ended and differential I/O standards, such as the 66- and 
33-MHz, 64- and 32-bit PCI standard, PCI-X, and the LVDS I/O standard 
at a maximum data rate of 805 megabits per second (Mbps) for inputs and 
640 Mbps for outputs. Each IOE contains a bidirectional I/O buffer and 
three registers for registering input, output, and output-enable signals. 
Dual-purpose DQS, DQ, and DM pins along with delay chains (used to 

CII51002-3.1

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February 2007

Logic Elements

phase-align double data rate (DDR) signals) provide interface support for 
external memory devices such as DDR, DDR2, and single data rate (SDR) 
SDRAM, and QDRII SRAM devices at up to 167 MHz. 

Figure 2–1

 shows a diagram of the Cyclone II EP2C20 device.

Figure 2–1. Cyclone II EP2C20 Device Block Diagram

The number of M4K memory blocks, embedded multiplier blocks, PLLs, 
rows, and columns vary per device.

Logic Elements

The smallest unit of logic in the Cyclone II architecture, the LE, is compact 
and provides advanced features with efficient logic utilization. Each LE 
features:

■

A four-input look-up table (LUT), which is a function generator that 
can implement any function of four variables

■

A programmable register

■

A carry chain connection

■

A register chain connection

■

The ability to drive all types of interconnects: local, row, column, 
register chain, and direct link interconnects

■

Support for register packing

■

Support for register feedback

PLL

PLL

IOEs

PLL

PLL

IOEs

IOEs

Logic
Array

Logic
Array

Logic
Array

Logic
Array

IOEs

M4K Blocks

M4K Blocks

Embedded
Multipliers

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Cyclone II Architecture

Figure 2–2

 shows a Cyclone II LE.

Figure 2–2. Cyclone II LE 

Each LE’s programmable register can be configured for D, T, JK, or SR 
operation. Each register has data, clock, clock enable, and clear inputs. 
Signals that use the global clock network, general-purpose I/O pins, or 
any internal logic can drive the register’s clock and clear control signals. 
Either general-purpose I/O pins or internal logic can drive the clock 
enable. For combinational functions, the LUT output bypasses the 
register and drives directly to the LE outputs.

Each LE has three outputs that drive the local, row, and column routing 
resources. The LUT or register output can drive these three outputs 
independently. Two LE outputs drive column or row and direct link 
routing connections and one drives local interconnect resources, allowing 
the LUT to drive one output while the register drives another output. This 
feature, register packing, improves device utilization because the device 
can use the register and the LUT for unrelated functions. When using 
register packing, the LAB-wide synchronous load control signal is not 
available. See 

“LAB Control Signals” on page 2–8

 for more information.

labclk1

labclk2

labclr2

LAB Carry-In

Clock &

Clock Enable

Select

LAB Carry-Out

Look-Up

Table
(LUT)

Carry

Chain

Row, Column,
And Direct Link 
Routing

Row, Column,
And Direct Link 
Routing

Programmable
Register

CLRN

D

Q

ENA

Register Bypass

Packed
Register Select

Chip-Wide

Reset

(DEV_CLRn)

labclkena1

labclkena2

Synchronous

Load and

Clear Logic

LAB-Wide

Synchronous

Load

LAB-Wide

Synchronous

Clear

Asynchronous

Clear Logic

data1
data2
data3

data4

labclr1

Local Routing

Register Chain
Output

Register
Feedback

Register Chain
Routing From
Previous LE

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February 2007

Logic Elements

Another special packing mode allows the register output to feed back into 
the LUT of the same LE so that the register is packed with its own fan-out 
LUT, providing another mechanism for improved fitting. The LE can also 
drive out registered and unregistered versions of the LUT output.

In addition to the three general routing outputs, the LEs within an LAB 
have register chain outputs. Register chain outputs allow registers within 
the same LAB to cascade together. The register chain output allows an 
LAB to use LUTs for a single combinational function and the registers to 
be used for an unrelated shift register implementation. These resources 
speed up connections between LABs while saving local interconnect 
resources. See 

“MultiTrack Interconnect” on page 2–10

 for more 

information on register chain connections.

LE Operating Modes

The Cyclone II LE operates in one of the following modes:

■

Normal mode

■

Arithmetic mode

Each mode uses LE resources differently. In each mode, six available 
inputs to the LE—the four data inputs from the LAB local interconnect, 
the LAB carry-in from the previous carry-chain LAB, and the register 
chain connection—are directed to different destinations to implement the 
desired logic function. LAB-wide signals provide clock, asynchronous 
clear, synchronous clear, synchronous load, and clock enable control for 
the register. These LAB-wide signals are available in all LE modes.

The Quartus

®

II software, in conjunction with parameterized functions 

such as library of parameterized modules (LPM) functions, automatically 
chooses the appropriate mode for common functions such as counters, 
adders, subtractors, and arithmetic functions. If required, you can also 
create special-purpose functions that specify which LE operating mode to 
use for optimal performance.

Normal Mode

The normal mode is suitable for general logic applications and 
combinational functions. In normal mode, four data inputs from the LAB 
local interconnect are inputs to a four-input LUT (see 

Figure 2–3

). The 

Quartus II Compiler automatically selects the carry-in or the 

data3

 

signal as one of the inputs to the LUT. LEs in normal mode support 
packed registers and register feedback.

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Cyclone II Architecture

Figure 2–3. LE in Normal Mode

Arithmetic Mode

The arithmetic mode is ideal for implementing adders, counters, 
accumulators, and comparators. An LE in arithmetic mode implements a 
2-bit full adder and basic carry chain (see 

Figure 2–4

). LEs in arithmetic 

mode can drive out registered and unregistered versions of the LUT 
output. Register feedback and register packing are supported when LEs 
are used in arithmetic mode.

data1

Four-Input

LUT

data2

data3
cin (from cout 
of previous LE)

data4

clock (LAB Wide)

ena (LAB Wide)

aclr (LAB Wide)

CLRN

D

Q

ENA

sclear

(LAB Wide)

sload

(LAB Wide)

Register chain

connection

Register
chain output

Row, Column, and
Direct Link Routing

Row, Column, and
Direct Link Routing

Local routing

Register Feedback

Packed Register Input

2–6

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February 2007

Logic Elements

Figure 2–4. LE in Arithmetic Mode

The Quartus II Compiler automatically creates carry chain logic during 
design processing, or you can create it manually during design entry. 
Parameterized functions such as LPM functions automatically take 
advantage of carry chains for the appropriate functions.

The Quartus II Compiler creates carry chains longer than 16 LEs by 
automatically linking LABs in the same column. For enhanced fitting, a 
long carry chain runs vertically, which allows fast horizontal connections 
to M4K memory blocks or embedded multipliers through direct link 
interconnects. For example, if a design has a long carry chain in a LAB 
column next to a column of M4K memory blocks, any LE output can feed 
an adjacent M4K memory block through the direct link interconnect. 
Whereas if the carry chains ran horizontally, any LAB not next to the 
column of M4K memory blocks would use other row or column 
interconnects to drive a M4K memory block. A carry chain continues as 
far as a full column.

clock (LAB Wide)

ena (LAB Wide)

aclr (LAB Wide)

CLRN

D

Q

ENA

Register chain

connection

sclear

(LAB Wide)

sload

(LAB Wide)

Register
chain output

Row, column, and
direct link routing

Row, column, and
direct link routing

Local routing

Register Feedback

Three-Input

LUT

Three-Input

LUT

cin (from cout

of previous LE)

data2

data1

cout

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Cyclone II Architecture

Logic Array 
Blocks

Each LAB consists of the following:

■

16 LEs

■

LAB control signals

■

LE carry chains

■

Register chains

■

Local interconnect

The local interconnect transfers signals between LEs in the same LAB. 
Register chain connections transfer the output of one LE’s register to the 
adjacent LE’s register within an LAB. The Quartus II Compiler places 
associated logic within an LAB or adjacent LABs, allowing the use of 
local, and register chain connections for performance and area efficiency. 

Figure 2–5

 shows the Cyclone II LAB.

Figure 2–5. Cyclone II LAB Structure

Direct link
interconnect
from adjacent
block

Direct link
interconnect
to adjacent
block

Row Interconnect

Column 
Interconnect

Local Interconnect

LAB

Direct link
interconnect
from adjacent
block

Direct link
interconnect
to adjacent
block

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February 2007

Logic Array Blocks

LAB Interconnects

The LAB local interconnect can drive LEs within the same LAB. The LAB 
local interconnect is driven by column and row interconnects and LE 
outputs within the same LAB. Neighboring LABs, PLLs, M4K RAM 
blocks, and embedded multipliers from the left and right can also drive 
an LAB’s local interconnect through the direct link connection. The direct 
link connection feature minimizes the use of row and column 
interconnects, providing higher performance and flexibility. Each LE can 
drive 48 LEs through fast local and direct link interconnects. 

Figure 2–6

 

shows the direct link connection.

Figure 2–6. Direct Link Connection

LAB Control Signals

Each LAB contains dedicated logic for driving control signals to its LEs. 
The control signals include:

■

Two clocks

■

Two clock enables

■

Two asynchronous clears

■

One synchronous clear

■

One synchronous load

LAB

Direct link
interconnect
to right

Direct link interconnect from
right LAB, M4K memory
block, embedded multiplier,
PLL, or IOE output

Direct link interconnect from

left LAB, M4K memory

block, embedded multiplier,

PLL, or IOE output

Local

Interconnect

Direct link

interconnect

to left

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Cyclone II Architecture

This gives a maximum of seven control signals at a time. When using the 
LAB-wide synchronous load, the 

clkena

 of 

labclk1

 is not available. 

Additionally, register packing and synchronous load cannot be used 
simultaneously.

Each LAB can have up to four non-global control signals. Additional LAB 
control signals can be used as long as they are global signals.

Synchronous clear and load signals are useful for implementing counters 
and other functions. The synchronous clear and synchronous load signals 
are LAB-wide signals that affect all registers in the LAB.

Each LAB can use two clocks and two clock enable signals. Each LAB’s 
clock and clock enable signals are linked. For example, any LE in a 
particular LAB using the 

labclk1

 signal also uses 

labclkena1

. If the 

LAB uses both the rising and falling edges of a clock, it also uses both 
LAB-wide clock signals. De-asserting the clock enable signal turns off the 
LAB-wide clock.

The LAB row clocks [5..0] and LAB local interconnect generate the LAB-
wide control signals. The MultiTrack

™

 interconnect’s inherent low skew 

allows clock and control signal distribution in addition to data. 

Figure 2–7

 

shows the LAB control signal generation circuit.

Figure 2–7. LAB-Wide Control Signals

LAB-wide signals control the logic for the register’s clear signal. The LE 
directly supports an asynchronous clear function. Each LAB supports up 
to two asynchronous clear signals (

labclr1

 and 

labclr2

).

labclkena1

labclk2

labclk1

labclkena2

labclr1

Dedicated
LAB Row
Clocks

Local
Interconnect

Local
Interconnect

Local
Interconnect

Local
Interconnect

syncload

synclr

labclr2

6

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February 2007

MultiTrack Interconnect

A LAB-wide asynchronous load signal to control the logic for the 
register’s preset signal is not available. The register preset is achieved by 
using a NOT gate push-back technique. Cyclone II devices can only 
support either a preset or asynchronous clear signal.

In addition to the clear port, Cyclone II devices provide a chip-wide reset 
pin (

DEV_CLRn

) that resets all registers in the device. An option set before 

compilation in the Quartus II software controls this pin. This chip-wide 
reset overrides all other control signals.

MultiTrack 
Interconnect

In the Cyclone II architecture, connections between LEs, M4K memory 
blocks, embedded multipliers, and device I/O pins are provided by the 
MultiTrack interconnect structure with DirectDrive™ technology. The 
MultiTrack interconnect consists of continuous, performance-optimized 
routing lines of different speeds used for inter- and intra-design block 
connectivity. The Quartus II Compiler automatically places critical paths 
on faster interconnects to improve design performance.

DirectDrive technology is a deterministic routing technology that ensures 
identical routing resource usage for any function regardless of placement 
within the device. The MultiTrack interconnect and DirectDrive 
technology simplify the integration stage of block-based designing by 
eliminating the re-optimization cycles that typically follow design 
changes and additions.

The MultiTrack interconnect consists of row (direct link, R4, and R24) and 
column (register chain, C4, and C16) interconnects that span fixed 
distances. A routing structure with fixed-length resources for all devices 
allows predictable and repeatable performance when migrating through 
different device densities.

Row Interconnects

Dedicated row interconnects route signals to and from LABs, PLLs, M4K 
memory blocks, and embedded multipliers within the same row. These 
row resources include:

■

Direct link interconnects between LABs and adjacent blocks

■

R4 interconnects traversing four blocks to the right or left

■

R24 interconnects for high-speed access across the length of the 
device

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Cyclone II Architecture

The direct link interconnect allows an LAB, M4K memory block, or 
embedded multiplier block to drive into the local interconnect of its left 
and right neighbors. Only one side of a PLL block interfaces with direct 
link and row interconnects. The direct link interconnect provides fast 
communication between adjacent LABs and/or blocks without using 
row interconnect resources.

The R4 interconnects span four LABs, three LABs and one M4K memory 
block, or three LABs and one embedded multiplier to the right or left of a 
source LAB. These resources are used for fast row connections in a four-
LAB region. Every LAB has its own set of R4 interconnects to drive either 
left or right. 

Figure 2–8

 shows R4 interconnect connections from an LAB. 

R4 interconnects can drive and be driven by LABs, M4K memory blocks, 
embedded multipliers, PLLs, and row IOEs. For LAB interfacing, a 
primary LAB or LAB neighbor (see 

Figure 2–8

) can drive a given R4 

interconnect. For R4 interconnects that drive to the right, the primary 
LAB and right neighbor can drive on to the interconnect. For R4 
interconnects that drive to the left, the primary LAB and its left neighbor 
can drive on to the interconnect. R4 interconnects can drive other R4 
interconnects to extend the range of LABs they can drive. Additionally, 
R4 interconnects can drive R24 interconnects, C4, and C16 interconnects 
for connections from one row to another. 

Figure 2–8. R4 Interconnect Connections

Notes to 

Figure 2–8

:

(1)

C4 interconnects can drive R4 interconnects.

(2)

This pattern is repeated for every LAB in the LAB row.

Primary
LAB (2)

R4 Interconnect

Driving Left

Adjacent LAB can
Drive onto Another
LAB's R4 Interconnect

C4 Column Interconnects (1)

R4 Interconnect
Driving Right

LAB

Neighbor

LAB

Neighbor

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MultiTrack Interconnect

R24 row interconnects span 24 LABs and provide the fastest resource for 
long row connections between non-adjacent LABs, M4K memory blocks, 
dedicated multipliers, and row IOEs. R24 row interconnects drive to 
other row or column interconnects at every fourth LAB. R24 row 
interconnects drive LAB local interconnects via R4 and C4 interconnects 
and do not drive directly to LAB local interconnects. R24 interconnects 
can drive R24, R4, C16, and C4 interconnects.

Column Interconnects

The column interconnect operates similar to the row interconnect. Each 
column of LABs is served by a dedicated column interconnect, which 
vertically routes signals to and from LABs, M4K memory blocks, 
embedded multipliers, and row and column IOEs. These column 
resources include:

■

Register chain interconnects within an LAB

■

C4 interconnects traversing a distance of four blocks in an up and 
down direction

■

C16 interconnects for high-speed vertical routing through the device

Cyclone II devices include an enhanced interconnect structure within 
LABs for routing LE output to LE input connections faster using register 
chain connections. The register chain connection allows the register 
output of one LE to connect directly to the register input of the next LE in 
the LAB for fast shift registers. The Quartus II Compiler automatically 
takes advantage of these resources to improve utilization and 
performance. 

Figure 2–9

 shows the register chain interconnects.

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Cyclone II Architecture

Figure 2–9. Register Chain Interconnects

The C4 interconnects span four LABs, M4K blocks, or embedded 
multipliers up or down from a source LAB. Every LAB has its own set of 
C4 interconnects to drive either up or down. 

Figure 2–10

 shows the C4 

interconnect connections from an LAB in a column. The C4 interconnects 
can drive and be driven by all types of architecture blocks, including 
PLLs, M4K memory blocks, embedded multiplier blocks, and column 
and row IOEs. For LAB interconnection, a primary LAB or its LAB 
neighbor (see 

Figure 2–10

) can drive a given C4 interconnect. C4 

interconnects can drive each other to extend their range as well as drive 
row interconnects for column-to-column connections.

LE 1

LE 2

LE 3

LE 4

LE 5

LE 6

LE 7

LE 8

LE 9

LE 10

LE 11

LE 12

LE13

LE 14

LE 15

LE 16

Carry Chain

Routing to

Adjacent LE

Local

Interconnect

Register Chain
Routing to Adjacent
LE's Register Input

Local Interconnect
Routing Among LEs
in the LAB

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February 2007

MultiTrack Interconnect

Figure 2–10. C4 Interconnect Connections

Note (1)

Note to 

Figure 2–10

:

(1)

Each C4 interconnect can drive either up or down four rows.

C4 Interconnect
Drives Local and R4
Interconnects
Up to Four Rows

Adjacent LAB can

drive onto neighboring
LAB's C4 interconnect

C4 Interconnect
Driving Up

C4 Interconnect
Driving Down

LAB

Row
Interconnect

Local

Interconnect

Primary

LAB

LAB

Neighbor

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Cyclone II Architecture

C16 column interconnects span a length of 16 LABs and provide the 
fastest resource for long column connections between LABs, M4K 
memory blocks, embedded multipliers, and IOEs. C16 column 
interconnects drive to other row and column interconnects at every 
fourth LAB. C16 column interconnects drive LAB local interconnects via 
C4 and R4 interconnects and do not drive LAB local interconnects 
directly. C16 interconnects can drive R24, R4, C16, and C4 interconnects.

Device Routing

All embedded blocks communicate with the logic array similar to 
LAB-to-LAB interfaces. Each block (for example, M4K memory, 
embedded multiplier, or PLL) connects to row and column interconnects 
and has local interconnect regions driven by row and column 
interconnects. These blocks also have direct link interconnects for fast 
connections to and from a neighboring LAB.

Table 2–1

 shows the Cyclone II device’s routing scheme.

Table 2–1. Cyclone II Device Routing Scheme (Part 1 of 2)

Source

Destination

Register

 Chain

Loca

l Inter

connect

Direct Link 

Interconnect

R4 Interconn

ect

R2

4 Interconnect

C4 Intercon

nect

C16 Interconnect

LE

M4K RAM Bloc

k

Embe

dded Multiplier

PLL

Col

u

mn IO

E

Ro

w I

O

E

Register 
Chain

v

Local 
Interconnect

v

v

v

v

v

v

Direct Link 
Interconnect

v

R4 
Interconnect

v

v

v

v

v

R24 
Interconnect

v

v

v

v

C4 
Interconnect

v

v

v

v

v

C16 
Interconnect

v

v

v

v

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February 2007

Global Clock Network & Phase-Locked Loops

Global Clock 
Network & 
Phase-Locked 
Loops

Cyclone II devices provide global clock networks and up to four PLLs for 
a complete clock management solution. Cyclone II clock network features 
include:

■

Up to 16 global clock networks

■

Up to four PLLs

■

Global clock network dynamic clock source selection

■

Global clock network dynamic enable and disable

LE

v

v

v

v

v

M4K memory 
Block

v

v

v

v

Embedded 
Multipliers

v

v

v

v

PLL

v

v

v

Column IOE

v

v

Row IOE

v

v

v

v

Table 2–1. Cyclone II Device Routing Scheme (Part 2 of 2)

Source

Destination

Register Chain

Local Inte

rconn

ect

Direct Link 

Interconnect

R4 Interco

nnect

R24 Interconnect

C4 Interconnect

C16 Inter

connect

LE

M4K

 R

A

M 

Bl

ock

Embedded Multiplier

PL

L

Col

u

mn IO

E

Row IO

E

Altera Corporation 

2–17

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Each global clock network has a clock control block to select from a 
number of input clock sources (PLL clock outputs, 

CLK[]

 pins, 

DPCLK[]

 

pins, and internal logic) to drive onto the global clock network. 

Table 2–2

 

lists how many PLLs, 

CLK[]

 pins, 

DPCLK[]

 pins, and global clock 

networks are available in each Cyclone II device. 

CLK[]

 pins are 

dedicated clock pins and 

DPCLK[]

 pins are dual-purpose clock pins.

Figures 2–11

 and 

2–12

 show the location of the Cyclone II PLLs, 

CLK[]

 

inputs, 

DPCLK[]

 pins, and clock control blocks. 

Table 2–2. Cyclone II Device Clock Resources

Device

Number of 

PLLs

Number of 

CLK Pins

Number of 

DPCLK Pins

Number of 

Global Clock 

Networks

EP2C5

2

8

8

8

EP2C8

2

8

8

8

EP2C15

4

16

20

16

EP2C20

4

16

20

16

EP2C35

4

16

20

16

EP2C50

4

16

20

16

EP2C70

4

16

20

16

2–18

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2007

Global Clock Network & Phase-Locked Loops

Figure 2–11. EP2C5 & EP2C8 PLL, CLK[], DPCLK[] & Clock Control Block Locations

Note to 

Figure 2–11

:

(1)

There are four clock control blocks on each side.

PLL 2

CLK[7..4]

DPCLK7

DPCLK6

CLK[3..0]

DPCLK0

DPCLK1

DPCLK10

DPCLK8

DPCLK2

GCLK[7..0]

GCLK[7..0]

DPCLK4

PLL 1

8

8

8

8

Clock Control

Block (1)

Clock Control

Block (1)

4

4

4

4

Altera Corporation 

2–19

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Figure 2–12. EP2C15 & Larger PLL, CLK[], DPCLK[] & Clock Control Block Locations

Notes to 

Figure 2–12

:

(1)

There are four clock control blocks on each side.

(2)

Only one of the corner 

CDPCLK

 pins in each corner can feed the clock control block at a time. The other 

CDPCLK

 pins 

can be used as general-purpose I/O pins.

PLL 4

PLL 3

PLL 2

CLK[7..4]

DPCLK7

CDPCLK5

CDPCLK4

DPCLK6

CLK[3..0]

DPCLK0

CDPCLK0

CDPCLK1

DPCLK1

CDPCLK7

DPCLK[9..8]

DPCLK[11..10]

CLK[11..8]

GCLK[15..0]

GCLK[15..0]

PLL 1

CDPCLK6

CDPCLK2

DPCLK[5..4]

DPCLK[3..2]

CLK[15..12]

CDPCLK3

Clock Control

Block (1)

Clock Control

Block (1)

16

16

16

16

2

2

4

4

4

4

4

2

2

4

(2)

(2)

(2)

(2)

4

4

3

3

3

3

2–20

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2007

Global Clock Network & Phase-Locked Loops

Dedicated Clock Pins

Larger Cyclone II devices (EP2C15 and larger devices) have 16 dedicated 
clock pins (

CLK[15..0]

, four pins on each side of the device). Smaller 

Cyclone II devices (EP2C5 and EP2C8 devices) have eight dedicated clock 
pins (

CLK[7..0]

, four pins on left and right sides of the device). These 

CLK

 pins drive the global clock network (GCLK), as shown in 

Figures 2–11

 and 

2–12

.

If the dedicated clock pins are not used to feed the global clock networks, 
they can be used as general-purpose input pins to feed the logic array 
using the MultiTrack interconnect. However, if they are used as general-
purpose input pins, they do not have support for an I/O register and 
must use LE-based registers in place of an I/O register.

Dual-Purpose Clock Pins

Cyclone II devices have either 20 dual-purpose clock pins, 

DPCLK[19..0]

 or 8 dual-purpose clock pins, 

DPCLK[7..0]

. In the 

larger Cyclone II devices (EP2C15 devices and higher), there are 
20

DPCLK

 pins; four on the left and right sides and six on the top and 

bottom of the device. The corner 

CDPCLK

 pins are first multiplexed before 

they drive into the clock control block. Since the signals pass through a 
multiplexer before feeding the clock control block, these signals incur 
more delay to the clock control block than other 

DPCLK

 pins that directly 

feed the clock control block. In the smaller Cyclone II devices (EP2C5 and 
EP2C8 devices), there are eight 

DPCLK

 pins; two on each side of the device 

(see 

Figures 2–11

 and 

2–12

).

A programmable delay chain is available from the 

DPCLK

 pin to its fan-

out destinations. To set the propagation delay from the 

DPCLK

 pin to its 

fan-out destinations, use the 

Input Delay from Dual-Purpose Clock Pin 

to Fan-Out Destinations

 assignment in the Quartus II software.

These dual-purpose pins can connect to the global clock network for 
high-fanout control signals such as clocks, asynchronous clears, presets, 
and clock enables, or protocol control signals such as 

TRDY

 and 

IRDY

 for 

PCI, or DQS signals for external memory interfaces.

Altera Corporation 

2–21

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Global Clock Network

The 16 or 8 global clock networks drive throughout the entire device. 
Dedicated clock pins (

CLK[]

), PLL outputs, the logic array, and 

dual-purpose clock (

DPCLK[]

) pins can also drive the global clock 

network. 

The global clock network can provide clocks for all resources within the 
device, such as IOEs, LEs, memory blocks, and embedded multipliers. 
The global clock lines can also be used for control signals, such as clock 
enables and synchronous or asynchronous clears fed from the external 
pin, or DQS signals for DDR SDRAM or QDRII SRAM interfaces. Internal 
logic can also drive the global clock network for internally generated 
global clocks and asynchronous clears, clock enables, or other control 
signals with large fan-out.

Clock Control Block

There is a clock control block for each global clock network available in 
Cyclone II devices. The clock control blocks are arranged on the device 
periphery and there are a maximum of 16 clock control blocks available 
per Cyclone II device. The larger Cyclone II devices (EP2C15 devices and 
larger) have 16 clock control blocks, four on each side of the device. The 
smaller Cyclone II devices (EP2C5 and EP2C8 devices) have eight clock 
control blocks, four on the left and right sides of the device.

The control block has these functions:

■

Dynamic global clock network clock source selection 

■

Dynamic enable/disable of the global clock network 

In Cyclone II devices, the dedicated 

CLK[]

 pins, PLL counter outputs, 

DPCLK[]

 pins, and internal logic can all feed the clock control block. The 

output from the clock control block in turn feeds the corresponding 
global clock network. 

The following sources can be inputs to a given clock control block:

■

Four clock pins on the same side as the clock control block

■

Three PLL clock outputs from a PLL

■

Four 

DPCLK

 pins (including 

CDPCLK

 pins) on the same side as the 

clock control block

■

Four internally-generated signals

2–22

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2007

Global Clock Network & Phase-Locked Loops

Of the sources listed, only two clock pins, two PLL clock outputs, one 

DPCLK

 pin, and one internally-generated signal are chosen to drive into a 

clock control block. 

Figure 2–13

 shows a more detailed diagram of the 

clock control block. Out of these six inputs, the two clock input pins and 
two PLL outputs can be dynamic selected to feed a global clock network. 
The clock control block supports static selection of 

DPCLK

 and the signal 

from internal logic.

Figure 2–13. Clock Control Block

Notes to 

Figure 2–13

:

(1)

The 

CLKSWITCH

 signal can either be set through the configuration file or it can be dynamically set when using the 

manual PLL switchover feature. The output of the multiplexer is the input reference clock (f

IN

) for the PLL. 

(2)

The 

CLKSELECT[1..0]

 signals are fed by internal logic and can be used to dynamically select the clock source for 

the global clock network when the device is in user mode.

(3)

The static clock select signals are set in the configuration file and cannot be dynamically controlled when the device 
is in user mode.

(4)

Internal logic can be used to enabled or disabled the global clock network in user mode.

CLKSWITCH 

(1)

Static Clock Select 

(3)

Static Clock

Select 

(3)

Internal Logic

Clock Control Block

DPCLK or

CDPCLK

CLKSELECT[1..0] 

(2)

CLKENA 

(4)

inclk1
inclk0

CLK[

n

 + 3]

CLK[

n

 + 2]

CLK[

n

 + 1]

CLK[

n

]

f

IN

C0
C1
C2

PLL

Global
Clock

Enable/
Disable

(3)

Altera Corporation 

2–23

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Global Clock Network Distribution

Cyclone II devices contains 16 global clock networks. The device uses 
multiplexers with these clocks to form six-bit buses to drive column IOE 
clocks, LAB row clocks, or row IOE clocks (see 

Figure 2–14

). Another 

multiplexer at the LAB level selects two of the six LAB row clocks to feed 
the LE registers within the LAB.

Figure 2–14. Global Clock Network Multiplexers

LAB row clocks can feed LEs, M4K memory blocks, and embedded 
multipliers. The LAB row clocks also extend to the row I/O clock regions.

IOE clocks are associated with row or column block regions. Only six 
global clock resources feed to these row and column regions. 

Figure 2–15

 

shows the I/O clock regions. 

Clock [15 or 7..0]

Row I/O Region
IO_CLK [5..0]

Column I/O Region
IO_CLK [5..0]

LAB Row Clock 
LABCLK[5..0]

Global Clock

Network

2–24

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2007

Global Clock Network & Phase-Locked Loops

Figure 2–15. LAB & I/O Clock Regions

f

For more information on the global clock network and the clock control 
block, see the 

PLLs in Cyclone II Devices

 chapter in Volume 1 of the 

Cyclone II Device Handbook

.

Column I/O Clock Region

IO_CLK[5..0]

Column I/O Clock Region

IO_CLK[5..0]

6

6

I/O Clock Regions

I/O Clock Regions

8 or 16

Global Clock
Network

Row I/O Clock
Region
IO_CLK[5..0]

Cyclone Logic Array

6

6

LAB Row Clocks

labclk[5..0]

LAB Row Clocks

labclk[5..0]

LAB Row Clocks

labclk[5..0]

LAB Row Clocks

labclk[5..0]

LAB Row Clocks

labclk[5..0]

LAB Row Clocks

labclk[5..0]

6

6

6

6

6

6

6

6

6

6

Altera Corporation 

2–25

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

PLLs

Cyclone II PLLs provide general-purpose clocking as well as support for 
the following features:

■

Clock multiplication and division

■

Phase shifting

■

Programmable duty cycle

■

Up to three internal clock outputs

■

One dedicated external clock output

■

Clock outputs for differential I/O support

■

Manual clock switchover

■

Gated lock signal

■

Three different clock feedback modes

■

Control signals

Cyclone II devices contain either two or four PLLs. 

Table 2–3

 shows the 

PLLs available for each Cyclone II device.

Table 2–3. Cyclone II Device PLL Availability

Device

PLL1

PLL2

PLL3

PLL4

EP2C5

v

v

EP2C8

v

v

EP2C15

v

v

v

v

EP2C20

v

v

v

v

EP2C35

v

v

v

v

EP2C50

v

v

v

v

EP2C70

v

v

v

v

2–26

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2007

Global Clock Network & Phase-Locked Loops

Table 2–4

 describes the PLL features in Cyclone II devices. 

Table 2–4. Cyclone II PLL Features

Feature

Description

Clock multiplication and division

m

 / (

n

 × post-scale counter) 

m

 and post-scale counter values (C0 to C2) range from 1 to 32. 

n

 ranges 

from 1 to 4.

Phase shift

Cyclone II PLLs have an advanced clock shift capability that enables 
programmable phase shifts in increments of at least 45°. The finest 
resolution of phase shifting is determined by the voltage control oscillator 
(VCO) period divided by 8 (for example, 1/1000 MHz/8 = down to 125-ps 
increments). 

Programmable duty cycle

The programmable duty cycle allows PLLs to generate clock outputs with 
a variable duty cycle. This feature is supported on each PLL post-scale 
counter (C0-C2). 

Number of internal clock outputs

The Cyclone II PLL has three outputs which can drive the global clock 
network. One of these outputs (C2) can also drive a dedicated 

PLL

<

#

>

_OUT

 pin (single ended or differential). 

Number of external clock outputs 

The C2 output drives a dedicated 

PLL

<

#

>

_OUT

 pin. If the C2 output is not 

used to drive an external clock output, it can be used to drive the internal 
global clock network. The C2 output can concurrently drive the external 
clock output and internal global clock network. 

Manual clock switchover

The Cyclone II PLLs support manual switchover of the reference clock 
through internal logic. This enables you to switch between two reference 
input clocks during user mode for applications that may require clock 
redundancy or support for clocks with two different frequencies.

Gated lock signal

The lock output indicates that there is a stable clock output signal in phase 
with the reference clock. Cyclone II PLLs include a programmable counter 
that holds the lock signal low for a user-selected number of input clock 
transitions, allowing the PLL to lock before enabling the locked signal. 
Either a gated locked signal or an ungated locked signal from the locked 
port can drive internal logic or an output pin.

Clock feedback modes

In zero delay buffer mode, the external clock output pin is phase-aligned 
with the clock input pin for zero delay. 
In normal mode, the PLL compensates for the internal global clock network 
delay from the input clock pin to the clock port of the IOE output registers 
or registers in the logic array.
In no compensation mode, the PLL does not compensate for any clock 
networks.

Control signals 

The 

pllenable

 signal enables and disables the PLLs. 

The 

areset

 signal resets/resynchronizes the inputs for each PLL. 

The 

pfdena

 signal controls the phase frequency detector (PFD) output 

with a programmable gate.

Altera Corporation 

2–27

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Figure 2–16

 shows a block diagram of the Cyclone II PLL.

Figure 2–16. Cyclone II PLL

Note (1)

Notes to 

Figure 2–16

:

(1)

This input can be single-ended or differential. If you are using a differential I/O standard, then two 

CLK

 pins are 

used. LVDS input is supported via the secondary function of the dedicated 

CLK

 pins. For example, the 

CLK0

 pin’s 

secondary function is 

LVDSCLK1p

 and the 

CLK1

 pin’s secondary function is 

LVDSCLK1n

. If a differential I/O 

standard is assigned to the PLL clock input pin, the corresponding 

CLK(n)

 pin is also completely used. The 

Figure 2–16

 shows the possible clock input connections (

CLK0

/

CLK1

) to PLL1. 

(2)

This counter output is shared between a dedicated external clock output I/O and the global clock network.

f

For more information on Cyclone II PLLs, see the PLLs in the 

Cyclone II 

Devices

 chapter in Volume 1 of the 

Cyclone II Device Handbook

.

Embedded 
Memory

The Cyclone II embedded memory consists of columns of M4K memory 
blocks. The M4K memory blocks include input registers that synchronize 
writes and output registers to pipeline designs and improve system 
performance. The output registers can be bypassed, but input registers 
cannot. 

PFD

Loop
Filter

Lock Detect

& Filter

VCO

Charge

Pump

÷c0

÷c1

÷c2

÷

m

÷

n

Global
Clock

Global
Clock

Global
Clock

To I/O or
general routing

PLL<

#

>_OUT

Post-Scale

Counters

VCO Phase Selection

Selectable at Each 

PLL Output Port

CLK1

CLK3

CLK2 

(1)

CLK0 

(1)

inclk0

inclk1

up

down

8

8

8

f

VCO

f

FB

f

IN

Reference

Input Clock

f

REF

 = f

IN 

/

n

(2)

Manual Clock

Switchover

Select Signal

÷k

(3)

2–28

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2007

Embedded Memory

Each M4K block can implement various types of memory with or without 
parity, including true dual-port, simple dual-port, and single-port RAM, 
ROM, and first-in first-out (FIFO) buffers. The M4K blocks support the 
following features:

■

4,608 RAM bits

■

250-MHz performance

■

True dual-port memory

■

Simple dual-port memory

■

Single-port memory

■

Byte enable

■

Parity bits

■

Shift register

■

FIFO buffer

■

ROM

■

Various clock modes

■

Address clock enable

1

Violating the setup or hold time on the memory block address 
registers could corrupt memory contents. This applies to both 
read and write operations.

Table 2–5

 shows the capacity and distribution of the M4K memory blocks 

in each Cyclone II device.

Table 2–5. M4K Memory Capacity & Distribution in Cyclone II Devices

Device

M4K Columns

M4K Blocks

Total RAM Bits

EP2C5

2

26

119,808

EP2C8

2

36

165,888

EP2C15

2

52

239,616

EP2C20

2

52

239,616

EP2C35

3

105

483,840

EP2C50

3

129

594,432

EP2C70

5

250

1,152,000

Altera Corporation 

2–29

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Table 2–6

 summarizes the features supported by the M4K memory.

Table 2–6. M4K Memory Features

Feature

Description

Maximum performance 

(1)

250 MHz

Total RAM bits per M4K block (including parity bits)

4,608

Configurations supported

4K × 1
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32 (not available in true dual-port mode)
128 × 36 (not available in true dual-port mode)

Parity bits

One parity bit for each byte. The parity bit, along with 
internal user logic, can implement parity checking for 
error detection to ensure data integrity. 

Byte enable

M4K blocks support byte writes when the write port has 
a data width of 1, 2, 4, 8, 9, 16, 18, 32, or 36 bits. The 
byte enables allow the input data to be masked so the 
device can write to specific bytes. The unwritten bytes 
retain the previous written value. 

Packed mode

Two single-port memory blocks can be packed into a 
single M4K block if each of the two independent block 
sizes are equal to or less than half of the M4K block 
size, and each of the single-port memory blocks is 
configured in single-clock mode.

Address clock enable

M4K blocks support address clock enable, which is 
used to hold the previous address value for as long as 
the signal is enabled. This feature is useful in handling 
misses in cache applications.

Memory initialization file (

.mif

)

When configured as RAM or ROM, you can use an 
initialization file to pre-load the memory contents.

Power-up condition

Outputs cleared

Register clears

Output registers only

Same-port read-during-write

New data available at positive clock edge

Mixed-port read-during-write

Old data available at positive clock edge

Note to 

Table 2–6

:

(1)

Maximum performance information is preliminary until device characterization.

2–30

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2007

Embedded Memory

Memory Modes

Table 2–7

 summarizes the different memory modes supported by the 

M4K memory blocks.

1

Embedded Memory can be inferred in your HDL code or 
directly instantiated in the Quartus II software using the 
MegaWizard

®

 Plug-in Manager Memory Compiler feature.

Table 2–7. M4K Memory Modes

Memory Mode

Description

Single-port memory

M4K blocks support single-port mode, used when 
simultaneous reads and writes are not required. 
Single-port memory supports non-simultaneous 
reads and writes.

Simple dual-port memory

Simple dual-port memory supports a 
simultaneous read and write.

Simple dual-port with mixed 
width 

Simple dual-port memory mode with different 
read and write port widths.

True dual-port memory

True dual-port mode supports any combination of 
two-port operations: two reads, two writes, or one 
read and one write at two different clock 
frequencies.

True dual-port with mixed 
width 

True dual-port mode with different read and write 
port widths.

Embedded shift register

M4K memory blocks are used to implement shift 
registers. Data is written into each address 
location at the falling edge of the clock and read 
from the address at the rising edge of the clock.

ROM

The M4K memory blocks support ROM mode. A 
MIF initializes the ROM contents of these blocks.

FIFO buffers

A single clock or dual clock FIFO may be 
implemented in the M4K blocks. Simultaneous 
read and write from an empty FIFO buffer is not 
supported.

Altera Corporation 

2–31

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Clock Modes

Table 2–8

 summarizes the different clock modes supported by the M4K 

memory.

Table 2–9

 shows which clock modes are supported by all M4K blocks 

when configured in the different memory modes. 

M4K Routing Interface

The R4, C4, and direct link interconnects from adjacent LABs drive the 
M4K block local interconnect. The M4K blocks can communicate with 
LABs on either the left or right side through these row resources or with 
LAB columns on either the right or left with the column resources. Up to 
16 direct link input connections to the M4K block are possible from the 
left adjacent LAB and another 16 possible from the right adjacent LAB. 
M4K block outputs can also connect to left and right LABs through each 
16 direct link interconnects. 

Figure 2–17

 shows the M4K block to logic 

array interface.

Table 2–8. M4K Clock Modes

Clock Mode

Description

Independent

In this mode, a separate clock is available for each port (ports A 
and B). Clock A controls all registers on the port A side, while 
clock B controls all registers on the port B side. 

Input/output

On each of the two ports, A or B, one clock controls all registers 
for inputs into the memory block: data input, 

wren

, and address. 

The other clock controls the block’s data output registers. 

Read/write

Up to two clocks are available in this mode. The write clock 
controls the block’s data inputs, 

wraddress

, and 

wren

. The 

read clock controls the data output, 

rdaddress

, and 

rden

. 

Single

In this mode, a single clock, together with clock enable, is used to 
control all registers of the memory block. Asynchronous clear 
signals for the registers are not supported.

Table 2–9. Cyclone II M4K Memory Clock Modes

Clocking Modes

True Dual-Port 

Mode

Simple Dual-Port 

Mode

Single-Port Mode

Independent

v

Input/output

v

v

v

Read/write

v

Single clock

v

v

v

2–32

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Cyclone II Device Handbook, Volume 1

February 2007

Embedded Multipliers

Figure 2–17. M4K RAM Block LAB Row Interface

f

For more information on Cyclone II embedded memory, see the 

Cyclone II Memory Blocks

 chapter in Volume 1 of the 

Cyclone II Device 

Handbook

.

Embedded 
Multipliers

Cyclone II devices have embedded multiplier blocks optimized for 
multiplier-intensive digital signal processing (DSP) functions, such as 
finite impulse response (FIR) filters, fast Fourier transform (FFT) 
functions, and discrete cosine transform (DCT) functions. You can use the 
embedded multiplier in one of two basic operational modes, depending 
on the application needs:

■

One 18-bit multiplier

■

Up to two independent 9-bit multipliers

dataout

M4K RAM

Block

datain

address

16

16

16

Direct link 
interconnect
from adjacent LAB

Direct link 
interconnect
to adjacent LAB

Direct link 
interconnect
from adjacent LAB

Direct link 
interconnect
to adjacent LAB

M4K RAM Block Local
Interconnect Region

C4 Interconnects

R4 Interconnects

LAB Row Clocks

Clocks

Byte enable

Control

Signals

6

Altera Corporation 

2–33

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Embedded multipliers can operate at up to 250 MHz (for the fastest speed 
grade) for 18 × 18 and 9 × 9 multiplications when using both input and 
output registers.

Each Cyclone II device has one to three columns of embedded multipliers 
that efficiently implement multiplication functions. An embedded 
multiplier spans the height of one LAB row. 

Table 2–10

 shows the number 

of embedded multipliers in each Cyclone II device and the multipliers 
that can be implemented.

The embedded multiplier consists of the following elements:

■

Multiplier block

■

Input and output registers

■

Input and output interfaces

Figure 2–18

 shows the multiplier block architecture.

Table 2–10. Number of Embedded Multipliers in Cyclone II Devices

Note (1)

Device

Embedded 

Multiplier Columns

Embedded 

Multipliers

9 × 9 Multipliers

18 × 18 Multipliers

EP2C5

1

13

26

13

EP2C8

1

18

36

18

EP2C15

1

26

52

26

EP2C20

1

26

52

26

EP2C35

1

35

70

35

EP2C50

2

86

172

86

EP2C70

3

150

300

150

Note to 

Table 2–10

:

(1)

Each device has either the number of 9 × 9-, or 18 × 18-bit multipliers shown. The total number of multipliers for 
each device is not the sum of all the multipliers.

2–34

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2007

Embedded Multipliers

Figure 2–18. Multiplier Block Architecture

Note to 

Figure 2–18

:

(1)

If necessary, these signals can be registered once to match the data signal path.

Each multiplier operand can be a unique signed or unsigned number. 
Two signals, 

signa

 and 

signb

, control the representation of each 

operand respectively. A logic 1 value on the 

signa

 signal indicates that 

data A is a signed number while a logic 0 value indicates an unsigned 
number. 

Table 2–11

 shows the sign of the multiplication result for the 

various operand sign representations. The result of the multiplication is 
signed if any one of the operands is a signed value. 

CLRN

D

Q

ENA

Data A

Data B

aclr

clock

ena

signa 

(1)

signb 

(1)

CLRN

D

Q

ENA

CLRN

D

Q

ENA

Data Out

Embedded Multiplier Block

Output

Register

Input

Register

Table 2–11. Multiplier Sign Representation

Data A (signa Value)

Data B (signb Value)

Result

Unsigned

Unsigned

Unsigned

Unsigned

Signed

Signed

Signed

Unsigned

Signed

Signed

Signed

Signed

Altera Corporation 

2–35

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

There is only one 

signa

 and one 

signb

 signal for each dedicated 

multiplier. Therefore, all of the data A inputs feeding the same dedicated 
multiplier must have the same sign representation. Similarly, all of the 
data B inputs feeding the same dedicated multiplier must have the same 
sign representation. The 

signa

 and 

signb

 signals can be changed 

dynamically to modify the sign representation of the input operands at 
run time. The multiplier offers full precision regardless of the sign 
representation and can be registered using dedicated registers located at 
the input register stage.

Multiplier Modes 

Table 2–12

 summarizes the different modes that the embedded 

multipliers can operate in.

Table 2–12. Embedded Multiplier Modes 

Multiplier Mode

Description

18-bit Multiplier

An embedded multiplier can be configured to support a 
single 18 × 18 multiplier for operand widths up to 18 bits. 
All 18-bit multiplier inputs and results can be registered 
independently. The multiplier operands can accept 
signed integers, unsigned integers, or a combination of 
both. 

9-bit Multiplier

An embedded multiplier can be configured to support 
two 9 × 9 independent multipliers for operand widths up 
to 9-bits. Both 9-bit multiplier inputs and results can be 
registered independently. The multiplier operands can 
accept signed integers, unsigned integers or a 
combination of both. 
There is only one 

signa

 signal to control the sign 

representation of both data A inputs and one 

signb

 

signal to control the sign representation of both data B 
inputs of the 9-bit multipliers within the same dedicated 
multiplier.

2–36

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2007

Embedded Multipliers

Embedded Multiplier Routing Interface

The R4, C4, and direct link interconnects from adjacent LABs drive the 
embedded multiplier row interface interconnect. The embedded 
multipliers can communicate with LABs on either the left or right side 
through these row resources or with LAB columns on either the right or 
left with the column resources. Up to 16 direct link input connections to 
the embedded multiplier are possible from the left adjacent LABs and 
another 16 possible from the right adjacent LAB. Embedded multiplier 
outputs can also connect to left and right LABs through 18 direct link 
interconnects each. 

Figure 2–19

 shows the embedded multiplier to logic 

array interface.

Figure 2–19. Embedded Multiplier LAB Row Interface

LAB

LAB

Row Interface

Block

Embedded Multiplier

16

[35..0]

[35..0]

Embedded Multiplier
to LAB Row Interface
Block Interconnect Region

36 Inputs per Row

36 Outputs per Row

R4 Interconnects

C4 Interconnects

C4 Interconnects

Direct Link Interconnect
from Adjacent LAB

18 Direct Link Outputs
to Adjacent LABs

Direct Link Interconnect
from Adjacent LAB

18

18

36

36

Control

5

18

18

16

LAB Block

Interconect Region

LAB Block

Interconect Region

Altera Corporation 

2–37

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

There are five dynamic control input signals that feed the embedded 
multiplier: 

signa

, 

signb

, 

clk

, 

clkena

, and 

aclr

. 

signa

 and 

signb

 

can be registered to match the data signal input path. The same 

clk

, 

clkena

, and 

aclr

 signals feed all registers within a single embedded 

multiplier. 

f

For more information on Cyclone II embedded multipliers, see the 

Embedded Multipliers in Cyclone II Devices

 chapter.

I/O Structure & 
Features

IOEs support many features, including:

■

Differential and single-ended I/O standards

■

3.3-V, 64- and 32-bit, 66- and 33-MHz PCI compliance

■

Joint Test Action Group (JTAG) boundary-scan test (BST) support

■

Output drive strength control

■

Weak pull-up resistors during configuration

■

Tri-state buffers

■

Bus-hold circuitry

■

Programmable pull-up resistors in user mode

■

Programmable input and output delays

■

Open-drain outputs

■

DQ and DQS I/O pins 

■

V

REF

 pins

Cyclone II device IOEs contain a bidirectional I/O buffer and three 
registers for complete embedded bidirectional single data rate transfer. 

Figure 2–20

 shows the Cyclone II IOE structure. The IOE contains one 

input register, one output register, and one output enable register. You can 
use the input registers for fast setup times and output registers for fast 
clock-to-output times. Additionally, you can use the output enable (OE) 
register for fast clock-to-output enable timing. The Quartus II software 
automatically duplicates a single OE register that controls multiple 
output or bidirectional pins. You can use IOEs as input, output, or 
bidirectional pins.

2–38

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2007

I/O Structure & Features

Figure 2–20. Cyclone II IOE Structure

Note to 

Figure 2–20

:

(1)

There are two paths available for combinational or registered inputs to the logic 
array. Each path contains a unique programmable delay chain.

The IOEs are located in I/O blocks around the periphery of the Cyclone II 
device. There are up to five IOEs per row I/O block and up to four IOEs 
per column I/O block (column I/O blocks span two columns). The row 
I/O blocks drive row, column (only C4 interconnects), or direct link 
interconnects. The column I/O blocks drive column interconnects. 

Figure 2–21

 shows how a row I/O block connects to the logic array. 

Figure 2–22

 shows how a column I/O block connects to the logic array.

Output Register

Output

Input 

(1)

OE Register

OE

Input Register

Logic Array

Altera Corporation 

2–39

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Figure 2–21. Row I/O Block Connection to the Interconnect

Notes to 

Figure 2–21

:

(1)

The 35 data and control signals consist of five data out lines, 

io_dataout[4..0]

, five output enables, 

io_coe[4..0]

, five input clock enables, 

io_cce_in[4..0]

, five output clock enables, 

io_cce_out[4..0]

, 

five clocks, 

io_cclk[4..0]

, five asynchronous clear signals, 

io_caclr[4..0]

, and five synchronous clear 

signals, 

io_csclr[4..0]

.

(2)

Each of the five IOEs in the row I/O block can have two 

io_datain

 (combinational or registered) inputs.

35

R4 & R24 Interconnects

C4 Interconnects

I/O Block Local 

Interconnect

35 Data and
Control Signals
from Logic Array (1)

io_datain0[4..0] 
io_datain1[4..0] 

(2)

io_clk[5..0]

Row I/O Block

Contains up to

Five IOEs

Direct Link

Interconnect

to Adjacent LAB

Direct Link

Interconnect

from Adjacent LAB

LAB Local
Interconnect

LAB

Row

I/O Block

2–40

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2007

I/O Structure & Features

Figure 2–22. Column I/O Block Connection to the Interconnect

Notes to 

Figure 2–22

:

(1)

The 28 data and control signals consist of four data out lines, 

io_dataout[3..0]

, four output enables, 

io_coe[3..0]

, four input clock enables, 

io_cce_in[3..0]

, four output clock enables, 

io_cce_out[3..0]

, 

four clocks, 

io_cclk[3..0]

, four asynchronous clear signals, 

io_caclr[3..0]

, and four synchronous clear 

signals, 

io_csclr[3..0]

.

(2)

Each of the four IOEs in the column I/O block can have two 

io_datain

 (combinational or registered) inputs.

2

8

 Data &

Control Signals 

from Logic Array (1)

Column I/O 
Block Contains
up to Four  IOEs

I/O Block

Local Interconnect

io_datain0[3..0]
io_datain1[3..0] (2)

R4 & R24 Interconnects

LAB Local
Interconnect

C4 & C24 Interconnects

28

LAB

LAB

LAB

io_clk[5..0]

Column I/O Block

Altera Corporation 

2–41

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

The pin’s 

datain

 signals can drive the logic array. The logic array drives 

the control and data signals, providing a flexible routing resource. The 
row or column IOE clocks, 

io_clk[5..0]

, provide a dedicated routing 

resource for low-skew, high-speed clocks. The global clock network 
generates the IOE clocks that feed the row or column I/O regions (see 

“Global Clock Network & Phase-Locked Loops” on page 2–16

). 

Figure 2–23

 illustrates the signal paths through the I/O block.

Figure 2–23. Signal Path Through the I/O Block

Each IOE contains its own control signal selection for the following 
control signals: 

oe

, 

ce_in

, 

ce_out

, 

aclr

/

preset

, 

sclr

/

preset

, 

clk_in

, and 

clk_out

. 

Figure 2–24

 illustrates the control signal 

selection.

Row or Column

io_clk[5..0]

io_datain0

io_datain1

io_dataout

io_coe

oe

ce_in

ce_out

io_cce_in

aclr/preset

io_cce_out

sclr/preset

io_caclr

clk_in

io_cclk

clk_out

dataout

Data and

Control

Signal

Selection

IOE

To Logic

Array

From Logic

Array

To Other
IOEs

io_csclr

2–42

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2007

I/O Structure & Features

Figure 2–24. Control Signal Selection per IOE

In normal bidirectional operation, you can use the input register for input 
data requiring fast setup times. The input register can have its own clock 
input and clock enable separate from the 

OE

 and output registers. You can 

use the output register for data requiring fast clock-to-output 
performance. The 

OE

 register is available for fast clock-to-output enable 

timing. The 

OE

 and output register share the same clock source and the 

same clock enable source from the local interconnect in the associated 
LAB, dedicated I/O clocks, or the column and row interconnects. All 
registers share 

sclr

 and 

aclr

, but each register can individually disable 

sclr

 and 

aclr

. 

Figure 2–25

 shows the IOE in bidirectional 

configuration.

clk_out

ce_in

clk_in

ce_out

aclr/preset

sclr/preset

Dedicated I/O
Clock [5..0]

Local
Interconnect

Local
Interconnect

Local
Interconnect

Local
Interconnect

Local
Interconnect

oe

io_coe

io_caclr

Local
Interconnect

io_csclr

io_cce_out

io_cce_in

io_cclk

Altera Corporation 

2–43

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Figure 2–25. Cyclone II IOE in Bidirectional I/O Configuration

The Cyclone II device IOE includes programmable delays to ensure zero 
hold times, minimize setup times, or increase clock to output times.

A path in which a pin directly drives a register may require a 
programmable delay to ensure zero hold time, whereas a path in which a 
pin drives a register through combinational logic may not require the 
delay. Programmable delays decrease input-pin-to-logic-array and IOE 
input register delays. The Quartus II Compiler can program these delays 
to automatically minimize setup time while providing a zero hold time. 

Chip-

W

ide Reset

OE Register

V

CCIO

Optio

n

al

PCI Clamp

Col

u

mn

or Ro

w

Interconect

io_clk[5..0]

Inp

u

t Register

Inp

u

t Pin to

Inp

u

t Register Delay

or Inp

u

t Pin to

Logic Array Delay

Open-Drain O

u

tp

u

t

sclr/preset

OE

clko

u

t

ce_o

u

t

aclr/prn

clkin

ce_in

O

u

tp

u

t

Pin Delay

P

r

og

r

ammable

P

u

ll-Up

Re

s

i

s

to

r

B

us

 Hold

PR

N

CLR

N

D

Q

O

u

tp

u

t Register

PR

N

CLR

N

D

Q

PR

N

CLR

N

D

Q

V

CCIO

data_in0

data_in1

E

N

A

E

N

A

E

N

A

2–44

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2007

I/O Structure & Features

Programmable delays can increase the register-to-pin delays for output 
registers. 

Table 2–13

 shows the programmable delays for Cyclone II 

devices.

There are two paths in the IOE for an input to reach the logic array. Each 
of the two paths can have a different delay. This allows you to adjust 
delays from the pin to internal LE registers that reside in two different 
areas of the device. You set the two combinational input delays by 
selecting different delays for two different paths under the 

Input delay 

from pin to internal cells logic

 option in the Quartus II software. 

However, if the pin uses the input register, one of delays is disregarded 
because the IOE only has two paths to internal logic. If the input register 
is used, the IOE uses one input path. The other input path is then 
available for the combinational path, and only one input delay 
assignment is applied.

The IOE registers in each I/O block share the same source for clear or 
preset. You can program preset or clear for each individual IOE, but both 
features cannot be used simultaneously. You can also program the 
registers to power up high or low after configuration is complete. If 
programmed to power up low, an asynchronous clear can control the 
registers. If programmed to power up high, an asynchronous preset can 
control the registers. This feature prevents the inadvertent activation of 
another device’s active-low input upon power up. If one register in an 
IOE uses a preset or clear signal then all registers in the IOE must use that 
same signal if they require preset or clear. Additionally a synchronous 
reset signal is available for the IOE registers. 

External Memory Interfacing 

Cyclone II devices support a broad range of external memory interfaces 
such as SDR SDRAM, DDR SDRAM, DDR2 SDRAM, and QDRII SRAM 
external memories. Cyclone II devices feature dedicated high-speed 
interfaces that transfer data between external memory devices at up to 
167 MHz/333 Mbps for DDR and DDR2 SDRAM devices and 
167 MHz/667 Mbps for QDRII SRAM devices. The programmable DQS 
delay chain allows you to fine tune the phase shift for the input clocks or 
strobes to properly align clock edges as needed to capture data.

Table 2–13. Cyclone II Programmable Delay Chain

Programmable Delays

Quartus II Logic Option

Input pin to logic array delay

Input delay from pin to internal cells

Input pin to input register delay

Input delay from pin to input register

Output pin delay

Delay from output register to output pin

Altera Corporation 

2–45

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

In Cyclone II devices, all the I/O banks support SDR and DDR SDRAM 
memory up to 167 MHz/333 Mbps. All I/O banks support DQS signals 
with the DQ bus modes of ×8/×9, or ×16/×18. 

Table 2–14

 shows the 

external memory interfaces supported in Cyclone II devices.

Cyclone II devices use data (DQ), data strobe (DQS), and clock pins to 
interface with external memory. 

Figure 2–26

 shows the DQ and DQS pins 

in the ×8/×9 mode. 

Table 2–14. External Memory Support in Cyclone II Devices

Note (1)

Memory Standard

I/O Standard

Maximum Bus 

Width

Maximum Clock 

Rate Supported 

(MHz)

Maximum Data 

Rate Supported 

(Mbps)

SDR SDRAM

LVTTL 

(2)

72

167

167

DDR SDRAM

SSTL-2 class I 

(2)

72

167

333 

(1)

SSTL-2 class II 

(2)

72

133

267 

(1)

DDR2 SDRAM

SSTL-18 class I 

(2)

72

167

333 

(1)

SSTL-18 class II 

(3)

72

125

250 

(1)

QDRII SRAM 

(4)

1.8-V HSTL class I 

(2)

36

167

668 

(1)

1.8-V HSTL class II 

(3)

36

100

400 

(1)

Notes to 

Table 2–14

:

(1)

The data rate is for designs using the Clock Delay Control circuitry.

(2)

The I/O standards are supported on all the I/O banks of the Cyclone II device.

(3)

The I/O standards are supported only on the I/O banks on the top and bottom of the Cyclone II device.

(4)

For maximum performance, Altera recommends using the 1.8-V HSTL I/O standard because of higher I/O drive 
strength. QDRII SRAM devices also support the 1.5-V HSTL I/O standard.

2–46

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2007

I/O Structure & Features

Figure 2–26. Cyclone II Device DQ & DQS Groups in ×8/×9 Mode

Notes (1)

, 

(2)

Notes to 

Figure 2–26

:

(1)

Each DQ group consists of a DQS pin, DM pin, and up to nine DQ pins.

(2)

This is an idealized pin layout. For actual pin layout, refer to the pin table.

Cyclone II devices support the data strobe or read clock signal (DQS) 
used in DDR and DDR2 SDRAM. Cyclone II devices can use either 
bidirectional data strobes or unidirectional read clocks. The dedicated 
external memory interface in Cyclone II devices also includes 
programmable delay circuitry that can shift the incoming DQS signals to 
center align the DQS signals within the data window.

The DQS signal is usually associated with a group of data (DQ) pins. The 
phase-shifted DQS signals drive the global clock network, which is used 
to clock the DQ signals on internal LE registers.

Table 2–15

 shows the number of DQ pin groups per device.

DQ Pins

DQS Pin

DM Pin

DQ Pins

(2)

Table 2–15. Cyclone II DQS & DQ Bus Mode Support (Part 1 of 2)

Note (1)

Device

Package

Number of ×8 

Groups

Number of ×9 

Groups 

(5)

, 

(6)

Number of ×16 

Groups

Number of ×18 
Groups 

(5)

, 

(6)

EP2C5

144-pin TQFP 

(2)

3

3

0

0

208-pin PQFP 

7 

(3)

4

3

3

EP2C8

144-pin TQFP 

(2)

3

3

0

0

208-pin PQFP

7 

(3)

4

3

3

256-pin FineLine BGA

®

8 

(3)

4

4

4

EP2C15

256-pin FineLine BGA

8

4

4

4

484-pin FineLine BGA

16 

(4)

8

8

8

EP2C20

256-pin FineLine BGA

8

4

4

4

484-pin FineLine BGA

16 

(4)

8

8

8

Altera Corporation 

2–47

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

You can use any of the DQ pins for the parity pins in Cyclone II devices. 
The Cyclone II device family supports parity in the ×8/×9, and ×16/×18 
mode. There is one parity bit available per eight bits of data pins. 

The data mask, DM, pins are required when writing to DDR SDRAM and 
DDR2 SDRAM devices. A low signal on the DM pin indicates that the 
write is valid. If the DM signal is high, the memory masks the DQ signals. 
In Cyclone II devices, the DM pins are assigned and are the preferred 
pins. Each group of DQS and DQ signals requires a DM pin. 

When using the Cyclone II I/O banks to interface with the DDR memory, 
at least one PLL with two clock outputs is needed to generate the system 
and write clock. The system clock is used to clock the DQS write signals, 
commands, and addresses. The write clock is shifted by –90° from the 
system clock and is used to clock the DQ signals during writes.

Figure 2–27

 illustrates DDR SDRAM interfacing from the I/O through 

the dedicated circuitry to the logic array.

EP2C35

484-pin FineLine BGA

16 

(4)

8

8

8

672-pin FineLine BGA

20 

(4)

8

8

8

EP2C50

484-pin FineLine BGA

16 

(4)

8

8

8

672-pin FineLine BGA

20 

(4)

8

8

8

EP2C70

672-pin FineLine BGA

20 

(4)

8

8

8

896-pin FineLine BGA

20 

(4)

8

8

8

Notes to 

Table 2–15

:

(1)

Numbers are preliminary.

(2)

EP2C5 and EP2C8 devices in the 144-pin TQFP package do not have any DQ pin groups in I/O bank 1.

(3)

Because of available clock resources, only a total of 6 DQ/DQS groups can be implemented.

(4)

Because of available clock resources, only a total of 14 DQ/DQS groups can be implemented.

(5)

The ×9 DQS/DQ groups are also used as ×8 DQS/DQ groups. The ×18 DQS/DQ groups are also used as ×16 
DQS/DQ groups.

(6)

For QDRI implementation, if you connect the D ports (write data) to the Cyclone II DQ pins, the total available ×9 
DQS /DQ and ×18 DQS/DQ groups are half of that shown in 

Table 2–15

.

Table 2–15. Cyclone II DQS & DQ Bus Mode Support (Part 2 of 2)

Note (1)

Device

Package

Number of ×8 

Groups

Number of ×9 

Groups 

(5)

, 

(6)

Number of ×16 

Groups

Number of ×18 
Groups 

(5)

, 

(6)

2–48

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2007

I/O Structure & Features

Figure 2–27. DDR SDRAM Interfacing

f

For more information on Cyclone II external memory interfaces, see the 

External Memory Interfaces

 chapter in Volume 1 of the 

Cyclone II Device 

Handbook

.

DQS

OE

VCC

PLL

GND

clk

DQ

OE

DataA

DataB

Resynchronizing
to System Clock

Global Clock

Clock Delay

Control Circuitry

-90˚ Shifted clk

Adjacent LAB LEs

Clock Control

Block

LE

Register

LE

Register

LE

Register

LE

Register

t

en/dis

Dynamic Enable/Disable

Circuitry

ENOUT

ena_register_mode

LE

Register

LE

Register

LE

Register

LE

Register

LE

Register

LE

Register

LE

Register

LE

Register

LE

Register

Altera Corporation 

2–49

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Programmable Drive Strength

The output buffer for each Cyclone II device I/O pin has a programmable 
drive strength control for certain I/O standards. The LVTTL, LVCMOS, 
SSTL-2 class I and II, SSTL-18 class I and II, HSTL-18 class I and II, and 
HSTL-1.5 class I and II standards have several levels of drive strength that 
you can control. Using minimum settings provides signal slew rate 
control to reduce system noise and signal overshoot. 

Table 2–16

 shows 

the possible settings for the I/O standards with drive strength control.

Table 2–16. Programmable Drive Strength (Part 1 of 2)

Note (1)

I/O Standard

I

OH

/I

OL

 Current Strength Setting (mA)

Top & Bottom I/O Pins

Side I/O Pins

LVTTL (3.3 V)

4

4

8

8

12

12

16

16

20

20

24

24

LVCMOS (3.3 V)

4

4

8

8

12

12

16

20

24

LVTTL/LVCMOS (2.5 V)

4

4

8

8

12

16

LVTTL/LVCMOS (1.8 V)

2

2

4

4

6

6

8

8

10

10

12

12

2–50

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2007

I/O Structure & Features

Open-Drain Output

Cyclone II devices provide an optional open-drain (equivalent to an 
open-collector) output for each I/O pin. This open-drain output enables 
the device to provide system-level control signals (that is, interrupt and 
write-enable signals) that can be asserted by any of several devices.

LVCMOS (1.5 V)

2

2

4

4

6

6

8

SSTL-2 class I

8

8

12

12

SSTL-2 class II

16

16

20

24

SSTL-18 class I

6

6

8

8

10

10

12

SSTL-18 class II

16

18

HSTL-18 class I

8

8

10

10

12

12

HSTL-18 class II

16

18

20

HSTL-15 class I

8

8

10

12

HSTL-15 class II

16

Note to 

Table 2–16

:

(1)

The default current in the Quartus II software is the maximum setting for each 
I/O standard.

Table 2–16. Programmable Drive Strength (Part 2 of 2)

Note (1)

I/O Standard

I

OH

/I

OL

 Current Strength Setting (mA)

Top & Bottom I/O Pins

Side I/O Pins

Altera Corporation 

2–51

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

Slew Rate Control

Slew rate control is performed by using programmable output drive 
strength.

Bus Hold

Each Cyclone II device user I/O pin provides an optional bus-hold 
feature. The bus-hold circuitry can hold the signal on an I/O pin at its 
last-driven state. Since the bus-hold feature holds the last-driven state of 
the pin until the next input signal is present, an external pull-up or 
pull-down resistor is not necessary to hold a signal level when the bus is 
tri-stated.

The bus-hold circuitry also pulls undriven pins away from the input 
threshold voltage where noise can cause unintended high-frequency 
switching. You can select this feature individually for each I/O pin. The 
bus-hold output drives no higher than V

CCIO

 to prevent overdriving 

signals.

1

If the bus-hold feature is enabled, the device cannot use the 
programmable pull-up option. Disable the bus-hold feature 
when the I/O pin is configured for differential signals. Bus hold 
circuitry is not available on the dedicated clock pins.

The bus-hold circuitry is only active after configuration. When going into 
user mode, the bus-hold circuit captures the value on the pin present at 
the end of configuration.

The bus-hold circuitry uses a resistor with a nominal resistance (R

BH

) of 

approximately 7 k

Ω

 to pull the signal level to the last-driven state. Refer 

to the 

DC Characteristics & Timing Specifications

 chapter in Volume 1 of the 

Cyclone II Device Handbook

 for the specific sustaining current for each 

V

CCIO

 voltage level driven through the resistor and overdrive current 

used to identify the next driven input level.

Programmable Pull-Up Resistor

Each Cyclone II device I/O pin provides an optional programmable 
pull-up resistor during user mode. If you enable this feature for an I/O 
pin, the pull-up resistor (typically 25 k

Ω

) holds the output to the V

CCIO

 

level of the output pin’s bank.

1

If the programmable pull-up is enabled, the device cannot use 
the bus-hold feature. The programmable pull-up resistors are 
not supported on the dedicated configuration, JTAG, and 
dedicated clock pins.

2–52

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2007

I/O Structure & Features

Advanced I/O Standard Support

Table 2–17

 shows the I/O standards supported by Cyclone II devices and 

which I/O pins support them.

Table 2–17. Cyclone II Supported I/O Standards & Constraints (Part 1 of 2)

I/O Standard

Type

V

CCIO

 Level

Top & Bottom 

I/O Pins

Side I/O Pins

Input

Output

CLK, 

DQS

User I/O 

Pins

CLK, 

DQS

PLL_OUT

User I/O 

Pins

3.3-V LVTTL and LVCMOS 

(1)

Single ended

3.3 V/

2.5 V

3.3 V

v

v

v

v

v

2.5-V LVTTL and LVCMOS

Single ended

3.3 V/

2.5 V

2.5 V

v

v

v

v

v

1.8-V LVTTL and LVCMOS

Single ended

1.8 V/

1.5 V

1.8 V

v

v

v

v

v

1.5-V LVCMOS

Single ended

1.8 V/

1.5 V

1.5 V

v

v

v

v

v

SSTL-2 class I

Voltage 
referenced

2.5 V

2.5 V

v

v

v

v

v

SSTL-2 class II

Voltage 
referenced

2.5 V

2.5 V

v

v

v

v

v

SSTL-18 class I

Voltage 
referenced

1.8 V

1.8 V

v

v

v

v

v

SSTL-18 class II

Voltage 
referenced

1.8 V

1.8 V

v

v

(2)

(2)

(2)

HSTL-18 class I

Voltage 
referenced

1.8 V

1.8 V

v

v

v

v

v

HSTL-18 class II

Voltage 
referenced

1.8 V

1.8 V

v

v

(2)

(2)

(2)

HSTL-15 class I

Voltage 
referenced

1.5 V

1.5 V

v

v

v

v

v

HSTL-15 class II

Voltage 
referenced 

1.5 V

1.5 V

v

v

(2)

(2)

(2)

PCI and PCI-X 

(1)

 

(3)

Single ended

3.3 V

3.3 V

v

v

v

Differential SSTL-2 class I or 
class II

Pseudo 
differential 

(4)

(5)

2.5 V

v

2.5 V

(5)

v 

(6)

 

v 

(6)

 

Differential SSTL-18 class I 
or class II

Pseudo 
differential 

(4)

(5)

1.8 V

v

 

(7)

1.8 V

(5)

v 

(6)

v 

(6)

 

Altera Corporation 

2–53

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

f

For more information on Cyclone II supported I/O standards, see the 

Selectable I/O Standards in Cyclone II Devices

 chapter in Volume 1 of the 

Cyclone II Device Handbook

.

High-Speed Differential Interfaces

Cyclone II devices can transmit and receive data through LVDS signals at 
a data rate of up to 640 Mbps and 805 Mbps, respectively. For the LVDS 
transmitter and receiver, the Cyclone II device’s input and output pins 
support serialization and deserialization through internal logic. 

Differential HSTL-15 class I 
or class II

Pseudo 
differential 

(4)

(5)

1.5 V

v

 

(7)

1.5 V

(5)

v 

(6)

v 

(6)

 

Differential HSTL-18 class I 
or class II

Pseudo 
differential 

(4)

(5)

1.8 V

v

 

(7)

1.8 V

(5)

v 

(6)

v 

(6)

 

LVDS

Differential

2.5 V

2.5 V

v

v

v

v

v

RSDS and mini-LVDS 

(8)

Differential

(5)

2.5 V

v

v

v

LVPECL 

(9)

Differential

3.3 V/
2.5 V/
1.8 V/
1.5 V

(5)

v

v

Notes to 

Table 2–17

:

(1)

To drive inputs higher than V

C C I O

 but less than 4.0 V, disable the PCI clamping diode and turn on the 

Allow 

LVTTL and LVCMOS input levels to overdrive input buffer

 option in the Quartus II software.

(2)

These pins support SSTL-18 class II and 1.8- and 1.5-V HSTL class II inputs.

(3)

PCI-X does not meet the IV curve requirement at the linear region. PCI-clamp diode is not available on top and 
bottom I/O pins.

(4)

Pseudo-differential HSTL and SSTL outputs use two single-ended outputs with the second output programmed 
as inverted. Pseudo-differential HSTL and SSTL inputs treat differential inputs as two single-ended HSTL and 
SSTL inputs and only decode one of them.

(5)

This I/O standard is not supported on these I/O pins.

(6)

This I/O standard is only supported on the dedicated clock pins.

(7)

PLL_OUT

 does not support differential SSTL-18 class II and differential 1.8 and 1.5-V HSTL class II.

(8)

mini-LVDS and RSDS are only supported on output pins.

(9)

LVPECL is only supported on clock inputs.

Table 2–17. Cyclone II Supported I/O Standards & Constraints (Part 2 of 2)

I/O Standard

Type

V

CCIO

 Level

Top & Bottom 

I/O Pins

Side I/O Pins

Input

Output

CLK, 

DQS

User I/O 

Pins

CLK, 

DQS

PLL_OUT

User I/O 

Pins

2–54

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2007

I/O Structure & Features

The reduced swing differential signaling (RSDS) and mini-LVDS 
standards are derivatives of the LVDS standard. The RSDS and 
mini-LVDS I/O standards are similar in electrical characteristics to 
LVDS, but have a smaller voltage swing and therefore provide increased 
power benefits and reduced electromagnetic interference (EMI). 
Cyclone II devices support the RSDS and mini-LVDS I/O standards at 
data rates up to 311 Mbps at the transmitter.

A subset of pins in each I/O bank (on both rows and columns) support 
the high-speed I/O interface. The dual-purpose LVDS pins require an 
external-resistor network at the transmitter channels in addition to 100-

Ω

 

termination resistors on receiver channels. These pins do not contain 
dedicated serialization or deserialization circuitry. Therefore, internal 
logic performs serialization and deserialization functions.

Cyclone II pin tables list the pins that support the high-speed I/O 
interface. The number of LVDS channels supported in each device family 
member is listed in 

Table 2–18

.

Table 2–18. Cyclone II Device LVDS Channels (Part 1 of 2)

Device

Pin Count

Number of LVDS 

Channels 

(1)

EP2C5

144

31 (35)

208

56 (60)

256

61 (65)

EP2C8

144

29 (33)

208

53 (57)

256

75 (79)

EP2C15

256

52 (60)

484

128 (136)

EP2C20

240

45 (53)

256

52 (60)

484

128 (136)

EP2C35

484

131 (139)

672

201 (209)

EP2C50

484

119 (127)

672

189 (197)

Altera Corporation 

2–55

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

You can use I/O pins and internal logic to implement a high-speed I/O 
receiver and transmitter in Cyclone II devices. Cyclone II devices do not 
contain dedicated serialization or deserialization circuitry. Therefore, 
shift registers, internal PLLs, and IOEs are used to perform 
serial-to-parallel conversions on incoming data and parallel-to-serial 
conversion on outgoing data.

The maximum internal clock frequency for a receiver and for a 
transmitter is 402.5 MHz. The maximum input data rate of 805 Mbps and 
the maximum output data rate of 640 Mbps is only achieved when DDIO 
registers are used. The LVDS standard does not require an input 
reference voltage, but it does require a 100-

Ω

 termination resistor 

between the two signals at the input buffer. An external resistor network 
is required on the transmitter side.

f

For more information on Cyclone II differential I/O interfaces, see the 

High-Speed Differential Interfaces in Cyclone II Devices

 chapter in Volume 1 

of the 

Cyclone II Device Handbook

.

Series On-Chip Termination

On-chip termination helps to prevent reflections and maintain signal 
integrity. This also minimizes the need for external resistors in high pin 
count ball grid array (BGA) packages. Cyclone II devices provide I/O 
driver on-chip impedance matching and on-chip series termination for 
single-ended outputs and bidirectional pins. 

EP2C70

672

160 (168)

896

257 (265)

Note to 

Table 2–18

:

(1)

The first number represents the number of bidirectional I/O pins which can be 
used as inputs or outputs. The number in parenthesis includes dedicated clock 
input pin pairs which can only be used as inputs.

Table 2–18. Cyclone II Device LVDS Channels (Part 2 of 2)

Device

Pin Count

Number of LVDS 

Channels 

(1)

2–56

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2007

I/O Structure & Features

Cyclone II devices support driver impedance matching to the impedance 
of the transmission line, typically 25 or 50

Ω

. When used with the output 

drivers, on-chip termination sets the output driver impedance to 25 or 
50

Ω

. Cyclone II devices also support I/O driver series termination 

(R

S

= 50 

Ω

) for SSTL-2 and SSTL-18. 

Table 2–19

 lists the I/O standards that 

support impedance matching and series termination.

1

The recommended frequency range of operation is pending 
silicon characterization.

On-chip series termination can be supported on any I/O bank. V

CCIO

 and 

V

REF

 must be compatible for all I/O pins in order to enable on-chip series 

termination in a given I/O bank. I/O standards that support different R

S

 

values can reside in the same I/O bank as long as their V

CCIO

 and V

REF

 are 

not conflicting.

1

When using on-chip series termination, programmable drive 
strength is not available. 

Impedance matching is implemented using the capabilities of the output 
driver and is subject to a certain degree of variation, depending on the 
process, voltage and temperature. The actual tolerance is pending silicon 
characterization. 

Table 2–19. I/O Standards Supporting Series Termination

Note (1)

I/O Standards

Target R

S

 (

Ω

)

V

CCIO

 (V)

3.3-V LVTTL and LVCMOS

25 

(2)

3.3

2.5-V LVTTL and LVCMOS

50 

(2)

2.5

1.8-V LVTTL and LVCMOS

50 

(2)

1.8

SSTL-2 class I 

50 

(2)

2.5

SSTL-18 class I 

50 

(2)

1.8

Notes to 

Table 2–19

:

(1)

Supported conditions are V

CCIO

= V

CCIO

 ±50 mV.

(2)

These R

S

 values are nominal values. Actual impedance varies across process, 

voltage, and temperature conditions. 

Altera Corporation 

2–57

February 2007

Cyclone II Device Handbook, Volume 1

Cyclone II Architecture

I/O Banks

The I/O pins on Cyclone II devices are grouped together into I/O banks 
and each bank has a separate power bus. EP2C5 and EP2C8 devices have 
four I/O banks (see 

Figure 2–28

), while EP2C15, EP2C20, EP2C35, 

EP2C50, and EP2C70 devices have eight I/O banks (see 

Figure 2–29

). 

Each device I/O pin is associated with one I/O bank. To accommodate 
voltage-referenced I/O standards, each Cyclone II I/O bank has a VREF 
bus. Each bank in EP2C5, EP2C8, EP2C15, EP2C20, EP2C35, and EP2C50 
devices supports two VREF pins and each bank of EP2C70 supports four 
VREF pins. When using the VREF pins, each VREF pin must be properly 
connected to the appropriate voltage level. In the event these pins are not 
used as VREF pins, they may be used as regular I/O pins.

The top and bottom I/O banks (banks 2 and 4 in EP2C5 and EP2C8 
devices and banks 3, 4, 7, and 8 in EP2C15, EP2C20, EP2C35, EP2C50, and 
EP2C70 devices) support all I/O standards listed in 

Table 2–17

, except the 

PCI/PCI-X I/O standards. The left and right side I/O banks (banks 1 and 
3 in EP2C5 and EP2C8 devices and banks 1, 2, 5, and 6 in EP2C15, EP2C20, 
EP2C35, EP2C50, and EP2C70 devices) support I/O standards listed in 

Table 2–17

, except SSTL-18 class II, HSTL-18 class II, and HSTL-15 class II 

I/O standards. See 

Table 2–17

 for a complete list of supported I/O 

standards.   

The top and bottom I/O banks (banks 2 and 4 in EP2C5 and EP2C8 
devices and banks 3, 4, 7, and 8 in EP2C15, EP2C20, EP2C35, EP2C50, and 
EP2C70 devices) support DDR2 memory up to 167 MHz/333 Mbps and 
QDR memory up to 167 MHz/668 Mbps. The left and right side I/O 
banks (1 and 3 of EP2C5 and EP2C8 devices and 1, 2, 5, and 6 of EP2C15, 
EP2C20, EP2C35, EP2C50, and EP2C70 devices) only support SDR and 
DDR SDRAM interfaces. All the I/O banks of the Cyclone II devices 
support SDR memory up to 167 MHz/167 Mbps and DDR memory up to 
167 MHz/333 Mbps.

1

DDR2 and QDRII interfaces may be implemented in Cyclone II 
side banks if the use of class I I/O standard is acceptable.