cyiv-51001-html.html

March 2016

Altera Corporation

■

Cyclone IV GX devices offer up to eight high-speed transceivers that provide:

■

Data rates up to 3.125 Gbps

■

8B/10B encoder/decoder

■

8-bit or 10-bit physical media attachment (PMA) to physical coding sublayer
(PCS) interface

■

Byte serializer/deserializer (SERDES)

■

Word aligner

■

Rate matching FIFO

■

TX bit slipper for Common Public Radio Interface (CPRI)

■

Electrical idle

■

Dynamic channel reconfiguration allowing you to change data rates and
protocols on-the-fly

■

Static equalization and pre-emphasis for superior signal integrity

■

150 mW per channel power consumption

■

Flexible clocking structure to support multiple protocols in a single transceiver
block

■

Cyclone IV GX devices offer dedicated hard IP for PCI Express (PIPE) (PCIe)
Gen 1:

■

×1, ×2, and ×4 lane configurations

■

End-point and root-port configurations

■

Up to 256-byte payload

■

One virtual channel

■

2 KB retry buffer

■

4 KB receiver (Rx) buffer

■

Cyclone IV GX devices offer a wide range of protocol support:

■

PCIe (PIPE) Gen 1 ×1, ×2, and ×4 (2.5 Gbps)

■

Gigabit Ethernet (1.25 Gbps)

■

CPRI (up to 3.072 Gbps)

■

XAUI (3.125 Gbps)

■

Triple rate serial digital interface (SDI) (up to 2.97 Gbps)

■

Serial RapidIO (3.125 Gbps)

■

Basic mode (up to 3.125 Gbps)

■

V-by-One (up to 3.0 Gbps)

■

DisplayPort (2.7 Gbps)

■

Serial Advanced Technology Attachment (SATA) (up to 3.0 Gbps)

■

OBSAI (up to 3.072 Gbps)

Chapter 1: Cyclone IV FPGA Device Family Overview

1–3

Device Resources

March 2016

Altera Corporation

■

Up to 532 user I/Os

■

LVDS interfaces up to 840 Mbps transmitter (Tx), 875 Mbps Rx

■

Support for DDR2 SDRAM interfaces up to 200 MHz

■

Support for QDRII SRAM and DDR SDRAM up to 167 MHz

■

Up to eight phase-locked loops (PLLs) per device

■

Offered in commercial and industrial temperature grades

Device Resources

Table 1–1

lists Cyclone IV E device resources.

Table 1–1. Resources for the Cyclone IV E Device Family

Resources

EP4CE6

EP4CE115

Logic elements (LEs)

6,272

10,320

15,408

22,320

28,848

39,600

55,856

75,408

114,480

Embedded memory
(Kbits)

270

414

504

594

1,134

2,340

2,745

3,888

Embedded 18 × 18
multipliers

116

154

200

266

General-purpose PLLs

Global Clock Networks

User I/O Banks

Maximum user I/O

179

343

153

532

374

426

528

Note to

Table 1–1

(1) The user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver

pins and dedicated configuration pins are not included in the pin count.

1–4

Chapter 1: Cyclone IV FPGA Device Family Overview

Device Resources

March 2016

Altera Corporation

Clock Networks and PLLs in

Table 1–2

lists Cyclone IV GX device resources.

Table 1–2. Resources for the Cyclone IV GX Device Family

Resources

EP4CGX110

EP4CGX150

Logic elements (LEs)

14,400

21,280

29,440

49,888

73,920

109,424

149,760

Embedded memory (Kbits)

540

756

1,080

2,502

4,158

5,490

6,480

Embedded 18 × 18 multipliers

140

198

280

360

General purpose PLLs

(4)

Multipurpose PLLs

(5)

Global clock networks

High-speed transceivers

(6)

Transceiver maximum data rate
(Gbps)

2.5

3.125

PCIe (PIPE) hard IP blocks

User I/O banks

150

290

310

475

Notes to

Table 1–2

(1) Applicable for the F169 and F324 packages.

(2) Applicable for the F484 package.

(3) Only two multipurpose PLLs for F484 package.

(4) Two of the general purpose PLLs are able to support transceiver clocking. For more information, refer to the

Cyclone IV Devices

chapter.

(5) You can use the multipurpose PLLs for general purpose clocking when they are not used to clock the transceivers. For more information, refer

to the

Clock Networks and PLLs in Cyclone IV Devices

chapter.

(6) If PCIe



1, you can use the remaining transceivers in a quad for other protocols at the same or different data rates.

(7) Including one configuration I/O bank and two dedicated clock input I/O banks for HSSI reference clock input.

(8) Including one configuration I/O bank and four dedicated clock input I/O banks for HSSI reference clock input.

(9) The user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver

pins and dedicated configuration pins are not included in the pin count.

Chapter 1:

Cyclone

FPGA

Dev

ice Family Ov

erview

1–
5

Packa

ge Ma

trix

Mar

ch 20

Alter

Co
rp

ati
o

Cyclone

IV Dev

ice Handbook,

Volume 1

Package Matrix

Table 1–3

lists Cyclone IV E device package offerings.

Table 1–3. Package Offerings for the Cyclone IV E Device Family

I/O Features in Cyclone IV Devices

Package

E144

M164

M256

U256

F256

F324

U484

F484

F780

Size (mm)

22 × 22

8 × 8

9 x 9

14 × 14

17 × 17

19 x 19

19 × 19

23 × 23

29 × 29

Pitch (mm)

0.5

0.8

1.0

0.8

1.0

Device

User I/O

LVDS

)

User I/O

LVDS

)

User I/O

LVDS

)

User I/O

LVDS

)

User I/O

LVDS

)

User I/O

LVDS

)

User I/O

LVDS

)

User I/O

LVDS

)

User I/O

LVDS

)

EP4CE6

—

179

—

EP4CE10

—

179

—

EP4CE15

165

—

343

137

—

EP4CE22

—

153

—

EP4CE30

—

193

—

328

124

532

224

EP4CE40

—

193

328

124

328

124

532

224

EP4CE55

—

324

132

324

132

374

160

EP4CE75

—

292

110

292

110

426

178

EP4CE115

—

280

103

528

230

Notes to

Table 1–3

(1) The E144 package has an exposed pad at the bottom of the package. This exposed pad is a ground pad that must be connected to the ground plane of your PCB. Use this exposed pad for electrical

connectivity and not for thermal purposes.

(2) Use the Pin Migration View window in Pin Planner of the Quartus II software to verify the pin migration compatibility when you perform device migration. For more information, refer to the

I/O

Management

chapter in volume 2 of the

Quartus II Handbook

(3) This includes both dedicated and emulated LVDS pairs. For more information, refer to the

1–
6

Chapter 1:

Cycl

one

IV FPGA D

vice Famil

y Overvi

Pac

kage Matrix

Cyclone

IV De

vic
e H

andbook,

March

016

tera

Cor
por
atio

Volume

Table 1–4

lists Cyclone IV GX device package offerings, including I/O and transceiver counts.

Table 1–4. Package Offerings for the Cyclone IV GX Device Family

Package

F169

F324

F484

F672

F896

Size (mm)

14 × 14

19 × 19

23 × 23

27 × 27

31 × 31

Pitch (mm)

1.0

Device

User I/O

LVDS

XCVRs

User I/O

LVDS

XCVRs

User I/O

LVDS

XCVRs

User I/O

LVDS

XCVRs

User I/O

LVDS

I/O Features in Cyclone IV Devices

XCVRs

EP4CGX15

—

EP4CGX22

150

—

EP4CGX30

150

290

130

—

EP4CGX50

—

290

130

310

140

—

EP4CGX75

—

290

130

310

140

—

EP4CGX110

—

270

120

393

181

475

220

EP4CGX150

—

270

120

393

181

475

220

Note to

Table 1–4

(1) Use the Pin Migration View window in Pin Planner of the Quartus II software to verify the pin migration compatibility when you perform device migration. For more

information, refer to the

I/O Management

chapter in volume 2 of the

Quartus II Handbook

(2) This includes both dedicated and emulated LVDS pairs. For more information, refer to the

chapter.

Chapter 1: Cyclone IV FPGA Device Family Overview

1–7

Cyclone IV Device Family Speed Grades

March 2016

Altera Corporation

Cyclone IV Device Family Speed Grades

Table 1–5

lists the Cyclone IV GX devices speed grades.

Table 1–6

lists the Cyclone IV E devices speed grades.

Table 1–5. Speed Grades for the Cyclone IV GX Device Family

Device

F169

F324

F484

F672

F896

EP4CGX15

C6, C7, C8, I7

—

EP4CGX22

C6, C7, C8, I7

—

EP4CGX30

C6, C7, C8, I7

—

EP4CGX50

—

C6, C7, C8, I7

—

EP4CGX75

—

C6, C7, C8, I7

—

EP4CGX110

—

C7, C8, I7

EP4CGX150

—

C7, C8, I7

Table 1–6. Speed Grades for the Cyclone IV E Device Family

Device

E144

M164

M256

U256

F256

F324

U484

F484

F780

EP4CE6

C8L, C9L, I8L

C6, C7, C8, I7,

—

I7N

C8L, C9L, I8L

C6, C7, C8, I7,

—

EP4CE10

C8L, C9L, I8L

C6, C7, C8, I7,

—

I7N

C8L, C9L, I8L

C6, C7, C8, I7,

—

EP4CE15

C8L, C9L, I8L
C6, C7, C8, I7

I7N

C7N, I7N

I7N

C8L, C9L, I8L

C6, C7, C8, I7,

—

C8L, C9L, I8L

C6, C7, C8, I7,

—

EP4CE22

C8L, C9L, I8L

C6, C7, C8, I7,

—

I7N

C8L, C9L, I8L

C6, C7, C8, I7,

—

EP4CE30

—

A7N

—

C8L, C9L, I8L

C6, C7, C8, I7,

C8L, C9L, I8L

C6, C7, C8, I7

EP4CE40

—

A7N

I7N

C8L, C9L, I8L

C6, C7, C8, I7,

C8L, C9L, I8L

C6, C7, C8, I7

EP4CE55

—

I7N

C8L, C9L, I8L

C6, C7, C8, I7

C8L, C9L, I8L

C6, C7, C8, I7

EP4CE75

—

I7N

C8L, C9L, I8L

C6, C7, C8, I7

C8L, C9L, I8L

C6, C7, C8, I7

EP4CE115

—

C8L, C9L, I8L

C7, C8, I7

C8L, C9L, I8L

C7, C8, I7

Notes to

Table 1–6

(1) C8L, C9L, and I8L speed grades are applicable for the 1.0-V core voltage.

(2) C6, C7, C8, I7, and A7 speed grades are applicable for the 1.2-V core voltage.

1–8

Chapter 1: Cyclone IV FPGA Device Family Overview

Cyclone IV Device Family Architecture

March 2016

Altera Corporation

“External Memory Interfaces”

Cyclone IV Device Family Architecture

This section describes Cyclone IV device architecture and contains the following
topics:

■

“FPGA Core Fabric”

■

“I/O Features”

■

“Clock Management”

■

■

“Configuration”

■

“High-Speed Transceivers (Cyclone IV GX Devices Only)”

■

“Hard IP for PCI Express (Cyclone IV GX Devices Only)”

FPGA Core Fabric

Cyclone IV devices leverage the same core fabric as the very successful Cyclone series
devices. The fabric consists of LEs, made of 4-input look up tables (LUTs), memory
blocks, and multipliers.

Each Cyclone IV device M9K memory block provides 9 Kbits of embedded SRAM
memory. You can configure the M9K blocks as single port, simple dual port, or true
dual port RAM, as well as FIFO buffers or ROM. They can also be configured to
implement any of the data widths in

Table 1–7

The multiplier architecture in Cyclone IV devices is the same as in the existing
Cyclone series devices. The embedded multiplier blocks can implement an 18 × 18 or
two 9 × 9 multipliers in a single block. Altera offers a complete suite of DSP IP
including finite impulse response (FIR), fast Fourier transform (FFT), and numerically
controlled oscillator (NCO) functions for use with the multiplier blocks. The
Quartus

II design software’s DSP Builder tool integrates MathWorks Simulink and

MATLAB design environments for a streamlined DSP design flow.

For more information, refer to the

Logic Elements and Logic Array Blocks in Cyclone IV

Devices

Memory Blocks in Cyclone IV Devices

, and

Embedded Multipliers in Cyclone IV

Devices

chapters.

Table 1–7. M9K Block Data Widths for Cyclone IV Device Family

Mode

Data Width Configurations

Single port or simple dual port

×1, ×2, ×4, ×8/9, ×16/18, and ×32/36

True dual port

×1, ×2, ×4, ×8/9, and ×16/18

Chapter 1: Cyclone IV FPGA Device Family Overview

1–9

Cyclone IV Device Family Architecture

March 2016

Altera Corporation

I/O Features in Cyclone IV Devices

I/O Features

Cyclone IV device I/O supports programmable bus hold, programmable pull-up
resistors, programmable delay, programmable drive strength, programmable
slew-rate control to optimize signal integrity, and hot socketing. Cyclone IV devices
support calibrated on-chip series termination (Rs OCT) or driver impedance matching
(Rs) for single-ended I/O standards. In Cyclone IV GX devices, the high-speed
transceiver I/Os are located on the left side of the device. The top, bottom, and right
sides can implement general-purpose user I/Os.

Table 1–8

lists the I/O standards that Cyclone IV devices support.

The LVDS SERDES is implemented in the core of the device using logic elements.

For more information, refer to the

Clock Networks and PLLs in Cyclone IV Devices

Clock Management

Cyclone IV devices include up to 30 global clock (GCLK) networks and up to eight
PLLs with five outputs per PLL to provide robust clock management and synthesis.
You can dynamically reconfigure Cyclone IV device PLLs in user mode to change the
clock frequency or phase.

Cyclone IV GX devices support two types of PLLs: multipurpose PLLs and general-
purpose PLLs:

■

Use multipurpose PLLs for clocking the transceiver blocks. You can also use them
for general-purpose clocking when they are not used for transceiver clocking.

■

Use general purpose PLLs for general-purpose applications in the fabric and
periphery, such as external memory interfaces. Some of the general purpose PLLs
can support transceiver clocking.

For more information, refer to the

chapter.

External Memory Interfaces

Cyclone IV devices support SDR, DDR, DDR2 SDRAM, and QDRII SRAM interfaces
on the top, bottom, and right sides of the device. Cyclone IV E devices also support
these interfaces on the left side of the device. Interfaces may span two or more sides of
the device to allow more flexible board design. The Altera

DDR SDRAM memory

interface solution consists of a PHY interface and a memory controller. Altera supplies
the PHY IP and you can use it in conjunction with your own custom memory
controller or an Altera-provided memory controller. Cyclone IV devices support the
use of error correction coding (ECC) bits on DDR and DDR2 SDRAM interfaces.

Table 1–8. I/O Standards Support for the Cyclone IV Device Family

Type

I/O Standard

Single-Ended I/O

LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X

Differential I/O

SSTL, HSTL, LVPECL, BLVDS, LVDS, mini-LVDS, RSDS, and PPDS

1–10

Chapter 1: Cyclone IV FPGA Device Family Overview

Cyclone IV Device Family Architecture

March 2016

Altera Corporation

External Memory Interfaces in Cyclone IV Devices

For more information, refer to the

chapter.

Configuration

Cyclone IV devices use SRAM cells to store configuration data. Configuration data is
downloaded to the Cyclone IV device each time the device powers up. Low-cost
configuration options include the Altera EPCS family serial flash devices and
commodity parallel flash configuration options. These options provide the flexibility
for general-purpose applications and the ability to meet specific configuration and
wake-up time requirements of the applications.

Table 1–9

lists which configuration schemes are supported by Cyclone IV devices.

IEEE 1149.6 (AC JTAG) is supported on all transceiver I/O pins. All other pins
support IEEE 1149.1 (JTAG) for boundary scan testing.

For more information, refer to the

JTAG Boundary-Scan Testing for Cyclone IV Devices

chapter.

For Cyclone IV GX devices to meet the PCIe 100 ms wake-up time requirement, you
must use passive serial (PS) configuration mode for the EP4CGX15/22/30 devices
and use fast passive parallel (FPP) configuration mode for the EP4CGX30F484 and
EP4CGX50/75/110/150 devices.

For more information, refer to the

Configuration and Remote System Upgrades in

Cyclone IV Devices

The cyclical redundancy check (CRC) error detection feature during user mode is
supported in all Cyclone IV GX devices. For Cyclone IV E devices, this feature is only
supported for the devices with the core voltage of 1.2 V.

For more information about CRC error detection, refer to the

SEU Mitigation in

Cyclone IV Devices

High-Speed Transceivers (Cyclone IV GX Devices Only)

Cyclone IV GX devices contain up to eight full duplex high-speed transceivers that
can operate independently. These blocks support multiple industry-standard
communication protocols, as well as Basic mode, which you can use to implement
your own proprietary protocols. Each transceiver channel has its own pre-emphasis
and equalization circuitry, which you can set at compile time to optimize signal
integrity and reduce bit error rates. Transceiver blocks also support dynamic
reconfiguration, allowing you to change data rates and protocols on-the-fly.

Table 1–9. Configuration Schemes for Cyclone IV Device Family

Devices

Supported Configuration Scheme

Cyclone IV GX

AS, PS, JTAG, and FPP

Cyclone IV E

AS, AP, PS, FPP, and JTAG

Note to

Table 1–9

(1) The FPP configuration scheme is only supported by the EP4CGX30F484 and EP4CGX50/75/110/150 devices.

Chapter 1: Cyclone IV FPGA Device Family Overview

1–11

Cyclone IV Device Family Architecture

March 2016

Altera Corporation

Cyclone IV Transceivers Architecture

Figure 1–1

shows the structure of the Cyclone IV GX transceiver.

For more information, refer to the

PCI Express Compiler User Guide

Hard IP for PCI Express (Cyclone IV GX Devices Only)

Cyclone IV GX devices incorporate a single hard IP block for ×1, ×2, or ×4 PCIe (PIPE)
in each device. This hard IP block is a complete PCIe (PIPE) protocol solution that
implements the PHY-MAC layer, Data Link Layer, and Transaction Layer
functionality. The hard IP for the PCIe (PIPE) block supports root-port and end-point
configurations. This pre-verified hard IP block reduces risk, design time, timing
closure, and verification. You can configure the block with the Quartus II software’s
PCI Express Compiler, which guides you through the process step by step.

For more information, refer to the

Figure 1–1. Transceiver Channel for the Cyclone IV GX Device

RX Phase

Compensation

FIFO

TX Phase

Compensation

FIFO

Byte Order

ing

Byte Deser

ializ

Byte Serializer

8B10B Decoder

8B10B Encoder

Rate Match FIFO

Receive

Channel PCS

Receive

Channel

PMA

ord Aligner

rx_datain

Deser

ializ

CDR

ansmi

Channel PCS

ansceive

Channel

PMA

tx_dataout

Ser

ializ

PCI Exp

ess ha

d IP

FPGA

Fab

PIPE In

face

1–12

Chapter 1: Cyclone IV FPGA Device Family Overview

Reference and Ordering Information

March 2016

Altera Corporation

Reference and Ordering Information

Figure 1–2

shows the ordering codes for Cyclone IV GX devices.

Figure 1–3

shows the ordering codes for Cyclone IV E devices.

Figure 1–2. Packaging Ordering Information for the Cyclone IV GX Device

Family Signature

Transceiver Count

Package Type

Package Code

Operating Temperature

Speed Grade

Optional Suffix

Indicates specific device
options or shipment method

GX : 3-Gbps transceivers

EP4C : Cyclone IV

15  :  14,400 logic elements
22  :  21,280 logic elements
30  :  29,440 logic elements
50  :  49,888 logic elements
75  :  73,920 logic elements
110 :  109,424 logic elements
150 :  149,760 logic elements

B : 2
C : 4
D : 8

F : FineLine BGA (FBGA)
N : Quad Flat Pack No Lead (QFN)

FBGA Package Type

14 :  169 pins
19 :  324 pins
23 :  484 pins
27 :  672 pins
31  :   896 pins

C : Commercial temperature (T

= 0° C to 85° C)

I : Industrial temperature (T

= -40° C to 100° C)

6 (fastest)
7
8

N : Lead-free

packaging

ES : Engineering sample

EP4C

Member Code

Family Variant

Figure 1–3. Packaging Ordering Information for the Cyclone IV E Device

Family Signature

Package Type

Package Code

Operating Temperature

Speed Grade

Optional Suffix

Indicates specific device
options or shipment method

E : Enhanced

logic/memory

EP4C : Cyclone IV

6  :  6,272 logic elements
10  :  10,320 logic elements
15  :  15,408 logic elements
22  :  22,320 logic elements
30  :  28,848 logic elements
40  :  39,600 logic elements
55  :  55,856 logic elements
75  :  75,408 logic elements
115 :  114,480 logic elements

F  :  FineLine BGA (FBGA)
E  :  Enhanced Thin Quad Flat Pack (EQFP)
U  :  Ultra FineLine BGA (UBGA)
M  :  Micro FineLine BGA (MBGA)

FBGA Package Type

17 :  256 pins
19  :   324 pins
23 :  484 pins
29 :  780 pins

EQFP Package Type

22 : 144 pins

UBGA Package Type

14 : 256 pins
19 : 484 pins

MBGA Package Type

8 : 164

pins

9 : 256

pins

C : Commercial temperature (T

= 0° C to 85° C)

I : Industrial temperature (T

= -40° C to 100° C)

Extended industrial temperature (T

= -40° C to 125° C)

A : Automotive temperature (T

= -40° C to 125° C)

6 (fastest)
7
8
9

N : Lead-free

packaging

ES : Engineering sample
L : Low-voltage

device

EP4C

Member Code

Family Variant

Chapter 1: Cyclone IV FPGA Device Family Overview

1–13

Document Revision History

March 2016

Altera Corporation