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www.adivatech.com    

(888) 30-ADIVA (23482)

O

30

Voltage Controlled Clock OSC.

ADVCXO Series

Surface Mount & Thru Hole

-

A

6

A

A

B    -

M

PACKAGE TYPE
FREQUENCY STABILITY
DUTY CYCLE
DEVIATION

FREQUENCY
OUTPUT
LINEARITY

EXAMPLE

45/55%

5

40/60%

6

±100 ppm min

A

±75ppm min

B

±50 ppm min

C

±200 ppm min

D

20%

A

15%

B

10%

C

None

Blank

TTL

A

CMOS

B

CMOS Compatible

C

Package Type

Duty Cycle

Deviation

Linearity

Output

±100 ppm

A

±50 ppm

B

±30 ppm

C

±25 ppm

D

Custom

E

Frequency Stability

ADVCXO G4 SMD

pg31

ADVCXO G6 SMD

pg31

ADVCXO I

SMD

pg32

ADVCXO H

Thru Hole pg33

p31_ADVCXOG4-html.html
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O

VC

XO

/V

C

O

31

ADVCXOG4 (unit: mm)

ADVCXOG6 (unit: mm)

STANDARD SPECIFICATIONS

Package Type

ADVCOXG4 

ADVCOXG6

Standard Frequency

27.000, 35.328 MHz

27.000, 35.328 MHz

Frequency Range

8.000 ~ 36.000MHz

8.000 ~ 36.000 MHz

Frequency Stability

±100 ppm (0ºC ~ 70ºC

±50 ppm (0ºC ~ 70ºC)

vs. Temperature Range

±25 ppm (0ºC ~ 70ºC)

±100 ppm (-40ºC ~ 85ºC)

±50 ppm (0-40ºC ~ 85ºC)

Custom

Output Load

CMOS or TTL

CMOS or TTL

Frequency Control Range

±100 ppm or ±75 ppm or ±50 ppm ±100 ppm or ±75 ppm or ±50 ppm

Supply Voltage

Vdd = 5V

Vdd = 5V

Frequency Control Voltage

Vc = 2.5 ±2 Vdc

Vc = 2.5 ±2 Vdc

Output Symmetry (Tw/T)

40% ~ 60% or 45% ~ 55%

40% ~ 60% or 45% ~ 55%

Output Voltage  Level

Output Logic High

90% Vdd min.

90% Vdd min.

Output Logic Low

10% Vdd max.

10% Vdd max.

Aging

±5 ppm/year

±5 ppm/year

OUTPUT WAVEFORM FOR CMOS

TAPE SPECIFICATIONS

TEST CIRCUIT

SOLDERING REFLOW PROFILE

SEE PAGE 30 FOR PART NUMBERING GUIDE

Voltage Controlled Clock OSC.

ADVCXOG Series (G4, G6)

Surface Mount

XTAL

OSC.

VCXO

VCO

TCXO

VCTCXO

FLTR

RES

IND

ADVCXOG4

ADVCXOG6

FEATURES

• Seam welding
• Superior quality

• Low power consumption
• Custom requirement available
• Application: Set top box, ADSL modem.

REEL PACKING (unit: mm)

FREQUENCY/MODULATION

VOLTAGE CHARACTERISTICS