Description
DATA DELAY 3D3608R-200 IC 8-bit & 12-bit Programmable Pulse Generators
Features, Applications
& 12-BIT PROGRAMMABLE PULSE GENERATORS (SERIES & 3D3612: PARALLEL INTERFACE)
FEATURES
· All-silicon, low-power CMOS technology 3.3V operation Vapor phase, IR and wave solderable Programmable via latched parallel interface Increment range: 0.25ns through 800us Pulse width tolerance: 1% (See Table 1) Supply current: 8mA typical Temperature stability: ±1.5% max to 85C) Vdd stability: ±1.0% max to 3.6V)
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The & 3D3612 devices are versatile & 12-bit programmable monolithic pulse generators. A rising-edge on the trigger input (TRIG) initiates the pulse, which is presented on the output pins (OUT,OUTB). The pulse width, programmed via the parallel interface, can be varied over 4095 (3D3612) equal steps according to the formula: tPW = tinh + addr * tinc where addr is the programmed address, tinc is the pulse width increment (equal to the device dash number), and tinh is the inherent (address zero) pulse width. The device also offers a reset input (RES), which can be used to terminate the pulse before the programmed time has expired.
TRIG RES OUT OUTB Trigger Input Reset Input Pulse Output Complementary Pulse Output AE Address Enable Input P0-P11 Address Inputs VDD +3.3 Volts GND Ground NC Do not connect externally
The all-CMOS & 3D3612 integrated circuits have been designed as reliable, economic alternatives to hybrid TTL pulse generators. The 3D3608 is offered in a standard 16-pin SOIC, and the 3D3612 is offered in a standard 20-pin SOL.
PART 3D3608R-20K 3D3608R-50K PART 3D3612W-20K 3D3612W-50K Pulse Width Increment ± 25us Maximum P.W. ± 128us Maximum P.W. 2.1 ms PART 3D3608R-500K 3D3608R-750K Pulse Width Increment ± 375us Maximum P.W. ± 1.9ms
NOTE: Any increment between 0.25ns and 800us (50us for the 12-bit generator) not shown is also available as a standard device.
Figure 1 illustrates the main functional blocks of the & 3D3612. Since these devices are CMOS designs, all unused input pins must be returned to well-defined logic levels, VDD or Ground. The pulse generator architecture is comprised of a number of delay cells (for fine control) and an oscillator & counter (for coarse control). Each device is individually trimmed for maximum accuracy and linearity throughout the address range. The change in pulse width from one address setting to the next is called the increment, or LSB. It is nominally equal to the device dash number. The minimum pulse width, achieved by setting the address to zero, is called the inherent pulse width. For best performance, it is essential that the power supply pin be adequately bypassed and filtered. In addition, the power bus should of as low an impedance construction as possible. Power planes are preferred. Also, signal traces should be kept as short as possible. The absolute error is defined as follows: eabs = tPW (tinh + addr * tinc) where tinh is the nominal inherent delay. The absolute error is limited to 1.5 LSB or 3.0 ns, whichever is greater, at every address. The inherent pulse width error is the deviation of the inherent width from its nominal value. It is limited 2.0 ns from the nominal inherent pulse width of 10 ns.
The characteristics of CMOS integrated circuits are strongly dependent on power supply and temperature. The & 3D3612 utilize novel compensation circuitry to minimize the performance variations induced by fluctuations in power supply and/or temperature. With regard to stability, the output pulse width of the at a given address, addr, can be split into two components: the inherent pulse width (tinh) and the relative pulse width (tPW – tinh). These components exhibit very different stability coefficients, both of which must be considered in very critical applications. The thermal coefficient of the relative pulse width is limited to ±250 PPM/C (except for the -0.25), which is equivalent to a variation, over the to 85C operating range, ±1.5% (±9% for the dash 0.25) from the room-temperature pulse width. This holds for all dash numbers. The thermal coefficient of the inherent pulse width is nominally +20ps/C for dash numbers less than 5, and +30ps/C for all other dash numbers. The power supply sensitivity of the relative pulse width ±1.0% (±3.0% for the dash 0.25) over the to 3.6V operating range, with respect to the pulse width at the nominal 3.3V power supply. This holds for all dash numbers. The sensitivity of the inherent pulse width is nominally -5ps/mV for all dash numbers. It should also be noted that the DNL is also adversely affected by thermal and supply variations, particularly at the MSL/LSB crossovers (ie, to 128, etc).
There are a number of ways of characterizing the pulse width accuracy of a programmable pulse generator. The first is the differential nonlinearity (DNL), also referred to as the increment error. It is defined as the deviation of the increment at a given address from its nominal value. For most dash numbers, the DNL is within 0.5 LSB at every address (see Table 1: Pulse Width Step). The integrated nonlinearity (INL) is determined by first constructing the least-squares best fit straight line through the pulse-width-versusaddress data. The INL is then the deviation of a given width from this line. For all dash numbers, the INL is within 1.0 LSB at every address. The relative error is defined as follows: erel = (tPW tinh) addr * tinc where addr is the address, tPW is the measured width at this address, tinh is the measured inherent width, and tinc is the nominal increment. It is very similar to the INL, but simpler to calculate. For most dash numbers, the relative error is less than 1.0 LSB at every address (see Table 1).
Figure 2 shows the timing diagram of the device when the reset input (RES) is not used. In this case, the pulse is triggered by the rising edge of the TRIG signal and ends at a time determined by the address loaded into the device. While the pulse is active, any additional triggers occurring are ignored. Once the pulse has ended, and after a short recovery time, the next trigger is recognized. Figure 3 shows the timing for the case where a reset is issued before the pulse has ended. Again, there is a short recovery time required before the next trigger can occur.
The 3D3608/3D3612 can operate in one of two addressing modes. In the transparent mode (AE held high), the parallel address inputs must persist for the duration of the output pulse, in accordance with Figure 4. In the latched mode, the address data is stored internally, which allows the parallel inputs to be connected to a multi-purpose data bus. Timing for this mode is also shown in Figure 4.
Manufacturer:Electronic Components
Datasheet:3d3608.pdf
