Description
ALTERA – ALTERA EP1K30QC208-1 50/T RY FPGA ACEX 1K Family 30K Gates 1728 Cells 250MHz 0.22um Technology 2.5V 208-Pin PQFP
Package Description PLASTIC, QFP-208
REACH Compliant Yes
Status Active
Programmable Logic Type LOADABLE PLD
Clock Frequency-Max 90 MHz
JESD-30 Code S-PQFP-G208
JESD-609 Code e0
Moisture Sensitivity Level 3
Number of I/O Lines 147
Number of Inputs 147
Number of Logic Cells 1728
Number of Outputs 147
Number of Terminals 208
Operating Temperature-Min 0.0 Cel
Operating Temperature-Max 70 Cel
Organization 147 I/O
Output Function MIXED
Package Body Material PLASTIC/EPOXY
Package Code FQFP
Package Equivalence Code QFP208,1.2SQ,20
Package Shape SQUARE
Package Style FLATPACK, FINE PITCH
Peak Reflow Temperature (Cel) 220
Power Supplies 2.5,2.5/3.3
Propagation Delay 0.4000 ns
Qualification Status Not Qualified
Seated Height-Max 4.1 mm
Sub Category Field Programmable Gate Arrays
Supply Voltage-Nom 2.5 V
Supply Voltage-Min 2.38 V
Supply Voltage-Max 2.62 V
Surface Mount YES
Technology CMOS
Temperature Grade COMMERCIAL
Terminal Finish Tin/Lead (Sn/Pb)
Terminal Form GULL WING
Terminal Pitch 0.5000 mm
Terminal Position QUAD
Time@Peak Reflow Temperature-Max (s) 30
Length 28 mm
Width 28 mm
Manufacturer:Altera
Datasheet:ACEX-1K.pdf
