Description
AMD MACH211-15JC Complex Programmable Logic Device 1/8 CONTROLLER IC COMPLEX-EEPLD64-CELL15NS PROP DELAYLDCC44PIN
High-performance electrically-erasable CMOS PLD families to 128 macrocells to 100 pins in cost-effective PLCC, PQFP and TQFP packages SpeedLockingTM guaranteed fixed timing to 16 product terms Commercial 5/5.5/6/7.5/10/12/15-ns tPD and Industrial 7.5/10/12/14/18-ns tPD Configurable macrocells Programmable polarity Registered or combinatorial outputs Internal and I/O feedback paths D-type or T-type flip-flops Output Enables Choice of clocks for each flip-flop Input registers for MACH 2 family JTAG (IEEE 1149.1)-compatible, 5-V in-system programming available Peripheral component interconnect (PCI) compliant 5/5.5/6/7.5/10/12 ns Safe for mixed supply voltage system designs Bus-FriendlyTM inputs and I/Os reduce risk of unwanted oscillatory outputs Programmable power-down mode results in power savings to 75% Supported by Vantis DesignDirectTM software for rapid logic development Supports HDL design methodologies with results optimized for Vantis Flexibility to adapt to user requirements Software partnerships that ensure customer success Lattice/Vantis and third-party hardware programming support Lattice/VantisPROTM (formerly known as MACHPRO software for in-system programmability support on PCs and Automated Test Equipment Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General
SPECIFICATIONS
| Mfr Package Description | PLASTIC, LCC-44 |
| Status | Discontinued |
| Programmable Logic Type | EE PLD |
| Clock Frequency-Max | 50.0 MHz |
| In-System Programmable | NO |
| JESD-30 Code | S-PQCC-J44 |
| JESD-609 Code | e0 |
| JTAG BST | NO |
| Number of Dedicated Inputs | 2.0 |
| Number of I/O Lines | 32.0 |
Manufacturer:AMD
Datasheet:AMDIS175-1.pdf
