Description
Cypress Semiconductor CY7C344-20JI IC SIMPLE EPLD, FPGAs/PLDs => PLDs (Programmable Logic Devices) => EPLD (Erasable PLD)
Package Description PLASTIC, LCC-28
Status Discontinued
Programmable Logic Type OT PLD
Architecture PAL-TYPE
Clock Frequency-Max 41.6 MHz
JESD-30 Code S-PQCC-J28
JESD-609 Code e0
Number of Dedicated Inputs 7
Number of I/O Lines 16
Number of Inputs 24
Number of Outputs 16
Number of Product Terms 320
Number of Terminals 28
Operating Temperature-Min -40 Cel
Operating Temperature-Max 85 Cel
Organization 7 DEDICATED INPUTS, 16 I/O
Output Function MACROCELL
Package Body Material PLASTIC/EPOXY
Package Code QCCJ
Package Equivalence Code LDCC28,.5SQ
Package Shape SQUARE
Package Style CHIP CARRIER
Peak Reflow Temperature (Cel) 225
Power Supplies 5
Propagation Delay 20 ns
Qualification Status Not Qualified
Seated Height-Max 4.57 mm
Sub Category Programmable Logic Devices
Supply Voltage-Nom 5 V
Supply Voltage-Min 4.5 V
Supply Voltage-Max 5.5 V
Surface Mount YES
Technology CMOS
Temperature Grade INDUSTRIAL
Terminal Finish Tin/Lead (Sn/Pb)
Terminal Form J BEND
Terminal Pitch 1.27 mm
Terminal Position QUAD
Time@Peak Reflow Temperature-Max (s) 30
Length 11.53 mm
Width 11.53 mm
Additional Feature MACROCELLS INTERCONNECTED BY PIA; 32 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Features
· High-performance, high-density replacement for TTL, 74HC, and custom logic· 32 macrocells, 64 expander product terms in one LAB· 8 dedicated inputs, 16 I/O pins· 0.8-micron double-metal CMOS EPROM technology· 28-pin, 300-mil DIP, cerDIP or 28-pin HLCC, PLCC package tional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an input, two expanders are used to create an input path. Even if all of the I/O pins are driven by macrocell registers, there are still 16 “buried” registers available. All inputs, macrocells, and I/O pins are interconnected within the LAB. The speed and density of the CY7C344 makes it a natural for all types of applications. With just this one device, the designer can implement complex state machines, registered logic, and combinatorial “glue” logic, without using multiple chips. This architectural flexibility allows the CY7C344 to replace multichip TTL solutions, whether they are synchronous, asynchronous, combinatorial, or all three.
Manufacturer:Cypress
Datasheet:CY7C344-20JI.pdf
