Description
DALLAS – AMDM-100 AMDM Series FAST / TTL Buffered 5-Tap Delay Modules
Low Profile 8-Pin Package Two Surface Mount Versions FAST/TTL Logic Buffered 5 Equal Delay Taps Operating Temperature Range +70OC 14-Pin Versions: FAIDM Series SIP Versions: FSIDM Series Low Voltage CMOS Versions refer to LVMDM / LVIDM Series AMDM 8-Pin Schematic
These part numbers do not have 5 equal taps. Tap-to-Tap Delays reference Tap 1.
VCC Supply Voltage………………………………………… 5.00VDC Input Pulse Voltage…………………………………………… 3.20V Input Pulse Rise Time………………………………… 3.0 ns max. Input Pulse Width / Period……………………… ns 1. Measurements made 25OC 2. Delay Times measured at 1.50V level of leading edge. 3. Rise Times measured from 4. 10pf probe and fixture load on output under test.
VCC Supply Voltage…………………………….. ± 0.25 VDC ICC Supply Current……………………………… 48 mA Maximum Logic “1” Input: VIH………………….. 2.00 V min., 5.50 V max. IIH…………………………. 20 µA max. @ 2.70V Logic “0” Input: VIL…………………………………… 0.80 V max. IIL…………………………………….. -0.6 mA VOH Logic “1” Voltage Out……………………………. 2.40 V min. VOL Logic “0” Voltage Out…………………………. 0.50 V max. PWI Input Pulse Width……………………….. 40% of Delay min. Operating Temperature Range………………………. to 70OC Storage Temperature Range…………………. to +150OC
Buffered 5 Tap Delay Molded Package Series: 8-pin DIP: AMDM Total Delay in nanoseconds (ns) Lead Style: Blank = Thru-hole G = “Gull Wing” SMD J = “J” Bend SMD Examples: 25ns (5ns per tap) 74F/TTL, 8-Pin G-SMD 100ns (20ns per tap) 74F/TTL, 8-Pin DIP
