Description
HEF4027BP652 ic Flip Flo p JK-Master-Slave Type Po s-Edge 2-Element 16-Pin P DIP Bulk RoHS Manufacturer: NXP
Product Training Modules Logic Packages
Category Integrated Circuits (ICs)
Family Logic – Flip Flops
Series 4000B
Packaging ? Tube?
Function Set(Preset) and Reset
Type JK Type
Output Type Differential
Number of Elements 2
Number of Bits per Element 1
Frequency – Clock 30MHz
Max Propagation Delay @ V, Max CL 60ns @ 15V, 50pF
Trigger Type Positive Edge
Current – Output High, Low 3mA, 3mA
Voltage – Supply 3 V ~ 15 V
Current – Quiescent 16µA
Input Capacitance 7.5pF
Operating Temperature -40°C ~ 85°C (TA)
Mounting Type Through Hole
Package / Case 16-DIP (0.300″, 7.62mm)
The HEF4027B is a edge-triggered dual JK f lip-flop which features independent set-direct (SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q ). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct (CD) and se t-direct (SD) inputs are independent and override the J, K, and CP inputs. The outputs are buffered for best system performance. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times. It operates over a recommended V DD power supply range of 3 V to 15 V referenced to V SS (usually ground). Unused inputs must be connected to V DD , V SS , or another input.
Manufacturer:NXP
Datasheet:NXP/HEF4027B.pdf
