Philips 74HC93D IC 4-bit Binary Ripple Counter 100MHZ, SOIC-14

The 74HC/HCT93 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT93 are 4-bit binary ripple counters. The devices consist of four master-slave flip-flops internally connected to provide a divide-by-two section and a divide-by-eight section. Each section has a separate clock input (CP ₀ and CP ₁) to initiate state changes of the counter on the HIGH-to-LOW clock transition. State changes of the Q_n outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes.

A gated AND asynchronous master reset (MR₁ and MR₂) is provided which overrides both clocks and resets (clears) all flip-flops.

Since the output from the divide-by-two section is not internally connected to the succeeding stages, the device may be operated in various counting modes. In a 4-bit ripple counter the output Q₀ must be connected externally to input CP ₁. The input count pulses are applied to clock input CP ₀. Simultaneous frequency divisions of 2, 4, 8 and 16 are performed at the Q₀, Q₁, Q₂ and Q₃ outputs as shown in the function table. As a 3-bit ripple counter the input count pulses are applied to input CP ₁.

Simultaneous frequency divisions of 2, 4 and 8 are available at the Q₁, Q₂ and Q₃ outputs. Independent use of the first flip-flop is available if the reset function coincides with reset of the 3-bit ripple-through counter.