Description
PHILIPS 74HCT138D CMOS 3-TO-8 LINE INVERTING DECODER/ DEMULTIPLEXER SOIC-16, NONE-RoHS
The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y 0 to Y 7). The device features three enable inputs (E 1, E 2 and E3). Every output will be HIGH unless E 1 and E 2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four ‘138’ ICs and one invert er. The ‘138’ can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs in clude clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V CC .
The 74HCT138D is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The decoder accepts three binary weighted address inputs (A0, A1 and A3) and when enabled, provides 8 mutually exclusive active LOW outputs (Y0 to Y7).
The 74HCT138 features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the 74HC138; 74HCT138 to a 1-of-32 (5 lines to 32 lines) decoder with just four 74HC138; 74HCT138 ICs and one inverter.
Features:
Demultiplexing capability
Multiple input enable for easy expansion
Complies with JEDEC standard no. 7A
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
ESD protection:
HBM EIA/JESD22-A114-C exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
Specified from -40 Cel to +85 Cel and from -40 Cel to +125 Cel
Manufacturer:Philips
Datasheet:Others/74HC_HCT138.pdf
