Description
PHILIPS TDA10021HT IC DVB-C CHANNEL RECEIVER Power Management IC Development Tools TQFP64. The TDA10021HT is a single-chip DVB-C channelreceiver for 4, 16, 32, 64, 128 and 256 QAM modulatedsignals. The device interfaces directly to the IF signal,which is sampled by a 10-bit ADC.The TDA10021HT performs the clock and the carrierrecovery functions. The digital loop filters for both clockand carrier recovery are programmable in order tooptimize their characteristics according to the currentapplication.After baseband conversion, equalization filters are usedfor echo cancellation in cable applications. These filtersare configured as either a T-spaced transversal equalizeror a Decision Feedback Equalizer (DFE), so that thesystem performance can be optimized according to thenetwork characteristics. A proprietary equalizationalgorithm, independent of carrier offset, is achieved inorder to assist carrier recovery. A decision directedalgorithm then takes place, to achieve final equalizationconvergence.The TDA10021HT implements a FORNEY convolutionalde-interleaver of depth 12 blocks and a Reed-Solomondecoder which corrects up to 8 erroneous bytes. Thede-interleaver and the RS decoder are automaticallysynchronized by the frame synchronization algorithmwhich uses the MPEG-2 sync byte. Finally descramblingaccording to DVB-C standard, is achieved at the ReedSolomon output. This device is controlled via an I2C-bus.Designed in 0.2μm CMOS technology and housed in a64 pin TQFP package, the TDA10021HT operates overthe commercial temperature range.
GENERAL DESCRIPTION
The TDA10021HT is a single-chip DVB-C channel receiver for 4, 16, 32, 64, 128 and 256 QAM modulated signals. The device interfaces directly to the IF signal, which is sampled by a 10-bit ADC.
FEATURES
• 4, 16, 32, 64, 128 and 256 Quadrature Amplitude Modulation (QAM) demodulator (DVB-C compatible: ETS 300-429/ITU-T J83 annex A/C)
• High performance for 256 QAM, especially for direct IF applications
• On-chip 10-bit Analog-to-Digital Converter (ADC)
• On-chip Phase-Locked Loop (PLL) for crystal frequency multiplication (typically 4 MHz crystal)
• Digital downconversion
• Programmable half Nyquist filter (roll off = 0.15 or 0.13)
• Two Pulse Width Modulated (PWM) AGC outputs with programmable take over point (for tuner and downconverter control)
• Clock timing recovery, with programmable 2nd-order loop filter
• Variable symbol rate capability from SACLK/64 to SACLK/4 (SACLK = 36 MHz maximum)
• Programmable anti-aliasing filters
• Full digital carrier recovery loop
• Carrier acquisition range up to 18% of symbol rate
• Integrated adaptive equalizer (linear transversal equalizer or decision feedback equalizer)
• On-chip Forward Error Correction (FEC) decoder (de-interleaver and RS decoder) and fully DVB-C compliant
• DVB compatible differential decoding and mapping
• Parallel and serial transport stream interface simultaneously
• I2C-bus interface, for easy control
• CMOS 0.2 µm technology.
APPLICATIONS
• Cable set-top boxes
• Cable modems
• MMDS (ETS 300-749) set-top boxes.
Manufacturer:Philips
Datasheet:TDA10021HT_PhilipsSemiconductors.pdf
