Description
Signetics SIG 74F85N Magnitude Comparator 4 Bit PDIP-16 Through Hole
The a 4-bit magnitude comparator that can be expanded to almost any length. It compares two 4-bit binary, BCD, or other monotonic codes and presents the three possible magnitude results at the outputs. The 4-bit inputs are weighted (A0A3) and (B0B3) where A3 and B3 are the most significant bits. The operation of the 74F85 is described in the Function Table, showing all possible logic conditions. The upper part of the table describes the normal operation under all conditions that will occur in a single device in a series expansion scheme. In the upper part of the table the three outputs are mutually exclusive. In the lower part of the table, the outputs reflect the feed-forward conditions that exist in the parallel expansion scheme. The expansion inputs IA>B, and IA=B and IAB, A=B and AB, IA=B and IAB = Low, IA=B = High, and IAThe a 4-bit magnitude comparator that can be expanded to almost any length. It compares two 4-bit binary, BCD, or other monotonic codes and presents the three possible magnitude results at the outputs. The 4-bit inputs are weighted (A0A3) and (B0B3) where A3 and B3 are the most significant bits. The operation of the 74F85 is described in the Function Table, showing all possible logic conditions. The upper part of the table describes the normal operation under all conditions that will occur in a single device in a series expansion scheme. In the upper part of the table the three outputs are mutually exclusive. In the lower part of the table, the outputs reflect the feed-forward conditions that exist in the parallel expansion scheme. The expansion inputs IA>B, and IA=B and IAB, A=B and AB, IA=B and IAB = Low, IA=B = High, and IAThe MC54/74F85 is a 4-Bit Magnitude Comparator which compares two 4-Bit words (A 0 -A 3 , B 0 -B 3 ), A 3 , B 3 being the most significant inputs. Operation is not restricted to binary codes; the device will work with any monotonic code. Three Outputs are provided: “A greater than B” (0 A > B ), “A less than B” (0 A < B ), “A equal to B” (0 A = B ). Three Expander Inputs, I A > B , I A < B , I A = B , allow cascading without external gates. For proper compare operation, the Expan – der Inputs to the least significant position must be connected as follows: I A < B = I A > B = L, I A = B = H. For serial (ripple) expansion the 0 A > B , 0 A < B Outputs are connected respectively to the I A > B and I A = B inputs of the next most sig – nificant comparator , as shown in Figure 1. Refer to applications section of data sheet for high speed method of comparing large words.
