Description
XC6SLX45-2CSG324I XILINX IC FPGA 218 I/O 324CSPBGA RoHS
The Spartan®-6 family provides leading system integration capabili ties with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption o f previous Spartan families, and faster, more comprehensive connectivity. Bu ilt on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input look- up table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second genera tion DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, power- optimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protec tion. These features provide a low- cost programmable alternative to custom ASIC products with unprec edented ease of use. Spartan-6 FPGAs offer the best solution f or high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applicatio ns. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms t hat deliver integrated software and hardware components that ena ble designers to focus on innovation as soon as their development cycle begins.
Description
Screening Level:Industrial
Max Processing Temp:260
Maximum Operating Supply Voltage:1.26 V
Fabrication Technology:45nm (CMOS)
Device Logic Units:43661
Maximum Number of User I/Os:218
Minimum Operating Supply Voltage:1.14 V
Lead Finish:Tin/Silver/Copper
Mounting:Surface Mount
Speed Grade:2
Operating Temperature:-40 to 100 °C
Device Logic Cells:43661
Typical Operating Supply Voltage:1.2 V
- Spartan-6 LX FPGA: Logic optimized
- Designed for low cost
- Multiple efficient integrated blocks
- Optimized selection of I/O standards
- Staggered pads
- High-volume plastic wire-bonded packages
