Description
FSC 74F112N Fairchild Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Reset IC;FLIP-FLOP;DUAL DUAL J-K NEG EDGE F/F PDIP-16
The 74F112 contains two independent, high-speed JK flip- flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Trig- gering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affect- ing the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on S D or C D prevents clocking and forces Q or Q HIGH, respectively.
Product Category: Flip Flops
RoHS: RoHS Compliant Details
Number of Circuits: 2
Logic Family: F
Logic Type: J-K Flip-Flop
Polarity: Inverting/Non-Inverting
Input Type: TTL
Output Type: TTL
Propagation Delay Time: 6.5 ns
High Level Output Current: – 1 mA
Low Level Output Current: 20 mA
Supply Voltage – Max: 5.5 V
Maximum Operating Temperature: + 70 C
Mounting Style: Through Hole
Package / Case: PDIP-16
Packaging: Tube
Function: Dual Negative Edge Triggered
Height: 4.57 mm
Length: 19.3 mm
Minimum Operating Temperature: 0 C
Number of Channels: 2
Number of Input Lines: 2
Number of Output Lines: 1
Operating Supply Voltage: 4.5 V to 5.5 V
Operating Temperature Range: 0 C to + 70 C
Reset Type: Set, Reset
Series: SN74F112
Manufacturer:Fairchild Semiconductor
Datasheet:Others/74F112.pdf
